WO2019010893A1 - 阵列基板及液晶显示器 - Google Patents

阵列基板及液晶显示器 Download PDF

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Publication number
WO2019010893A1
WO2019010893A1 PCT/CN2017/111637 CN2017111637W WO2019010893A1 WO 2019010893 A1 WO2019010893 A1 WO 2019010893A1 CN 2017111637 W CN2017111637 W CN 2017111637W WO 2019010893 A1 WO2019010893 A1 WO 2019010893A1
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Prior art keywords
terminal
groove
layer
crimping
wall
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PCT/CN2017/111637
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English (en)
French (fr)
Inventor
黄翠
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武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US15/749,233 priority Critical patent/US10591788B2/en
Publication of WO2019010893A1 publication Critical patent/WO2019010893A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate and a liquid crystal display.
  • the conductive end of the non-display area of the display panel is typically formed by crimping conductive lines from the metal lines drawn from the display area to the contacts of the chip.
  • the contact of the conventional chip is usually a convex structure.
  • the present invention provides an array substrate in which the conductive particles are unstable and cause conduction between the conductive ends to cause a short circuit.
  • the invention also provides a liquid crystal display.
  • the array substrate of the present invention includes a peripheral region and a plurality of conductive ends disposed in the peripheral region, the peripheral region including a substrate, a buffer layer sequentially disposed on the substrate, an insulating layer, and an interlayer dielectric layer, and a groove extending from the interlayer dot dielectric layer to the substrate;
  • Each of the conductive ends includes a first terminal, a crimping end including a crimping layer and a second terminal disposed on the crimping layer, and a plurality of conductive particles, the first terminal including an inner wall surface laminated on the groove a connecting portion and an extension connected to the connecting portion on the interlayer dielectric layer extending from the inner wall to the periphery of the groove; the second terminal cross section is the same as the groove cross section, and the crimping layer is The first terminal extension is opposite, the second terminal is inserted into the groove, and the conductive particles are evenly sealed in a gap between the connecting portion of the first terminal and the second terminal, and crimping Within the gap between the layer and the extension The first terminal and the second terminal are now electrically connected.
  • part or all of the inner wall of the groove is a slope inclined toward the inside of the groove.
  • the groove has a V-shaped cross section
  • the second terminal is a protrusion protruding from the bonding layer.
  • the cross section of the groove is an inverted trapezoid
  • the second terminal is a protrusion protruding from the crimping layer and having an inverted trapezoidal cross section.
  • the cross section of the groove is a circular arc shape
  • the inner wall is a circular arc-shaped concave surface
  • the second terminal is a protrusion protruding from the pressure-bonding layer in a circular arc shape.
  • the inner wall of the groove comprises an inclined groove side wall and a groove bottom wall formed by the base
  • the connecting section is laminated on the groove side wall and the groove bottom wall, and is laminated on a part of the groove side wall The same angle as the side wall of the groove.
  • the first terminal is a metal layer.
  • the crimping end is formed at a contact of a chip.
  • the liquid crystal display panel of the present invention includes a display area and a non-display area, and further includes the array substrate, and a peripheral area of the array substrate is located in the non-display area.
  • the liquid crystal display is a flexible OLED or an LCD display.
  • the first terminal of the array substrate of the present invention is located on the substrate in the longitudinal direction and extends to the position of the substrate.
  • the connecting portion is disposed with a slope, so that the contact area of the entire terminal is increased, and the crimping end is crimped.
  • the area of the crimping gap between the second terminal and the first terminal is increased, and the contact area of the gap between the conductive particles is increased, which limits the flow frequency of the conductive particles to the gap between the crimping end and the first terminal, and enhances the conduction in the crimping gap. Particle uniformity and stability.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic side view showing an inner side of a conductive end of an array substrate including a first terminal according to an embodiment of the present invention
  • Figure 3 is a schematic side view of the inner side of the conductive end shown in Figure 2;
  • FIG. 4 is a schematic side view showing an inner side of a conductive end of an array substrate including a first terminal according to an embodiment of the present invention
  • Figure 5 is a schematic side view showing the inner side of the conductive end shown in Figure 4.
  • Figure 6 is a plan view of the first terminal shown in Figure 4.
  • FIG. 7 is a schematic side view showing an inner side of a conductive end of an array substrate including a first terminal according to an embodiment of the present invention
  • Figure 8 is a schematic side view showing the inner side of the conductive end shown in Figure 7.
  • the patterned patterning process described in the present application includes a patterning process such as film formation, development, exposure, etching, and the like.
  • An embodiment of the present invention provides an array substrate including a peripheral region and a plurality of conductive ends disposed in the peripheral region, the peripheral region including a substrate, a buffer layer sequentially disposed on the substrate, an insulating layer, and an interlayer dielectric layer. Also included is a groove extending from the interlayer dot dielectric layer to the substrate;
  • Each of the conductive ends includes a first terminal, a crimping layer, and a second terminal disposed on the bonding layer and a plurality of conductive particles, the first terminal including a connecting portion laminated on an inner wall surface of the groove and An extension of the connecting segment connected by the inner wall to the interlayer dielectric layer of the periphery of the groove;
  • the second terminal cross section is the same as the cross section of the groove, the crimping layer is opposite to the first terminal extending portion, the second terminal is inserted into the groove, and the conductive particles are uniformly sealed a gap between the connecting portion of the first terminal and the second terminal, and a gap between the crimping layer and the extending portion to achieve conduction between the first terminal and the second terminal.
  • part or all of the inner wall of the groove is a slope inclined toward the inside of the groove.
  • the smaller the angle value of the slope inclination the larger the area of the first terminal, which is advantageous for the contact performance of the first terminal.
  • an embodiment of the present invention provides an array substrate 100 including a peripheral region 10 and a plurality of conductive ends 20 disposed in the peripheral region 10 .
  • the peripheral region 10 includes a substrate 11.
  • the buffer layer 12, the insulating layer 13, and the interlayer dielectric layer 14 disposed on the substrate 11 are sequentially stacked, and further includes a recess 15 extending from the interlayer dot dielectric layer 14 to the substrate 11.
  • the insulating layer has a two-layer structure.
  • the substrate 11 is made of a flexible material.
  • the array substrate further includes an intermediate functional region (not shown) for providing a semiconductor layer, a source drain, an electrode, and the like.
  • the substrate 11 and the buffer layer 12, the insulating layer 13 and the interlayer dielectric layer 14 which are sequentially stacked on the substrate 11 are all extended from the intermediate portion of the array substrate.
  • the groove 15 has a V-shaped cross section, and the groove 15 includes two opposite groove side walls 151 and opposite end side walls, a groove side wall and an end side wall.
  • the groove-shaped groove body, the groove side wall 151 and the opposite end side walls are inclined away from the inside of the groove 15 to form an inclined surface.
  • Each of the conductive ends 20 includes a first terminal 21 , a crimping end and a plurality of conductive particles 24 .
  • the crimping end includes a crimping layer 22 and a second terminal 23 disposed on the crimping layer 22 .
  • the crimp end is a chip package or a chip integrated component or a contact on the chip. In this embodiment, the contacts are extended by the chip 30.
  • the first terminal 21 is a metal layer, and may be formed in the same layer as the channel of the source and the drain on the array substrate, or may be formed separately.
  • the first terminal 21 includes a connecting portion 211 laminated on an inner wall surface of the recess 15 and an extension connected to the connecting portion 211 and extending from the inner wall to the interlayer dielectric layer 14 on the periphery of the recess 15 212.
  • the portion of the first terminal 21 located in the recess has the same shape as the recess, and the extension 212 on the interlayer dielectric layer 14 is disposed around the recess 15. Since the groove side wall 151 and the end side wall are both inclined surfaces, the area of the connecting portion 212 formed on the side wall 151 of the groove and the end side wall is increased as compared with the area of the vertical surface, so that the area can be increased.
  • the effective contact area of the first terminal 21 is increased as compared with the area of the vertical surface, so that the area can be increased.
  • the second terminal 23 has the same cross section as the groove 15 , and the second terminal 23 is a convex protrusion protruding from the crimping layer 22 .
  • the crimping layer 22 is opposite to the first terminal 21 extending section 212, and the second terminal 23 is inserted into the recess 15
  • the conductive particles 24 are evenly sealed in the gap between the connecting portion 211 of the first terminal 21 and the second terminal 23, and in the gap between the crimping layer 22 and the extending portion 212 to realize the first terminal 21 and
  • the second terminal 23 is turned on.
  • the first terminal 21 of the array substrate of the present invention on the substrate 11 has a depth extending to the position of the substrate 11 in the longitudinal direction, and the connecting portion is disposed with a sloped surface in the lateral direction, thus increasing the contact area of the entire terminal when crimping After the end crimping, between the crimping layer 22 and the second terminal 23 and the first terminal 21
  • the area of the crimping gap is increased. Therefore, the contact area of the gap of the conductive conductive particles 24 is increased, and at least one conductive particle can be accommodated in the depth direction, which limits the flow frequency of the conductive particles to the gap between the crimping end and the first terminal, and enhances the crimping gap.
  • the uniformity and stability of the inner conductive particles further improve the connection stability between the first terminal 21 and the second terminal 23.
  • the groove 15 has an inverted trapezoidal cross section, and includes a groove bottom wall 152 formed by the base and surrounding the bottom wall 152.
  • the groove sidewall 153 is provided, the groove sidewall 153 is an inclined surface, and the second terminal 23 is a protrusion protruding from the crimp layer 22 in an inverted trapezoidal shape.
  • the connecting portion 211 of the first terminal 21 varies with the cross-sectional shape of the groove during the manufacturing process.
  • the connecting portion 211 of the present embodiment is laminated on the groove bottom wall 152 and the groove side wall 153, and is laminated on the groove.
  • the portion of the side wall 153 is inclined at the same angle as the groove side wall 153 to ensure the maximum area of the connecting section.
  • the second terminal of the crimping end is opposed to the connecting portion 211 of the first terminal 21 and forms a crimping gap to accommodate the conductive particles 23, and the crimping layer 22 forms a gap with the extending portion to accommodate the conductive particles 23.
  • a top view of the first terminal 21 of the present embodiment includes three regions A, B, and C, and the B region and the C region are top views of the connecting portion 211 of the first terminal 21,
  • the A area is a top view of the extension section 212.
  • the groove 15 has a circular arc shape
  • the connecting portion 211 of the first terminal 21 is an arc.
  • the inner wall 155 is a circular arc-shaped concave surface
  • the second terminal 23 is a convex protrusion protruding from the pressure-bonding layer in a circular arc shape.
  • the embodiment of the present invention further provides a liquid crystal display panel, including a display area and a non-display area, and the array substrate, wherein a peripheral area of the array substrate is located in the non-display area, and a chip with a crimping end is a liquid crystal display.
  • Driver chip Also included is a display medium layer and a counter substrate.
  • a plurality of display elements are disposed on the array substrate and the opposite substrate, and the plurality of display elements are used to generate an electric field to drive the display medium layer for image display.
  • the display medium layer is also described as an example of another display medium, such as an organic electroluminescence display (OLED).
  • the display medium layer is a liquid crystal molecular layer, that is, the display panel in the present embodiment is liquid crystal.
  • the display panel Liquid Crystal Display, LCD
  • the first terminal 21 is crimped to the crimping end and conductively conducted by the conductive particles to achieve conduction between the array substrate and the opposite substrate and the chip.
  • the buffer layer 12, the insulating layer 13, and the interlayer dielectric layer 14 of the array substrate are mainly made of SiO2 and SiNx.
  • the crimping layer of the first terminal 21 and the crimping end and the second terminal 23 are pressed by crimping of the chip contacts. If the wire is drawn in the dielectric layer display area according to the conventional design, the wire is first changed to the gate layer, and then jumped back to the dielectric layer through the smaller via structure. Since the substrate of the flexible OLED is usually flexible polyimide (PI), the expansion ratio is inconsistent with the metal layers (such as Ti/Al/Ti), SiO2 and SiNx, and the high temperature of the crimping process easily causes the multilayer structure of the array substrate. The cracking is like.
  • the first terminal of the conductive end of the present invention has a depth direction directly to the substrate through the insulating layer and the buffer layer, and the connecting portion is provided with a sloped surface, which can not only cause multi-layer cracking caused by a small high temperature, but also stabilize the stability of the conductive particles. . It should be noted that the drawings of the present invention are only schematic views, and the size and shape may be normal.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板（100），包括外围区域（10）及设于外围区域（10）的数个导电端（20），外围区域（10）包括基底（11）、依次层叠设置于基底（11）的缓冲层（12）、绝缘层（13）及层间电介质层（14），还包括由层间电介质层（14）延伸至基底（11）的凹槽（15）；每一导电端（20）包括第一端子（21）、包括压接层（22）及设于压接层（22）的第二端子（23）的压接端及数个导电粒子（24），第一端子（21）包括层叠于凹槽（15）的内壁表面的连接段（211）及与连接段（211）连接的由内壁延伸至凹槽（15）周缘的层间电介质层（14）上的延伸段（212）；压接层（22）与第一端子（21）的延伸段（212）相对，第二端子（23）插接于凹槽（15）内，导电粒子（24）均匀封于第一端子（21）的连接段（211）与第二端子（23）之间的缝隙，以及压接层（22）与延伸段（212）之间的缝隙内，实现第一端子（21）和第二端子（23）的导通。

Description

阵列基板及液晶显示器
本发明要求2017年7月10日递交的发明名称为“阵列基板及液晶显示器”的申请号2017105567159的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示屏技术领域，尤其涉及一种阵列基板以及液晶显示器。
背景技术
显示面板非显示区的导电端通常为从显示区引出的金属线与芯片的触点压接导电粒子形成。传统的芯片的触点通常为凸起结构，压接金属线时由于导电粒子中的树脂的流动，造成导电粒子在触点与金属线之间空隙处聚集，而触点与金属线压接缝隙内无导电粒子，反而使相邻的端子导通，造成短路。
发明内容
本发明提供一种导电粒子不稳定导致导电端之间导通而造成短路的阵列基板。
本发明还提供一种液晶显示器。
本发明所述的阵列基板，包括外围区域及设于所述外围区的数个导电端，所述外围区域包括基底、依次层叠设置于基底的缓冲层、绝缘层及层间电介质层，还包括由所述层间点介质层延伸至所述基底的凹槽；
每一所述导电端包括第一端子、包括压接层及设于压接层的第二端子的压接端及数个导电粒子，所述第一端子包括层叠于所述凹槽的内壁表面的连接段及与连接段连接的由所述内壁延伸至所述凹槽周缘的层间电介质层上的延伸段；所述第二端子截面与所述凹槽截面相同，所述压接层与所述第一端子延伸段相对，所述第二端子插接于所述凹槽内，所述导电粒子均匀封于所述第一端子的连接段与第二端子之间的缝隙，以及压接层与延伸段之间的缝隙内，以实 现所述第一端子与第二端子的导通。
其中，所述凹槽的内壁部分或者全部为向远离凹槽内部方向倾斜的斜面。
其中，所述凹槽的横截面为V型，所述第二端子为凸设于压接层的凸起。
其中，所述凹槽的横截面为倒置梯形，所述第二端子为凸设于压接层的截面为倒置梯形的凸起。
其中，所述凹槽的横截面为圆弧形，所述内壁为圆弧形凹面，所述第二端子为凸设于压接层的截面为圆弧形的凸起。
其中，所述凹槽的内壁包括倾斜的槽侧壁和由基底形成的槽底壁，所述连接段层叠于所述槽侧壁及槽底壁上，并且层叠于所述槽侧壁的部分与槽侧壁倾斜角度相同。
其中，所述第一端子为金属层。
其中，所述压接端形成于为芯片的触点。
本发明所述一种液晶显示屏，包括显示区和非显示区，还包括所述的阵列基板，所述阵列基板的外围区域位于所述非显示区内。
其中，所述液晶显示器为柔性OLED或者LCD显示屏。
本发明所述的阵列基板的位于基底上的第一端子在纵向上，深度延伸至基底的位置，横向上，连接段采用斜面设置，如此增加了整个端子的接触面积，当压接端压接后，第二端子与第一端子之间的压接缝隙面积增大，导电粒子所在缝隙接触面积增大，限制了导电粒子向压接端与第一端子空隙流动频率，增强压接缝隙内导电粒子的均匀性和稳定性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例所述阵列基板平面示意图；
图2为本发明一实施例的阵列基板的导电端的包含第一端子的内部侧面示意简图；
图3为图2所示的导电端的内部侧面示意简图；
图4为本发明一实施例的阵列基板的导电端的包含第一端子的内部侧面示意简图；
图5为图4所示的导电端的内部侧面示意简图；
图6为图4所示的第一端子的俯视图；
图7为本发明一实施例的阵列基板的导电端的包含第一端子的内部侧面示意简图；
图8为图7所示的导电端的内部侧面示意简图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。本申请所述的图案化构图工艺包括成膜、显影、曝光、蚀刻等构图工艺。
本发明实施例提供一种阵列基板，包括外围区域及设于所述外围区的数个导电端，所述外围区域包括基底、依次层叠设置于基底的缓冲层、绝缘层及层间电介质层，还包括由所述层间点介质层延伸至所述基底的凹槽；
每一所述导电端包括第一端子、压接层及设于压接层的第二端子及数个导电粒子，所述第一端子包括层叠于所述凹槽的内壁表面的连接段及与连接段连接的由所述内壁延伸至所述凹槽周缘的层间电介质层上的延伸段；
所述第二端子截面与所述凹槽截面相同，所述压接层与所述第一端子延伸段相对，所述第二端子插接于所述凹槽内，所述导电粒子均匀封于所述第一端子的连接段与第二端子之间的缝隙，以及压接层与延伸段之间的缝隙内，以实现所述第一端子与第二端子的导通。其中，所述凹槽的内壁部分或者全部为向远离凹槽内部方向倾斜的斜面。其中，斜面倾斜的角度值越小，所述第一端子的面积越大，这样有利于第一端子的接触性能。
具体请参阅图1与图2，本发明实施例提供一种阵列基板100，包括外围区域10及设于所述外围区域10的数个导电端20。所述外围区域10包括基底 11、依次层叠设置于基底11的缓冲层12、绝缘层13及层间电介质层14，还包括由所述层间点介质层14延伸至所述基底11的凹槽15。其中绝缘层为两层结构。所述基板11为柔性材质制成。所述阵列基板还包括中间功能区域(图未示)用于设置如半导体层、源漏极、电极等。其中所述基底11、依次层叠设置于基底11的缓冲层12、绝缘层13及层间电介质层14均为所述阵列基板中间区域延伸出来的。
请参阅图3，本发明实施例中，所述凹槽15横截面为V型，所述凹槽15包括两个相对的槽侧壁151及相对的端侧壁，槽侧壁与端侧壁围成条状的槽体，槽侧壁151及相对的端侧壁均向远离凹槽15内部方向倾斜构成倾斜面。每一所述导电端20包括第一端子21、压接端及数个导电粒子24，压接端包括压接层22及设于压接层22的第二端子23。所述压接端为芯片封装件或者芯片集成件或芯片上的触点。本实施例中，为芯片30延伸的触点。所述第一端子21为金属层，可以是所述阵列基板上的源漏极的通道工序同层形成，也可以是单独形成。
所述第一端子21包括层叠于所述凹槽15的内壁表面的连接段211及与连接段211连接的由所述内壁延伸至所述凹槽15周缘的层间电介质层14上的延伸段212。所述第一端子21位于凹槽内的部分的形状与凹槽相同，位于层间电介质层14上的延伸段212围绕所述凹槽15设置。由于槽侧壁151及端侧壁均为倾斜面，相较于竖直面面积大，那么形成于槽侧壁151及端侧壁均的连接段212的面积就增大，这样就可以增大第一端子21的有效接触面积。
所述第二端子23截面与所述凹槽15截面相同，所述第二端子23为凸设于压接层22的锥形的凸起。压接端与所述第一端子21压接时，所述压接层22与所述第一端子21延伸段212相对，所述第二端子23插接于所述凹槽15内，所述导电粒子24均匀封于所述第一端子21的连接段211与第二端子23之间的缝隙，以及压接层22与延伸段212之间的缝隙内，以实现所述第一端子21与第二端子23的导通。
本发明所述的阵列基板的位于基底11上的第一端子21在纵向上，深度延伸至基底11的位置，横向上，连接段采用斜面设置，如此增加了整个端子的接触面积，当压接端压接后，压接层22与第二端子23与第一端子21之间的 压接缝隙面积增大，因此，导电导电粒子24所在缝隙接触面积增大，深度方向上至少可以容纳一个导电粒子，限制了导电粒子向压接端与第一端子空隙流动频率，增强压接缝隙内导电粒子的均匀性和稳定性，进而提高第一端子21与第二端子23之间的连接稳定性。
请采纳语文图4与图5，本发明另一实施例中，与上述实施例不同的是，所述凹槽15的横截面为倒置梯形，包括基底形成的槽底壁152及围绕底壁152设置的槽侧壁153，所述槽侧壁153为倾斜面，所述第二端子23为凸设于压接层22的截面为倒置梯形的凸起。所述第一端子21的连接段211在制造过程中随着凹槽的截面形状而变化，本实施例的连接段211层叠于槽底壁152及槽侧壁153上，并且层叠于所述槽侧壁153的部分与槽侧壁153倾斜角度相同，以保证连接段的最大面积。压接端的第二端子与所述第一端子21的连接段211的相对并形成压接缝隙容纳导电粒子23，压接层22与所述延伸段相对形成容纳导电粒子23的缝隙。比如图，6所示，为本实施例第一端子21的俯视图，其包括A、B、C三个区域，所述B区域与C区域为所述第一端子21的连接段211的俯视图，所述A区域为延伸段212的俯视图，当连接段211的倾斜角度值越小，那么B区域的面积越大，这样就增加了第一端子21的接触面积。
请参阅图7与图8，本发明另一实施例中，与上述实施例不同的是，所述凹槽15的横截面为圆弧形，所述第一端子21的连接段211为圆弧形，所述内壁155为圆弧形凹面，所述第二端子23为凸设于压接层的截面为圆弧形的凸起。所述压接端与所述第一端子21压接时，圆弧形第二端子23与第一端子21的连接段211形成容纳导电粒子24的压接缝隙，压接层22与所述延伸段相对形成容纳导电粒子23的缝隙。
本发明实施例还提供一种液晶显示屏，包括显示区和非显示区及所述的阵列基板，所述阵列基板的外围区域位于所述非显示区内，设置压接端的芯片为液晶显示屏的驱动芯片。还包括显示介质层以及对向基板。其中，阵列基板与对向基板上设置有多个显示元件(图未示)，所示多个显示元件用于产生电场驱动显示介质层进行图像显示。本实施例中，显示介质层还以为其他显示介质，例如有机发光材料(Organic Electroluminesence Display，OLED)为例进行说明。当然，可变更地，显示介质层为液晶分子层，也即是本实施中显示面板以液晶 显示面板(Liquid Crystal Display，LCD)或者其他显示材料，并不以此为限。所述第一端子21与压接端压接并通过导电粒子导通实现阵列基板与对向基板与芯片的导通。
所述阵列基板的缓冲层12、绝缘层13及层间电介质层14，这些结构主要为SiO2和SiNx制成。通过芯片触点的压接，使第一端子21与压接端的压接层和第二端子23进行压合。如果按照常规设计该线金属线在介电层显示区引出之后，先换线到栅极层，再通过较小的过孔结构跳回介电层显。由于柔性OLED的基底通常是柔性的聚酰亚胺(PI)，其膨胀率与金属层(如Ti/Al/Ti)、SiO2和SiNx不一致，压接过程的高温易造成阵列基板的多层结构的开裂如。本发明所述的导电端的第一端子深度方向直接到基底穿过绝缘层和缓冲层，而且连接段采用斜面设置，不但可以较小高温造成的多层开裂现象，而且可以稳固导电粒子的稳定性。需要说明的是，本发明的附图只是示意图，大小形状可能存在尺寸差皆为正常。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (17)

  1. 一种阵列基板，其中，包括外围区域及设于所述外围区的数个导电端，所述外围区域包括基底、依次层叠设置于基底的缓冲层、绝缘层及层间电介质层，还包括由所述层间点介质层延伸至所述基底的凹槽；
    每一所述导电端包括第一端子、包括压接层及设于压接层的第二端子的压接端及数个导电粒子，所述第一端子包括层叠于所述凹槽的内壁表面的连接段及与连接段连接的由所述内壁延伸至所述凹槽周缘的层间电介质层上的延伸段；
    所述第二端子截面与所述凹槽截面相同，所述压接层与所述第一端子延伸段相对，所述第二端子插接于所述凹槽内，所述导电粒子均匀封于所述第一端子的连接段与第二端子之间的缝隙，以及压接层与延伸段之间的缝隙内，以实现所述第一端子与第二端子的导通。
  2. 如权利要求1所述的阵列基板，其中，所述凹槽的内壁部分或者全部为向远离凹槽内部方向倾斜的斜面。
  3. 如权利要求2所述的阵列基板，其中，所述凹槽的横截面为V型，所述第二端子为凸设于压接层的凸起。
  4. 如权利要求2所述的阵列基板，其中，所述凹槽的横截面为倒置梯形，所述第二端子为凸设于压接层的截面为倒置梯形的凸起。
  5. 如权利要求2所述的阵列基板，其中，所述凹槽的横截面为圆弧形，所述内壁为圆弧形凹面，所述第二端子为凸设于压接层的截面为圆弧形的凸起。
  6. 如权利要求4所述的阵列基板，其中，所述凹槽的内壁包括倾斜的槽侧壁和由基底形成的槽底壁，所述连接段层叠于所述槽侧壁及槽底壁上，并且层叠于所述槽侧壁的部分与槽侧壁倾斜角度相同。
  7. 如权利要求1所述的阵列基板，其中，所述第一端子为金属层。
  8. 如权利要求1所述的阵列基板，其中，所述压接端形成于为芯片的触点。
  9. 一种液晶显示屏，包括显示区和非显示区，其中，还包括阵列基板， 阵列基板包括外围区域及设于所述外围区的数个导电端，所述外围区域包括基底、依次层叠设置于基底的缓冲层、绝缘层及层间电介质层，还包括由所述层间点介质层延伸至所述基底的凹槽；
    每一所述导电端包括第一端子、包括压接层及设于压接层的第二端子的压接端及数个导电粒子，所述第一端子包括层叠于所述凹槽的内壁表面的连接段及与连接段连接的由所述内壁延伸至所述凹槽周缘的层间电介质层上的延伸段；
    所述第二端子截面与所述凹槽截面相同，所述压接层与所述第一端子延伸段相对，所述第二端子插接于所述凹槽内，所述导电粒子均匀封于所述第一端子的连接段与第二端子之间的缝隙，以及压接层与延伸段之间的缝隙内，以实现所述第一端子与第二端子的导通；所述阵列基板的外围区域位于所述非显示区内。
  10. 如权利要求9所述的液晶显示屏，其中，所述凹槽的内壁部分或者全部为向远离凹槽内部方向倾斜的斜面。
  11. 如权利要求10所述的液晶显示屏，其中，所述凹槽的横截面为V型，所述第二端子为凸设于压接层的凸起。
  12. 如权利要求10所述的液晶显示屏，其中，所述凹槽的横截面为倒置梯形，所述第二端子为凸设于压接层的截面为倒置梯形的凸起。
  13. 如权利要求10所述的液晶显示屏，其中，所述凹槽的横截面为圆弧形，所述内壁为圆弧形凹面，所述第二端子为凸设于压接层的截面为圆弧形的凸起。
  14. 如权利要求12所述的液晶显示屏，其中，所述凹槽的内壁包括倾斜的槽侧壁和由基底形成的槽底壁，所述连接段层叠于所述槽侧壁及槽底壁上，并且层叠于所述槽侧壁的部分与槽侧壁倾斜角度相同。
  15. 如权利要求9所述的液晶显示屏，其中，所述第一端子为金属层。
  16. 如权利要求9所述的液晶显示屏，其中，所述压接端形成于为芯片的触点。
  17. 如权利要求9所述的液晶显示屏，其中，所述液晶显示器为柔性OLED或者LCD显示屏。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107153307B (zh) * 2017-07-10 2020-08-04 武汉华星光电半导体显示技术有限公司 阵列基板及液晶显示器
US10591788B2 (en) 2017-07-10 2020-03-17 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Array substrate and liquid crystal display panel
CN108649350A (zh) * 2018-04-23 2018-10-12 武汉华星光电半导体显示技术有限公司 一种导电端子及显示装置
CN108987439A (zh) * 2018-06-21 2018-12-11 武汉华星光电半导体显示技术有限公司 显示面板和显示装置
CN109065507B (zh) 2018-08-09 2020-08-04 武汉华星光电半导体显示技术有限公司 显示面板
CN110007514A (zh) * 2019-03-26 2019-07-12 武汉华星光电技术有限公司 背光源贴合结构及显示装置
CN113589570B (zh) * 2021-07-23 2022-11-04 Tcl华星光电技术有限公司 显示面板及液晶显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1264494A (zh) * 1997-07-15 2000-08-23 株式会社日立制作所 半导体装置、其安装结构体及其制造方法
JP2003264352A (ja) * 2002-03-07 2003-09-19 Fujikura Ltd 配線基板間の接続における位置ずれ防止構造
KR20090098076A (ko) * 2008-03-13 2009-09-17 주식회사 하이닉스반도체 플립 칩 패키지
JP2012049398A (ja) * 2010-08-27 2012-03-08 Fujifilm Corp 導電接合構造、実装構造体及び導電接合方法
JP2017004715A (ja) * 2015-06-09 2017-01-05 デクセリアルズ株式会社 異方性導電接続構造体、異方性導電材料、および異方性導電接続方法
CN106405892A (zh) * 2016-10-24 2017-02-15 昆山国显光电有限公司 平板显示装置的压接结构和压接方法
CN107153307A (zh) * 2017-07-10 2017-09-12 武汉华星光电半导体显示技术有限公司 阵列基板及液晶显示器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1264494A (zh) * 1997-07-15 2000-08-23 株式会社日立制作所 半导体装置、其安装结构体及其制造方法
JP2003264352A (ja) * 2002-03-07 2003-09-19 Fujikura Ltd 配線基板間の接続における位置ずれ防止構造
KR20090098076A (ko) * 2008-03-13 2009-09-17 주식회사 하이닉스반도체 플립 칩 패키지
JP2012049398A (ja) * 2010-08-27 2012-03-08 Fujifilm Corp 導電接合構造、実装構造体及び導電接合方法
JP2017004715A (ja) * 2015-06-09 2017-01-05 デクセリアルズ株式会社 異方性導電接続構造体、異方性導電材料、および異方性導電接続方法
CN106405892A (zh) * 2016-10-24 2017-02-15 昆山国显光电有限公司 平板显示装置的压接结构和压接方法
CN107153307A (zh) * 2017-07-10 2017-09-12 武汉华星光电半导体显示技术有限公司 阵列基板及液晶显示器

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