KR20180026613A - 반도체 칩, 이를 구비한 전자장치 및 반도체 칩의 연결방법 - Google Patents

반도체 칩, 이를 구비한 전자장치 및 반도체 칩의 연결방법 Download PDF

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KR20180026613A
KR20180026613A KR1020160113476A KR20160113476A KR20180026613A KR 20180026613 A KR20180026613 A KR 20180026613A KR 1020160113476 A KR1020160113476 A KR 1020160113476A KR 20160113476 A KR20160113476 A KR 20160113476A KR 20180026613 A KR20180026613 A KR 20180026613A
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South Korea
Prior art keywords
bumps
semiconductor chip
connection pads
conductive
insulating layer
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KR1020160113476A
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English (en)
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KR102627991B1 (ko
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하승화
조정연
김병용
양정도
황정호
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삼성디스플레이 주식회사
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Priority to KR1020160113476A priority Critical patent/KR102627991B1/ko
Priority to US15/685,640 priority patent/US10643931B2/en
Publication of KR20180026613A publication Critical patent/KR20180026613A/ko
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Abstract

본 발명의 실시예에 의한 반도체 칩은, 베이스 기판과, 상기 베이스 기판의 일면 상에 배치된 적어도 하나의 도전성 패드와, 상기 도전성 패드가 배치된 상기 베이스 기판의 일면 상에 배치되며 상기 도전성 패드의 일 영역을 노출하는 개구부를 가지는 절연층과, 상기 개구부에 의해 노출되는 상기 도전성 패드의 일 영역 상부 및 상기 개구부 주변의 절연층 상부에 배치되며 상기 개구부에 대응하는 오목부를 가지는 적어도 하나의 범프를 포함하며, 상기 범프는 장변방향을 따라 나열된 복수의 오목부들을 가진다.

Description

반도체 칩, 이를 구비한 전자장치 및 반도체 칩의 연결방법{SEMICONDUCTOR CHIP, ELECTRONIC DEVICE HAVING THE SAME AND CONNECTING METHOD OF THE SEMICONDUCTOR CHIP}
본 발명의 실시예는 반도체 칩, 이를 구비한 전자장치 및 반도체 칩의 연결방법에 관한 것이다.
최근, 전자장치의 고성능화 및 고집적화에 따라, 반도체 칩에 구비되는 접속 단자들의 개수가 비약적으로 증가하고 있다. 이에 따라, 미세 피치(fine pitch)를 가진 반도체 칩에 대한 수요가 급증하고 있다.
이러한 미세 피치(fine pitch)를 가지는 반도체 칩을 이방성 전도성 필름(anisotropic conductive film; 이하, 'ACF'로 약기함)과 같은 접착제를 이용하여 표시패널 등의 전자장치에 실장하는 경우, 쇼트 결함이나 오픈 불량이 발생할 확률이 증가하게 된다. 일례로, ACF 내부에 포함된 도전 입자가 반도체 칩에 구비된 접속 단자들, 예컨대 범프들의 측면에 밀집되어 인접한 범프들 사이의 쇼트 결함을 야기하거나, 혹은 ACF의 도전 입자가 미세 크기를 가지는 적어도 일부의 범프에 대응하는 위치에 적절히 배치되지 않아 오픈 불량을 유발할 수 있다.
한편, 반도체 칩과 상기 반도체 칩이 실장되는 전자장치 사이의 저저항 특성을 확보하기 위하여, 고압의 공법을 적용하여 반도체 칩을 전자장치에 실장할 수 있다. 하지만, 이와 같이 고압의 공법을 적용하게 되면, 반도체 칩 및/또는 전자장치에 구비된 범프들, 접속 패드들 및/또는 배선들의 크랙을 유발할 수 있다.
본 발명이 이루고자 하는 기술적 과제는, 전자장치의 접속 패드에 용이하게 직접 접합될 수 있는 구조의 범프를 구비한 반도체 칩, 이를 구비한 전자장치 및 반도체 칩의 연결방법을 제공하는 것이다.
본 발명의 실시예에 의한 반도체 칩은, 베이스 기판과, 상기 베이스 기판의 일면 상에 배치된 적어도 하나의 도전성 패드와, 상기 도전성 패드가 배치된 상기 베이스 기판의 일면 상에 배치되며 상기 도전성 패드의 일 영역을 노출하는 개구부를 가지는 절연층과, 상기 개구부에 의해 노출되는 상기 도전성 패드의 일 영역 상부 및 상기 개구부 주변의 절연층 상부에 배치되며 상기 개구부에 대응하는 오목부를 가지는 적어도 하나의 범프를 포함하며, 상기 범프는 장변방향을 따라 나열된 복수의 오목부들을 가진다.
실시예에 따라, 상기 절연층은, 상기 범프의 장변방향의 일 라인 상에 나란히 배치된 복수의 제1 개구부들을 가질 수 있다.
실시예에 따라, 상기 제1 개구부들 각각은 상기 범프의 장변방향과 교차하는 방향으로 연장될 수 있다.
실시예에 따라, 상기 절연층은, 상기 범프에 대응하는 각각의 범프 영역 내에서 상기 장변방향으로 연장되며 상기 제1 개구부들을 일체로 연결하는 적어도 하나의 제2 개구부를 더 가질 수 있다.
실시예에 따라, 상기 범프는 한 층 이상의 금속층을 포함할 수 있다.
실시예에 따라, 상기 반도체 칩은 상기 도전성 패드와 상기 범프 사이에 구비되는 도전성 매개층을 더 포함할 수 있다.
실시예에 따라, 상기 범프는 5㎛ 내지 20㎛의 폭을 가지고, 상기 오목부들 각각은 1㎛ 내지 4㎛의 깊이를 가질 수 있다.
실시예에 따라, 상기 절연층은, 각각 한 층 이상의 무기막 및 유기막을 포함하는 다층 구조를 가질 수 있다.
실시예에 따라, 상기 오목부들 각각은 상기 절연층의 높이에 대응하는 깊이를 가질 수 있다.
본 발명의 실시예에 의한 전자장치는, 적어도 제1 금속을 포함하는 다수의 접속 패드들이 제공된 기판과, 상기 접속 패드들 각각과 마주하도록 배치되어 상기 접속 패드들에 전기적으로 연결되며 적어도 제2 금속을 포함하는 다수의 범프들이 제공된 반도체 칩과, 상기 접속 패드들과 상기 범프들의 사이에 제공되며 상기 제1 금속과 상기 제2 금속이 혼합된 도전성 접합층을 포함한다.
실시예에 따라, 상기 반도체 칩은, 베이스 기판과, 상기 접속 패드들을 향하는 상기 베이스 기판의 일면 상에 상기 범프들 각각에 대응하도록 배치되며 해당 범프에 전기적으로 연결되는 다수의 도전성 패드들과, 상기 도전성 패드들이 제공된 상기 베이스 기판의 일면 상에 배치되며 상기 범프들과 상기 도전성 패드들의 사이에서 상기 범프들 각각의 장변방향의 일 라인 상에 배치된 복수의 제1 개구부들을 가지는 절연층을 더 포함할 수 있다.
실시예에 따라, 상기 제1 개구부들 각각은 상기 범프의 장변방향과 교차하는 방향으로 연장될 수 있다.
실시예에 따라, 상기 전자장치는 상기 기판을 포함한 표시패널을 구비할 수 있다.
본 발명의 실시예에 의한 반도체 칩의 연결방법은, 적어도 장변방향에서 복수의 돌기들 및 오목부들을 가지는 다수의 범프들을 구비하는 반도체 칩을 마련하는 단계와, 상기 범프들에 대응하는 다수의 접속 패드들을 구비하는 기판을 마련하는 단계와, 상기 범프들과 상기 접속 패드들이 서로 마주하도록 상기 반도체 칩을 상기 기판 상에 배치하는 단계와, 상기 반도체 칩에 소정의 진동 및 압력을 가하면서, 상기 범프들 및 상기 접속 패드들을 접합하는 단계를 포함한다.
실시예에 따라, 상기 범프들 및 상기 접속 패드들을 접합하는 단계는, 상기 반도체 칩에 초음파 범위의 진동을 가하면서 상기 범프들과 상기 접속 패드들을 마찰시켜 상기 돌기들 및 상기 접속 패드들의 일부를 용융시키는 단계와, 상기 범프들 및 상기 접속 패드들의 사이에 상기 범프들에 포함된 금속과 상기 접속 패드들에 포함된 금속이 혼합된 도전성 접합층을 형성하는 단계를 포함할 수 있다.
본 발명의 실시예에 의하면, 표면에 복수의 오목부들을 가지는 범프를 구비한 반도체 칩, 이를 구비한 전자장치 및 반도체 칩의 연결방법을 제공한다. 이러한 본 발명의 실시예에 의하면, 서로 대응하는 범프와 접속 패드 사이의 직접 접합을 용이하게 할 수 있다. 따라서, ACF 등을 이용하지 않고도 반도체 칩을 전자장치의 접속 패드에 안정적으로 연결할 수 있으며, 저압 조건에서도 범프와 접속 패드를 용이하게 접합할 수 있다. 또한, 직접 접합 구조를 통해 저저항 특성을 확보할 수 있다.
도 1a 및 도 1b는 본 발명의 일 실시예에 의한 반도체 칩의 사시도이다.
도 2는 도 1a 및 도 1b에 도시된 반도체 칩의 일 영역을 확대 도시한 사시도이다.
도 3a 내지 도 3g는 본 발명의 일 실시예에 의한 범프의 사시도이다.
도 4a 및 도 4b는 도 2에 도시된 반도체 칩의 I-I' 선 및 Ⅱ-Ⅱ' 선에 따른 단면의 일례를 도시한 단면도이다.
도 5a 내지 도 5f는 본 발명의 일 실시예에 의한 절연층의 평면도이다.
도 6은 도 2에 도시된 반도체 칩의 I-I' 선에 따른 단면의 다른 예를 도시한 단면도이다.
도 7은 본 발명의 일 실시예에 의한 전자장치의 사시도이다.
도 8은 도 7의 Ⅲ-Ⅲ' 선에 따른 단면의 일례를 개략적으로 도시한 단면도이다.
도 9는 본 발명의 일 실시예에 의한 반도체 칩의 연결방법을 설명하기 위한 단면도이다.
도 10은 도 9의 일 영역을 확대하여 도시한 단면도이다.
이하, 첨부된 도면을 참조하여 본 발명의 실시예 및 그 밖에 당업자가 본 발명의 내용을 쉽게 이해하기 위하여 필요한 사항에 대하여 상세히 설명하기로 한다. 다만, 하기에 설명하는 실시예는 그 표현 여부에 관계없이 예시적인 것에 불과하다. 즉, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 다양한 형태로 변경되어 실시될 수 있을 것이다.
한편, 도면에서 본 발명의 특징과 직접적으로 관계되지 않은 일부 구성요소는 본 발명을 명확하게 나타내기 위하여 생략되었을 수 있다. 또한, 도면 상의 일부 구성요소는 그 크기나 비율 등이 다소 과장되어 도시되었을 수 있다. 도면 전반에서 동일 또는 유사한 구성요소들에 대해서는 비록 다른 도면 상에 표시되더라도 가능한 한 동일한 참조번호 및 부호를 부여하였다.
도 1a 및 도 1b는 본 발명의 일 실시예에 의한 반도체 칩의 사시도이다. 그리고, 도 2는 도 1a 및 도 1b에 도시된 반도체 칩의 일 영역을 확대 도시한 사시도이다. 편의상, 도 1a 내지 도 1b와 도 2에서는, 반도체 칩의 구성요소들 중 베이스 기판과, 상기 베이스 기판의 일면에 배치된 범프들만을 개략적으로 도시하기로 한다.
도 1a 및 도 1b를 참조하면, 본 발명의 일 실시예에 의한 반도체 칩(100)은, 베이스 기판(110)과, 상기 베이스 기판(110)의 일면 상에 배치된 적어도 하나의 범프(120)를 포함한다. 실시예에 따라, 반도체 칩(100)은 베이스 기판(110)의 동일한 일면(예컨대, 하부면)에 소정 피치로 배열된 다수의 범프들(120)을 구비할 수 있다.
실시예에 따라, 베이스 기판(110)은 실리콘 웨이퍼(Silicon Wafer)일 수 있다. 다만, 베이스 기판(110)이 이에 한정되지는 않으며, 베이스 기판(110)의 재질 및 형상 등은 변경될 수 있다. 실시예에 따라, 베이스 기판(110)에는, 도시되지 않은 다양한 회로소자들 및/또는 배선들이 배치되는 회로층이 내재될 수 있다.
이러한 베이스 기판(110)의 적어도 일면에는, 상기 회로소자들 및/또는 배선들을 전자장치(일례로, 표시패널)에 전기적으로 연결하기 위한 적어도 하나의 범프(120)가 구비될 수 있다. 실시예에 따라, 범프(120)는 금속 범프일 수 있다.
실시예에 따라, 베이스 기판(110)의 일면에는 입/출력신호를 전달하기 위한 입/출력 범프들을 포함한 다수의 범프들(120)이 구비될 수 있다. 일례로, 베이스 기판(110)의 일면에는 각각 적어도 한 행의 입력 범프들 및 출력 범프들이 구비되고, 입력 범프들 및 출력 범프들은 일정 거리 이상 이격되어 배열될 수 있다.
한편, 도 1a 및 도 1b에서는 가로 방향 및 세로 방향을 따라 반도체 칩(100)의 일면에 범프들(120)이 규칙적으로 배열된 실시예를 도시하였으나, 본 발명이 이에 한정되지는 않는다. 즉, 범프들(120)의 크기(예컨대, 길이, 폭 및 높이), 개수, 배열구조 및/또는 범프들(120) 사이의 피치 등은 다양하게 변경 실시될 수 있다. 일례로, 범프들(120)은 지그재그로 배열될 수도 있다.
도 2를 참조하면, 실시예에 따라, 범프들(120) 각각의 표면은 복수의 돌기들(122) 및 오목부들(124)로 이루어진 요철구조를 가진다. 실시예에 따라, 오목부들(124)은 범프들(120)의 일 표면에 형성된 딤플들일 수 있다.
특히, 본 발명의 실시예에서, 범프들(120) 각각은 장변방향(길이방향; 예컨대, y 방향)을 따라 나열된 복수의 오목부들(124)을 가지며, 이에 따라 범프들(120) 각각의 장변방향에는 복수의 돌기들(122)이 배치된다. 한편, 범프들(120) 각각은, 단변방향(예컨대, x 방향)에서 적어도 하나의 오목부(124)를 가지며, 이에 따라 단변방향에는 적어도 두 개의 돌기들(122)이 배치된다.
이와 같이 범프들(120)이 적어도 장변방향을 따라 복수의 오목부들(124)을 가지게 되면, 반도체 칩(100)을 표시패널과 같은 전자장치에 전기적으로 연결함에 있어서, 범프들(120)을 전자장치의 접속 패드에 용이하게 직접 접합할 수 있다. 보다 구체적으로, 전자장치의 접속 패드에 접합되는 범프들(120)의 표면이 요철구조를 가지며, 특히 장변방향을 따라 복수의 오목부들(124)을 가지게 되면, 접합공정의 초기에, 접합 계면에 배치되는 다수의 돌기들(122)에 압력을 집중시킬 수 있다. 이에 따라, 접합 계면에 보다 큰 마찰 에너지를 유도할 수 있다. 따라서, 저압 조건에서도 범프들(120)을 용이하게 전자장치의 접속 패드에 직접 접합할 수 있으며, 그 접합의 질을 향상시킬 수 있다.
한편, 범프들(120)을 전자장치의 접속 패드에 직접 접합하여 도통시키는 경우, ACF와 같이 도전입자를 포함하는 접착제를 이용하지 않아도 된다. 따라서, 범프들(120)이 미세한 크기, 예컨대, 미세한 폭(단변방향의 길이), 길이(장변방향의 길이) 및/또는 높이를 가지거나, 범프들(120) 사이의 피치가 일례로 10㎛ 내지 15㎛ 이하 수준으로 미세하더라도 범프들(120)과 이에 대응하는 전자장치의 접속 패드들 사이를 안정적으로 연결할 수 있다. 또한, 직접 접합 구조를 통해 범프들(120)과 접속 패드들의 사이에서 저저항 특성을 확보할 수 있다.
실시예에 따라, 범프들(120) 각각은 5㎛ 내지 20㎛의 폭을 가질 수 있다. 범프들(120) 각각이 5㎛ 미만의 폭을 가질 경우에는 접합 공정에 어려움이 있을 수 있다. 따라서, 범프들(120) 각각의 폭을 5㎛ 이상으로 설계함으로써, 안정적인 접합이 가능하도록 한다. 한편, 범프들(120) 각각이 20㎛보다 큰 폭을 가질 경우에는 집적도가 낮아질 수 있으며, 미세 피치 조건을 만족하지 못할 수 있다.
본 발명의 실시예에서는 범프들(120) 각각에 복수의 돌기들(122) 및 오목부들(124)을 형성함으로써, 접합 공정의 초기에는 돌기들(122)에 압력이 집중되어 마찰 에너지를 상승시킬 수 있다. 또한, 돌기들(122)이 용융되면서 접속 패드들의 표면과 결합하여 확산층(diffusion layer)을 형성하기 시작하면, 범프들(120)과 이에 대응하는 접속 패드들의 사이에 면 접촉의 형태로 도전성 접합층이 형성될 수 있다. 이때, 본 발명의 실시예와 같이 범프들(120) 각각의 표면에 다수의 돌기들(122) 및 오목부들(124)이 존재하게 되면, 범프들(120)과 접속 패드들 사이의 마찰계면이 증가하여 비교적 낮은 압력이 가해지더라도 양질의 접합층이 형성되도록 할 수 있다. 이에 따라, 범프들(120)과 접속 패드들 사이에 안정적인 접속 구조를 제공할 수 있다.
도 3a 내지 도 3g는 본 발명의 일 실시예에 의한 범프의 사시도이다. 이중, 도 3a 내지 도 3c는 범프들의 일면에 형성된 오목부들이 범프들의 외측벽까지 연장된 실시예를 개시한 것으로서, 반도체 칩이 전자장치에 실장될 때 범프들이 향하는 방향을 고려하여 오목부들이 형성된 범프의 표면이 하부를 향하도록 도시한 것이다. 한편, 도 3d 내지 도 3g는 범프들의 일면에 형성된 오목부들이 돌기에 둘러싸인 실시예를 개시한 것으로서, 오목부들의 형상을 보여주기 위하여 오목부들이 형성된 범프의 표면이 상부를 향하도록 도시한 것이다.
도 3a 내지 도 3g를 참조하면, 범프들(120) 각각은, 복수의 오목부들(124)을 구비한다. 실시예에 따라, 범프들(120) 각각의 표면에 형성되는 오목부들(124)의 크기(면적 및/또는 깊이), 모양, 개수 및/또는 배치구조는 다양하게 변경 실시될 수 있다. 예컨대, 범프들(120) 각각은 도 3a 내지 도 3g에 도시된 실시예 중 어느 하나의 실시예에 부합되는 요철구조의 표면을 가지거나, 혹은 이 외에 다양한 형태로 변형된 요철구조의 표면을 가질 수 있다.
실시예에 따라, 범프들(120) 각각의 표면에서, 복수의 오목부들(124)이 서로 연결되거나, 혹은 서로 분리될 수 있다. 또한, 실시예에 따라, 범프들(120) 각각의 표면에 구비되는 돌기들(122)의 형상은 다양하게 변경 실시될 수 있다. 예컨대, 돌기들(122)은 점 형태의 뾰족한 팁을 가지거나, 선 혹은 면 형태의 완만한 팁을 가질 수 있다.
다만, 본 발명의 실시예에서는, 범프들(120)의 적어도 장변방향(길이방향)에 복수의 오목부들(124)이 구비된다. 이에 따라, 범프들(120)의 장변방향에는 다수의 돌기들(122)이 형성된다. 이러한 범프들(120)을 구비한 반도체 칩(100)을 전자장치의 접속 패드에 직접 접합시키고자 할 때, 접합 공정의 초기에는 반도체 칩(100)에 가해지는 하중이 범프들(120)의 표면 전체가 아니라 돌기들(122)에 집중되게 된다. 보다 구체적으로, 압력(P)은 하중(F)에 비례하고 단면적(A)에는 반비례하므로, 반도체 칩(100)에 동일한 정도의 하중(F)이 가해진다 하더라도, 접합 공정의 초기에는 실제 마찰이 돌기들(122)에서만 발생하여 돌기들(122)에 가해지는 압력(P)은 상승하게 된다. 즉, 본 발명의 실시예에서는 범프들(120)의 표면에 복수의 오목부들(124)을 형성함으로써, 접합공정의 초기 단계에서 접속 패드와의 접촉 면적을 감소시키는 방식으로 돌기들(122)에 가해지는 압력(P)을 상승시킨다. 이에 따라, 마찰계면에 더 큰 마찰 에너지를 유도할 수 있다.
이에 따라, 돌기들(122)로 구성되는 접합 계면에 보다 큰 마찰 에너지를 유도하여 접합을 용이하게 할 수 있다. 따라서, 고압의 공법을 적용하지 않고도 반도체 칩(100)을 전자장치에 용이하게 연결할 수 있다.
또한, 범프들(120)이 적어도 장변방향(길이방향)에서 복수의 오목부들(124)을 구비하므로, 범프들(120)의 표면적이 효과적으로 증가될 수 있다. 이에 따라, 마찰 에너지에 의해 돌기들(122)이 용융되면서 전자장치의 접속 패드와의 사이에 접합층을 형성할 때, 접합량을 충분히 확보할 수 있다. 따라서, 접합층을 용이하게 형성함은 물론, 접합층에 의한 고상(solid state) 접합의 질을 향상시킬 수 있게 된다. 실시예에 따라, 범프들(120)에 형성되는 오목부들(124)의 크기, 개수 및/또는 피치 등은 접합단계에서 적용될 수 있는 하중 및 압력의 범위에 따라 다양하게 변경될 수 있다. 예컨대, 전자장치의 크기, 해상도 및/또는 재질 등을 고려하여 접합 시 적용할 수 있는 하중의 범위 및 실제 필요한 접합 압력을 산출하고, 범프들(120) 각각에 형성될 오목부들(124)의 크기, 개수 및/또는 피치 등을 결정할 수 있다.
또한, 실시예에 따라, 범프들(120)은 단변방향에서도 복수의 오목부들(124)을 구비할 수 있다. 이 경우, 단변방향에도 세 개 이상의 돌기(122)가 형성되며, 이에 따라 반도체 칩(100)과 전자장치의 접속 패드 사이에 접합층을 용이하게 형성할 수 있다.
도 4a 및 도 4b는 도 2에 도시된 반도체 칩의 I-I' 선 및 Ⅱ-Ⅱ' 선에 따른 단면의 일례를 도시한 단면도이다. 보다 구체적으로, 도 4a는 범프의 단변방향(예컨대, x 방향)을 따른 단면의 일례를 나타낸 것이고, 도 4b는 범프의 장변방향(예컨대, y 방향)을 따른 단면의 일례를 나타낸 것이다.
도 4a를 참조하면, 반도체 칩(100)은, 베이스 기판(110)과, 상기 베이스 기판(110)의 일면 상에 배치된 적어도 하나의 도전성 패드(112)와, 상기 도전성 패드(112) 상의 적어도 일 영역에 배치된 절연층(114), 도전성 매개층(116) 및 범프(120)를 포함한다. 실시예에 따라, 도전성 매개층(116) 및 범프(120)는 이에 대응하는 도전성 패드(112)와 중첩되도록 도전성 패드(112)의 일면(예컨대, 상부면) 상에 배치될 수 있다. 실시예에 따라, 도전성 매개층(116) 및 범프(120)는 절연층(114)에 의해 커버되지 않는 도전성 패드(112)의 일 영역을 통해 상기 도전성 패드(112)에 전기적으로 연결될 수 있다.
실시예에 따라, 도전성 패드(112)는 한 층 이상의 도전층, 일례로 금속층을 포함할 수 있다. 한편, 도전성 패드(112)의 재질이 반드시 금속에 한정되지는 않으며, 도전성 패드(112)의 재질은 변경될 수 있다. 예컨대, 도전성 패드(121)는 금속, 이들의 합금, 도전성 고분자, 도전성 금속 산화물 중 적어도 하나를 포함할 수 있다.
실시예에 따라, 도전성 패드(112)를 구성할 수 있는 금속으로는, 구리(Cu), 은(Ag), 금(Au), 백금(Pt), 팔라듐(Pd), 니켈(Ni), 주석(Sn), 알루미늄(Al), 코발트(Co), 로듐(Rh), 이리듐(Ir), 철(Fe), 루테늄(Ru), 오스뮴(Os), 망간(Mn), 몰리브덴(Mo), 텅스텐(W), 니오브(Nb), 탄탈럼(Ta), 타이타늄(Ti), 비스머스(Bi), 안티몬(Sb), 납(Pb) 등을 들 수 있다. 실시예에 따라, 도전성 패드(112)를 구성할 수 있는 도전성 고분자로는 폴리티오펜계, 폴리피롤계, 폴리아닐린계, 폴리아세틸렌계, 폴리페닐렌계 화합물 및 이들의 혼합물 등을 들 수 있다. 특히, 폴리티오펜계 중에서는 PEDOT/PSS 화합물을 사용할 수 있다. 실시예에 따라, 도전성 패드(112)를 구성할 수 있는 도전성 금속 산화물로는 ITO(Indium Tin Oxide), IZO(Indium Zinc Oxide), AZO(Antimony Zinc Oxide), ITZO(Indium Tin Zinc Oxide), ZnO(Zinc Oxide), SnO2(Tin Oxide) 등을 들 수 있다. 또한, 전술한 도전성 물질 외에도 도전성을 제공할 수 있는 재료이면 도전성 패드(112)를 구성하는 물질로 이용될 수 있다.
실시예에 따라, 도전성 패드(112)가 형성되는 영역의 면적은 도전성 매개층(116) 및 범프(120)가 형성되는 영역의 면적보다 클 수 있으나, 이에 한정되지는 않는다. 다만, 도전성 패드(112)는 절연층(114), 도전성 매개층(116) 및/또는 범프(120)에 의해 덮이게 되고, 이에 따라 외부로 노출되지는 않을 수 있다.
실시예에 따라, 도전성 패드(112)의 일 영역의 상부에는 절연층(114)이 구비될 수 있다. 이러한 절연층(114)은 도전성 패드(112)의 적어도 일 영역(예컨대, 본딩 영역 혹은 컨택 영역)을 노출하는 개구부(OP)를 가질 수 있다. 예컨대, 절연층(114)은, 도전성 패드(112)의 중앙부를 노출하면서 도전성 패드(112)의 가장자리 영역만을 덮도록 패터닝될 수 있다. 즉, 절연층(114)은 도전성 패드(112)가 배치된 베이스 기판(110)의 일면 상에 배치되되, 도전성 패드(112)의 일 영역(예컨대, 중앙 영역)을 노출하는 개구부(OP)를 가질 수 있다. 이러한 절연층(114)은 반도체 칩(100)을 보호하는 패시베이션막으로서 구비될 수 있다.
실시예에 따라, 절연층(114)은 한 층 이상의 산화막 혹은 질화막을 포함할 수 있으나, 이에 한정되지는 않는다. 예컨대, 절연층(114)은 실리콘 질화막(SiNx) 및/또는 실리콘 산화막(SiO2)으로 구성될 수 있다.
실시예에 따라, 절연층(114)에 의해 노출된 도전성 패드(112)의 상부에는 도전성 매개층(116)이 제공될 수 있다. 실시예에 따라, 도전성 매개층(116)은 한 층 이상의 금속층으로 구현될 수 있다. 예컨대, 도전성 매개층(116)은 구리(Cu), 은(Ag), 금(Au), 백금(Pt), 팔라듐(Pd), 니켈(Ni), 주석(Sn), 알루미늄(Al), 코발트(Co), 로듐(Rh), 이리듐(Ir), 철(Fe), 루테늄(Ru), 오스뮴(Os), 망간(Mn), 몰리브덴(Mo), 텅스텐(W), 니오브(Nb), 탄탈럼(Ta), 타이타늄(Ti), 비스머스(Bi), 안티몬(Sb), 납(Pb) 및 이들의 합금 중 적어도 하나를 포함하는 한 층 이상의 금속층으로 구현될 수 있다. 이러한 도전성 매개층(116)은 반도체 칩(100)의 씨드(seed) 층으로서 구비되어, 도전성 패드(112)와 범프(120)를 전기적으로 연결한다.
실시예에 따라, 도전성 매개층(116)의 상부에는 범프(120)가 제공될 수 있다. 실시예에 따라, 범프(120)는 도전성 매개층(116)과 함께, 절연층(114)의 개구부(OP)에 의해 노출되는 도전성 패드(112)의 일 영역 상부 및 상기 개구부(OP) 주변의 절연층(114) 상부에 배치된다.
이러한 범프(120)는 절연층(114)의 프로파일을 따라 요철구조의 표면을 가진다. 즉, 범프(120)의 표면에는 절연층(114)의 개구부(OP)에 대응하는 오목부(124)가 형성되며, 상기 오목부(124)의 주변에는 돌기들(122)이 형성된다. 실시예에 따라, 오목부(124)의 깊이(D1)는 절연층(114)의 높이(혹은, 두께)(H1)와 유사 또는 실질적으로 동일할 수 있다. 즉, 오목부(124)의 깊이(D1)는 절연층(114)의 높이(H1)에 대응될 수 있다. 예컨대, 절연층(114)이 1㎛ 내지 2㎛의 높이(H1)를 가지면, 오목부(124)는 1㎛ 내지 2㎛의 깊이(D1)를 가질 수 있다. 절연층(114)이 1㎛보다 작은 높이(H1)를 가지면, 절연성을 충분히 확보하기 어렵거나 패시베이션막으로서 기능하기 어려울 수 있다. 한편, 절연층(114)이 2㎛보다 큰 높이(H1)를 가지면, 일례로, 4㎛보다 큰 높이(H1)를 가지게 되면 도전성 매개층(116)에 단선이 발생할 확률이 증가할 수 있다. 따라서, 절연층(114)의 높이(H1)는 절연성이 안정적으로 확보되면서도 도전성 매개층(116)에 단선결함이 방지될 수 있는 정도의 범위 내에서 설정될 수 있다. 일례로, 절연층(114)은 1㎛ 내지 4㎛의 높이(H1)를 가질 수 있다. 그리고, 범프(120)의 표면은 절연층(114)의 프로파일을 따르게 되므로, 오목부(124)는 절연층(114)의 높이(H1)에 상응하는 깊이(D1), 예컨대 1㎛ 내지 4㎛의 깊이(D1)를 가질 수 있다.
실시예에 따라, 범프(120)는 한 층 이상의 금속층으로 구현될 수 있다. 예컨대, 범프(120)는 구리(Cu), 은(Ag), 금(Au), 백금(Pt), 팔라듐(Pd), 니켈(Ni), 주석(Sn), 알루미늄(Al), 코발트(Co), 로듐(Rh), 이리듐(Ir), 철(Fe), 루테늄(Ru), 오스뮴(Os), 망간(Mn), 몰리브덴(Mo), 텅스텐(W), 니오브(Nb), 탄탈럼(Ta), 타이타늄(Ti), 비스머스(Bi), 안티몬(Sb), 납(Pb) 및 이들의 합금 중 적어도 하나를 포함하는 한 층 이상의 금속층으로 구현될 수 있다. 이러한 범프(120)는 도시되지 않은 전자장치의 접속 패드에 연결되어, 반도체 칩(100)과 전자장치를 전기적으로 연결한다.
도 4b를 참조하면, 실시예에 따라, 범프(120)는 적어도 장변방향에서 복수의 오목부들(124)을 가진다. 이를 위해, 절연층(114)은 개별 범프 영역의 장변방향을 따라 배열된 복수의 개구부들(OP)을 포함할 수 있다. 실시예에 따라, 상기 복수의 개구부들(OP)은 각각의 범프 영역 내에서 일체로 연결되거나, 혹은 서로 분리될 수 있다.
도 5a 내지 도 5f는 본 발명의 일 실시예에 의한 절연층의 평면도이다. 이러한 도 5a 내지 도 5f는 절연층에 구비되는 개구부와 관련한 다양한 실시예들을 도시한 것으로서, 본 발명이 이에 한정되지는 않는다. 즉, 절연층은 도 5a 내지 도 5f에 도시된 실시예들 중 어느 하나의 실시예에 부합되는 개구부를 가지거나, 혹은 이 외에 다양한 형태로 변형된 개구부를 가질 수 있다. 한편, 도 5a 내지 도 5f에서는 개구부의 위치를 보다 명확히 나타내기 위하여 각각의 범프가 형성되는 범프 영역을 추가적으로 도시하였으며, 상기 범프 영역은 점선으로 나타내었다.
도 5a 내지 도 5f를 참조하면, 절연층(114)은 도전성 패드(112)가 배치된 베이스 기판(110)의 일면을 덮도록 형성되되, 각각의 범프(120)가 형성될 범프 영역(120a) 내에서 도전성 패드(112)의 일 영역을 노출하는 개구부(OP1, OP2)를 가진다.
실시예에 따라, 절연층(114)은 도 5a에 도시된 바와 같이, 각각의 범프 영역(120a) 내에 서로 분리되어 배치된 복수의 제1 개구부들(OP1)을 가질 수 있다. 일례로, 절연층(114)은 범프 영역(120a)에 형성될 범프(120)의 장변방향(예컨대, y 방향)으로 배치된 일 라인(L) 상에 나란히 배치된 복수의 제1 개구부들(OP1)을 가질 수 있다. 실시예에 따라, 제1 개구부들(OP1)은 범프(120)의 장변방향의 일 라인(L) 상에 일정 간격으로 배치될 수 있다. 이러한 제1 개구부들(OP1) 각각은 범프(120)의 장변방향과 교차하는 방향, 예컨대 범프(120)의 단변방향(예컨대, x 방향)으로 연장될 수 있다.
실시예에 따라, 제1 개구부들(OP1)은 도 5b에 도시된 바와 같이, 각각의 범프 영역(120a) 내에 단변방향으로도 두 개 이상 나열될 수 있다. 즉, 제1 개구부들(OP1)의 크기, 형상 및 개수와 이들 사이의 피치 및 배치구조 등은 다양하게 변경될 수 있다.
실시예에 따라, 절연층(114)은 도 5c에 도시된 바와 같이, 각각의 범프 영역(120a) 내에서 범프(120)의 장변방향으로 연장되며 제1 개구부들(OP1)을 일체로 연결하는 적어도 하나의 제2 개구부(OP2)를 더 가질 수 있다. 즉, 실시예에 따라, 각각의 범프 영역(120a) 내에서 해당 범프 영역(120a)에 배치된 개구부들(OP1, OP2)은 일체로 연결될 수 있다.
실시예에 따라, 제1 개구부들(OP1) 및/또는 제2 개구부들(OP2)은 범프(120)의 폭 또는 길이만큼의 길이를 가질 수 있다. 예컨대, 제1 개구부들(OP1)은 범프(120)의 폭만큼의 길이를 가지도록 각각의 범프 영역(120a) 내에 가로로 배치되고, 제2 개구부들(OP2)은 범프(120)의 길이만큼의 길이를 가지도록 각각의 범프 영역(120a) 내에 세로로 배치될 수 있다.
실시예에 따라, 제1 개구부들(OP1) 및/또는 제2 개구부들(OP2)의 크기(폭 및 길이), 개수 및/또는 형상 등은 다양하게 변경될 수 있다. 예컨대, 도 5d에 도시된 바와 같이, 제1 개구부들(OP1)은 범프(120)의 폭 보다 작은 길이를 가지도록 각각의 범프 영역(120a) 내에 배치되고, 제2 개구부들(OP2)은 범프(120)의 길이보다 작은 길이를 가지도록 각각의 범프 영역(120a) 내에 배치될 수 있다.
실시예에 따라, 도 5e 및 도 5f에 도시된 바와 같이, 각각의 범프 영역(120a) 내에 복수의 제2 개구부들(OP2)이 배치될 수 있다. 또한, 제1 및 제2 개구부들(OP1, OP2)을 포함하는 개구부(OP)의 형상은 변경될 수 있다.
실시예에 따라, 절연층(114)은 도 5f에 도시된 바와 같이, 개구부(OP)에 둘러싸인 섬 형상의 절연체(114')를 더 포함할 수 있다. 이러한 절연체(114')는 각각의 범프 영역(120a) 내에 적어도 하나 이상 배치될 수 있으며, 절연체(114')의 크기, 형상 및 개수 등은 다양하게 변경될 수 있다.
전술한 바와 같이, 절연층(114)에 구비되는 개구부(OP)의 크기, 형상, 개수 및/또는 그 배치구조는 다양하게 변경 실시될 수 있다. 예컨대, 범프(120)의 표면에 형성하고자 하는 오목부(124)의 면적, 형상, 개수, 및/또는 배치구조에 부합되도록 각각의 범프 영역(120a) 내에 위치된 절연층(114)을 부분적으로 식각하여 개구부(OP)를 형성할 수 있다. 즉, 본 발명의 실시예에 의하면, 범프들(120) 각각의 적어도 장변방향을 따라 절연층(114)에 복수의 개구부(OP)를 배치함으로써, 범프들(120) 각각의 장변방향에 복수의 오목부들(124)이 형성되도록 유도할 수 있다.
도 6은 도 2에 도시된 반도체 칩의 I-I' 선에 따른 단면의 다른 예를 도시한 단면도이다. 도 6에서, 도 4a와 유사 또는 동일한 구성요소에 대해서는 동일 부호를 부여하고, 이에 대한 상세한 설명은 생략하기로 한다.
도 6을 참조하면, 실시예에 따라, 절연층(114)은 다층 구조를 가질 수 있다. 일례로, 절연층(114)은 각각 한 층 이상의 무기막(114a) 및 유기막(114b)을 포함하는 다층 구조를 가질 수 있다.
이와 같이, 절연층(114)을 다층 구조로 구성함에 따라, 절연층(114)은 무기막(114a)의 높이(H1) 및 유기막(114b)의 높이(H2)의 합에 상응하는 높이(H1+H2)를 가질 수 있다. 이와 같이, 절연층(114)의 높이(H1+H2)가 증가되면, 오목부(124)의 깊이(D2)는 보다 깊어지게 되고, 개별 돌기(122)의 높이 및/또는 그 부피는 증가하게 된다. 일례로, 절연층(114)을 다층 구조로 구성함에 의하여 상기 절연층(114)이 3㎛ 내지 4㎛의 높이(H1+H2)를 갖도록 할 수 있다. 이 경우, 범프(120)의 표면에는 대략 3㎛ 내지 4㎛의 깊이(D2)를 갖는 오목부(124)가 형성될 수 있다.
실시예에 따라, 도 4a에 도시된 바와 같이 절연층(114)이 단일층으로 구성되는 경우 오목부(124)는 대략 1㎛ 내지 2㎛의 깊이(D1)를 가질 수 있다. 그리고, 실시예에 따라, 도 6에 도시된 바와 같이 절연층(114)이 일례로, 무기막(114a) 및 유기막(114b)을 포함한 다층 구조를 가지는 경우, 오목부(124)는 대략 3㎛ 내지 4㎛의 깊이(D2)를 가질 수 있다. 즉, 실시예에 따라, 오목부(124)는 대략 1㎛ 내지 4㎛ 범위의 깊이(D1, D2)를 가질 수 있다.
한편, 절연층(114)의 높이(H1, H1+H2) 및 이에 따른 오목부(124)의 깊이(D1, D2)는 다양하게 변경될 수 있다. 다만, 이는 절연층(114)에 의한 절연성이 충분히 확보되는 조건을 만족함과 동시에, 도전성 매개층(116)의 단선 등이 방지될 수 있는 정도의 조건을 만족할 수 있는 범위 내에서 결정될 수 있다. 일례로, 절연층(114)의 높이(H1, H1+H2) 및 오목부(124)의 깊이(D1, D2)는 각각 대략 1㎛ 내지 4㎛의 범위 내에서 결정될 수 있다.
도 6에 도시된 실시예에서와 같이, 오목부(124)의 깊이(D2)가 깊어지게 되면, 상기 오목부(124)가 형성된 범프(120)의 표면을 전자장치의 접속 패드와 접합할 때, 돌기들(122)에 집중되는 압력과 더불어 전단강도(shear strength)가 증가된다. 또한, 개별 돌기들(122)의 부피가 증가하므로 접합량 자체가 증가하게 된다. 이에 따라, 보다 용이하게 접합공정을 진행할 수 있으며, 접합의 질을 향상시킬 수 있다.
도 7은 본 발명의 일 실시예에 의한 전자장치의 사시도이다. 그리고, 도 8은 도 7의 Ⅲ-Ⅲ' 선에 따른 단면의 일례를 개략적으로 도시한 단면도이다. 실시예에 따라, 도 7 및 도 8에서는 전자장치의 일례로서 표시장치를 도시하기로 하나, 본 발명에 의한 전자장치가 반드시 표시장치에만 국한되지는 않는다. 도 7 및 도 8에서, 도 1 내지 도 6에 도시된 실시예와 유사 또는 동일한 구성 요소(예컨대, 반도체 칩)에 대해서는 동일 부호를 부여하고, 이에 대한 상세한 설명은 생략하기로 한다.
도 7 및 도 8을 참조하면, 본 발명의 실시예에 의한 전자장치는 일례로 표시장치일 수 있다. 이러한 전자장치는 표시패널(200)과 이에 실장된 반도체 칩(100)을 포함한다.
실시예에 따라, 표시패널(200)은 적어도 활성영역(Active Area; AA)에서 서로 중첩되는 제1 기판(210) 및 제2 기판(220)과, 제1 기판(210)의 비활성영역(Non-active Area; NA)에 배치된 다수의 접속 패드들(212)을 포함한다. 활성영역(AA)은 적어도 화소들(미도시)이 배치되는 영역으로서, 영상이 표시되는 영역을 의미할 수 있다. 비활성영역(NA)은 활성영역(AA)을 제외한 나머지 영역을 의미하는 것으로서, 일례로 배선영역, 패드영역 및/또는 각종 더미영역 등을 포함할 수 있다. 실시예에 따라, 표시패널(200)은 유기전계발광 표시패널, 액정 표시패널, 및 플라즈마 표시패널 중 하나일 수 있으나, 표시패널(200)의 종류가 이에 한정되지는 않는다.
실시예에 따라, 제1 기판(210) 및 제2 기판(220) 중 적어도 하나는 유리 기판 혹은 플라스틱 기판일 수 있다. 예컨대, 제1 기판(210) 및/또는 제2 기판(220)은, 폴리에테르술폰(PES, polyethersulfone), 폴리아크릴레이트(polyacrylate), 폴리에테르이미드(PEI, polyetherimide), 폴리에틸렌 나프탈레이트(PEN, polyethylene naphthalate), 폴리에틸렌 테레프탈레이드(PET, polyethylene terephthalate), 폴리페닐렌 설파이드(PPS, polyphenylene sulfide), 폴리아릴레이트(PAR, polyarylate), 폴리이미드(PI, polyimide), 폴리카보네이트(PC, Polycarbonate), 셀룰로오스 트리 아세테이트(TAC) 및 셀룰로오스아세테이트 프로피오네이트(CAP, cellulose acetate propionate) 중 적어도 하나의 물질을 포함한 가요성 기판(flexible substrate)일 수 있다. 또한, 제1 기판(210) 및/또는 제2 기판(220)은 유리(glass) 및 강화 유리 중 하나의 물질을 포함하는 경성 기판(rigid substrate)일 수도 있다. 한편, 제1 기판(210) 및/또는 제2 기판(220)은 투명한 재질의 기판일 수 있으나, 이에 한정되지는 않는다.
또한, 실시예에 따라, 제1 기판(210) 및 제2 기판(220) 중 적어도 하나는, 적어도 한 층의 무기막 및/또는 유기막을 포함하는 절연층으로 구현될 수도 있다. 예컨대, 제2 기판(220)은 적어도 한 층의 무기막 및/또는 유기막을 포함하는 박막 봉지층(Thin Film Encapsulation; TFE)일 수 있다.
실시예에 따라, 접속 패드들(212)은 도전성 물질로 구성되어, 도시되지 않은 각종 신호선들 및/또는 전원선들에 접속될 수 있다. 실시예에 따라, 접속 패드들(212)은 적어도 제1 금속, 예컨대 알루미늄(Al)을 포함할 수 있다. 이러한 접속 패드들(212)은 표시패널(200)과 반도체 칩(100)의 사이에서 표시패널(200)을 구동하기 위한 각종 전원들 및/또는 신호들을 전달할 수 있다.
실시예에 따라, 반도체 칩(100)은, 제1 기판(210) 상의 비활성 영역(NA)에 실장될 수 있다. 이러한 반도체 칩(100)은, 표시패널(200)을 구동하기 위한 구동회로를 포함할 수 있다. 일례로, 반도체 칩(100)의 내부에는 도시되지 않은 주사 구동회로 및/또는 데이터 구동회로가 집적될 수 있다.
실시예에 따라, 반도체 칩(100)은, 베이스 기판(110)과 다수의 범프들(120)을 구비할 수 있다. 실시예에 따라, 범프들(120)은 접속 패드들(212) 각각과 마주하도록 상기 베이스 기판(110)의 일면에 배치되어 상기 접속 패드들(212)에 전기적으로 연결될 수 있다. 실시예에 따라, 범프들(120)은 적어도 제2 금속을 포함할 수 있다. 제2 금속은 제1 금속과 동일 또는 상이한 금속일 수 있다. 예컨대, 제2 금속은 금(Au)일 수 있다.
실시예에 따라, 도 7의 반도체 칩(100)은, 앞서 도 1 내지 도 6에서 설명한 실시예에 의한 반도체 칩(100)일 수 있다. 예컨대, 반도체 칩(100)은, 도 1 내지 도 6에 도시된 바와 같이, 접속 패드들(212)을 향하는 베이스 기판(110)의 일면 상에 범프들(120) 각각과 대응하도록 배치되며 해당 범프(120)에 전기적으로 연결되는 다수의 도전성 패드들(112)과, 상기 도전성 패드들(112)이 제공된 베이스 기판(110)의 일면을 덮되 범프들(120) 및 도전성 패드들(112)의 사이에서 범프들(120)의 장변방향으로 연장된 일 라인(L) 상에 배치된 복수의 제1 개구부들(OP1)을 가지는 절연층(114)을 더 포함할 수 있다. 실시예에 따라, 제1 개구부들(OP1) 각각은 범프(120)의 장변방향과 교차하는 방향으로 연장될 수 있다.
실시예에 따라, 접속 패드들(212)과 범프들(120)의 사이에는 도전성 접합층(300)이 구비된다. 도전성 접합층(300)은 접속 패드들(212)에 포함된 제1 금속과 범프들(120)에 포함된 제2 금속이 혼합되어 구성되며, 반도체칩(100)을 표시패널(200)에 연결할 때 범프들(120)과 접속 패드들(212)을 마찰시켜 이들의 표면을 용융시킨 후 굳혀서 얻어진 고상 접합층일 수 있다. 일례로, 도전성 접합층(300)의 내부에는 알루미늄(Al)과 금(Au)이 혼합되어 존재할 수 있다.
실시예에 따라, 접속 패드들(212) 및/또는 범프들(120)은 일례로 5㎛ 내지 20㎛의 미세한 폭 및/또는 피치를 가질 수 있다. 특히, 본 발명의 실시예에 의하면 ACF 등을 이용하지 않고 접속 패드들(212)과 범프들(120)을 직접 접합하므로 접속 패드들(212) 및/또는 범프들(120)이 미세한 폭 및/또는 피치를 가지더라도 이들 사이에 안정적인 접속 구조를 제공할 수 있다.
실시예에 따라, 표시패널(200)과 반도체 칩(100)의 사이에는 도시되지 않은 비도전성 접착층이 추가적으로 구비될 수 있다. 이러한 비도전성 접착층은 표시패널(200)과 반도체 칩(100)의 사이에 개재되어 표시패널(200) 상에 반도체 칩(100)을 안정적으로 접착할 수 있다.
도 9는 본 발명의 일 실시예에 의한 반도체 칩의 연결방법을 설명하기 위한 단면도이다. 그리고, 도 10은 도 9의 일 영역을 확대하여 도시한 단면도이다. 도 9 및 도 10에 개시된 반도체 칩 및 표시패널은 앞서 도 1 내지 도 8에서 설명한 실시예에 의한 반도체 칩 및 표시패널일 수 있다. 따라서, 도 9 및 도 10에서 도 1 내지 도 8과 유사 또는 동일한 구성요소에는 동일 부호를 부여하고, 이에 대한 상세한 설명은 생략하기로 한다.
도 9 내지 도 10을 참조하면, 우선 다수의 범프들(120)이 제공된 반도체 칩(100)을 마련함과 아울러, 상기 범프들(120)에 대응하는 다수의 접속 패드들(212)이 제공된 제1 기판(210)을 포함한 표시패널(200)을 마련한다.
실시예에 따라, 반도체 칩(100)은 도 1 내지 도 8에서 설명한 실시예에 의한 반도체 칩일 수 있다. 예컨대, 반도체 칩(100)은 표면에 복수의 돌기들(122) 및 오목부들(124)을 구비한 범프들(120)을 포함할 수 있다. 실시예에 따라, 범프들(120)은 적어도 장변방향에서 복수의 돌기들(122) 및 오목부들(124)을 구비할 수 있다.
실시예에 따라, 접속 패드들(212)은 제1 기판(210) 상에 배치된 제1 도전층(212a)과, 상기 제1 도전층(212a) 상에 배치된 제2 도전층(212b)을 포함할 수 있다. 한편, 제1 도전층(212a)이 제공된 제1 기판(210)의 일면은 절연성을 가지는 보호층(214)으로 덮이되, 보호층(214)은 제1 도전층(212a)의 일 영역을 노출하는 개구부를 가진다. 제2 도전층(212b)은 보호층(214)에 형성된 개구부에 의해 제1 도전층(212a)과 접촉될 수 있다.
실시예에 따라, 제1 도전층(212a)은 금속, 이들의 합금, 도전성 고분자, 도전성 금속 산화물 중 적어도 하나를 포함할 수 있다. 일례로, 제1 도전층(212a)은 도 4a에 대한 설명에서 나열한 바와 같은 도전성 패드(112)를 구성할 수 있는 도전성 물질 중 적어도 하나를 포함할 수 있다.
실시예에 따라, 제2 도전층(212b)은, 한 층 이상의 금속층으로 구현될 수 있다. 일례로, 제2 도전층(212b)은 도 4a에 대한 설명에서 나열한 바와 같은 범프(120)를 구성할 수 있는 금속 및 이들의 합금 중 적어도 하나를 포함할 수 있다. 이러한 제2 도전층(212b)은 범프(120)와 동일한 금속 물질을 포함할 수 있으나, 이에 한정되지는 않는다. 일례로, 범프(120)는 금(Au)을 포함하는 단일층으로 구성되고, 제2 도전층(212b)은 타이타늄(Ti)/알루미늄(Al)/타이타늄(Ti) 층으로 구성될 수 있다.
특히, 본 발명의 실시예에서는 범프들(120)의 표면에 복수의 돌기들(122) 및 오목부들(124)을 형성함에 의해, 동종 금속을 접합할 때에 비해 큰 에너지가 필요한 이종 금속의 접합 공정이라 하더라도 상기 접합 공정을 비교적 용이하게 수행할 수 있다. 따라서, 제2 도전층(212b)은 범프들(120)과 동일한 금속은 물론 상이한 금속으로도 구성될 수 있다.
이후, 범프들(120)과 접속 패드들(212)이 서로 마주하도록 반도체 칩(100)을 제1 기판(210) 상에 정렬하여 배치한다. 실시예에 따라, 표시패널(200)은 접합장치의 스테이지(410) 상에 안착되고, 반도체 칩(100)은 접합장치의 헤드부(420)에 진공 흡착되어 제1 기판(210) 상에 정렬될 수 있다.
이후, 헤드부(420)를 통해 반도체 칩(100)에 소정의 진동 및 압력을 가하면서, 접속 패드들(212)과 범프들(120)을 마찰시킨다. 일례로, 반도체 칩(100)에 초음파(U/S) 범위의 진동을 가하여 접속 패드들(212)과 범프들(120)을 빠른 속도로 마찰시킬 수 있다. 이때 발생하는 마찰 에너지에 의해 접속 패드들(212) 및 범프들(120)의 표면이 용융되게 된다. 예컨대, 마찰 에너지에 의해 범프들(120)의 표면에 제공된 돌기들(122)이 용융됨과 아울러, 접속 패드들(212)의 표면, 예컨대 제2 도전층(212b)의 적어도 일부가 용융될 수 있다. 이에 따라, 접속 패드들(212)과 범프들(120)의 사이에서 접속 패드들(212)에 포함된 제1 금속과 범프들(120)에 포함된 제2 금속이 서로 혼합되고, 진동 및 압력이 제거된 이후 굳어지면서 도 8에 도시된 바와 같은 도전성 접합층(300)을 형성하게 된다. 즉, 도전성 접합층(300)은 제1 금속 및 제2 금속이 혼합되어 구성될 수 있다.
이와 같이 본 발명의 실시예에서는 초음파(U/S)를 이용하여 접속 패드들(212)과 범프들(120)을 직접 접합함에 의해, 반도체 칩(100)을 제1 기판(210) 상에 실장한다. 이에 따라, ACF 등을 이용하지 않고도 반도체 칩(100)을 제1 기판(210)의 접속 패드들(212)에 안정적으로 연결할 수 있다.
특히, 본 발명의 실시예에서는 범프들(120)의 표면에 복수의 돌기들(122) 및 오목부들(124)을 형성함에 의해 접합공정의 초기 단계에서 돌기들(122)에 집중적으로 압력이 가해지도록 한다. 따라서, 저압 조건에서도 범프들(120)을 접속 패드들(212)에 용이하게 접합할 수 있다.
전술한 바와 같은 본 발명의 실시예에 의하면, 범프들(120) 각각의 표면에 복수의 돌기들(122) 및 오목부들(124)을 형성함으로써, 접합 공정의 초기에는 돌기들(122)에 압력이 집중되도록 하여 마찰 에너지를 상승시킬 수 있다. 이에 따라, 고압 공정을 적용하지 않고도 돌기들(122)을 비교적 용이하게 용융시켜, 범프들(120)과 이에 대응하는 접속 패드들(212)의 사이에 확산층(diffusion layer)의 형성을 용이하게 유도할 수 있다.
즉, 본 발명의 실시예에 의하면, 범프들(120) 각각에 복수의 오목부들(124)이 형성되지 않은 비교 예 대비, 반도체 칩(100)에 동일한 하중을 가하더라도 돌기들(122)을 비교적 용이하게 용융시킬 수 있다. 따라서, 전자장치의 배선들이나 접속 패드들(212)의 손상이 방지될 수 있는 정도의 저압 공정으로도 돌기들(122)을 비교적 용이하게 용융시킬 수 있다. 이러한 본 발명의 실시예에 의하면, 일례로 제1 및 제2 기판(210, 220)이 유연한 플라스틱 기판으로 구성되는 플렉서블 표시패널(200) 상에서도 저압 공정을 적용하여 반도체 칩(100)을 상기 표시패널(200)에 안정적으로 연결할 수 있다.
또한, 돌기들(122)이 용융되면서 접속 패드들(212)의 표면과 결합하여 확산층(diffusion layer)을 형성하기 시작하면, 범프들(120)과 이에 대응하는 접속 패드들(212)의 사이에 면 접촉의 형태로 도전성 접합층(300)이 형성되게 된다. 이때, 본 발명의 실시예와 같이 범프들(120) 각각의 표면에 다수의 돌기들(122) 및 오목부들(124)이 존재하게 되면, 범프들(120)과 접속 패드들(212) 사이의 마찰계면이 증가하게 된다. 이에 따라, 범프들(120) 각각에 복수의 오목부들(124)이 형성되지 않은 비교 예 대비, 동일한 압력 혹은 그 이하의 저압 조건에서도 보다 양질의 접합층(300)이 형성되도록 할 수 있다. 이러한 본 발명의 실시예에 의하면, 각각의 범프들(120)이 일례로 5㎛ 내지 20㎛ 이하의 미세한 폭 및/또는 피치를 가지더라도 범프들(120)과 접속 패드들(212) 사이에 안정적인 접속 구조를 제공할 수 있다. 또한, 직접 접합 구조를 통해 범프들(120)과 접속 패드들(212) 사이에서 저저항 특성을 확보할 수 있다.
본 발명의 기술 사상은 전술한 실시예에 따라 구체적으로 기술되었으나, 상기 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 지식을 가진 자라면 본 발명의 기술 사상의 범위 내에서 다양한 변형 예가 가능함을 이해할 수 있을 것이다.
본 발명의 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라, 특허 청구범위에 의해 정해져야만 할 것이다. 또한, 특허 청구범위의 의미 및 범위, 그리고 그 균등 개념으로부터 도출되는 모든 변경 또는 변형된 형태가 본 발명의 범위에 포함되는 것으로 해석되어야 할 것이다.
100: 반도체 칩 110: 베이스 기판
112: 도전성 패드 114: 절연층
116: 도전성 매개층 120: 범프
122: 돌기 124: 오목부
200: 표시패널 210: 제1 기판
212: 접속 패드 220: 제2 기판
300: 도전성 접합층

Claims (15)

  1. 베이스 기판과,
    상기 베이스 기판의 일면 상에 배치된 적어도 하나의 도전성 패드와,
    상기 도전성 패드가 배치된 상기 베이스 기판의 일면 상에 배치되며, 상기 도전성 패드의 일 영역을 노출하는 개구부를 가지는 절연층과,
    상기 개구부에 의해 노출되는 상기 도전성 패드의 일 영역 상부 및 상기 개구부 주변의 절연층 상부에 배치되며, 상기 개구부에 대응하는 오목부를 가지는 적어도 하나의 범프를 포함하며,
    상기 범프는 장변방향을 따라 나열된 복수의 오목부들을 가지는 반도체 칩.
  2. 제1항에 있어서,
    상기 절연층은, 상기 범프의 장변방향의 일 라인 상에 나란히 배치된 복수의 제1 개구부들을 가지는 반도체 칩.
  3. 제2항에 있어서,
    상기 제1 개구부들 각각은 상기 범프의 장변방향과 교차하는 방향으로 연장된 반도체 칩.
  4. 제2항에 있어서,
    상기 절연층은, 상기 범프에 대응하는 각각의 범프 영역 내에서 상기 장변방향으로 연장되며 상기 제1 개구부들을 일체로 연결하는 적어도 하나의 제2 개구부를 더 가지는 반도체 칩.
  5. 제1항에 있어서,
    상기 범프는 한 층 이상의 금속층을 포함하는 반도체 칩.
  6. 제1항에 있어서,
    상기 도전성 패드와 상기 범프 사이에 구비되는 도전성 매개층을 더 포함하는 반도체 칩.
  7. 제1항에 있어서,
    상기 범프는 5㎛ 내지 20㎛의 폭을 가지고, 상기 오목부들 각각은 1㎛ 내지 4㎛의 깊이를 가지는 반도체 칩.
  8. 제1항에 있어서,
    상기 절연층은, 각각 한 층 이상의 무기막 및 유기막을 포함하는 다층 구조를 가지는 반도체 칩.
  9. 제1항에 있어서,
    상기 오목부들 각각은 상기 절연층의 높이에 대응하는 깊이를 가지는 반도체 칩.
  10. 적어도 제1 금속을 포함하는 다수의 접속 패드들이 제공된 기판과,
    상기 접속 패드들 각각과 마주하도록 배치되어 상기 접속 패드들에 전기적으로 연결되며, 적어도 제2 금속을 포함하는 다수의 범프들이 제공된 반도체 칩과,
    상기 접속 패드들과 상기 범프들의 사이에 제공되며 상기 제1 금속과 상기 제2 금속이 혼합된 도전성 접합층을 포함하는 전자장치.
  11. 제10항에 있어서,
    상기 반도체 칩은,
    베이스 기판과,
    상기 접속 패드들을 향하는 상기 베이스 기판의 일면 상에 상기 범프들 각각에 대응하도록 배치되며, 해당 범프에 전기적으로 연결되는 다수의 도전성 패드들과,
    상기 도전성 패드들이 제공된 상기 베이스 기판의 일면 상에 배치되며, 상기 범프들과 상기 도전성 패드들의 사이에서 상기 범프들 각각의 장변방향의 일 라인 상에 배치된 복수의 제1 개구부들을 가지는 절연층을 더 포함하는 전자장치.
  12. 제11항에 있어서,
    상기 제1 개구부들 각각은 상기 범프의 장변방향과 교차하는 방향으로 연장된 전자장치.
  13. 제10항에 있어서,
    상기 기판을 포함한 표시패널을 구비하는 전자장치.
  14. 적어도 장변방향에서 복수의 돌기들 및 오목부들을 가지는 다수의 범프들을 구비하는 반도체 칩을 마련하는 단계와,
    상기 범프들에 대응하는 다수의 접속 패드들을 구비하는 기판을 마련하는 단계와,
    상기 범프들과 상기 접속 패드들이 서로 마주하도록 상기 반도체 칩을 상기 기판 상에 배치하는 단계와,
    상기 반도체 칩에 소정의 진동 및 압력을 가하면서, 상기 범프들 및 상기 접속 패드들을 접합하는 단계를 포함하는 반도체 칩의 연결방법.
  15. 제14항에 있어서,
    상기 범프들 및 상기 접속 패드들을 접합하는 단계는,
    상기 반도체 칩에 초음파 범위의 진동을 가하면서 상기 범프들과 상기 접속 패드들을 마찰시켜 상기 돌기들 및 상기 접속 패드들의 일부를 용융시키는 단계와,
    상기 범프들 및 상기 접속 패드들의 사이에, 상기 범프들에 포함된 금속과 상기 접속 패드들에 포함된 금속이 혼합된 도전성 접합층을 형성하는 단계를 포함하는 반도체 칩의 연결방법.
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