TWI239086B - Circuit board structure integrated with semiconductor chip and method for fabricating the same - Google Patents
Circuit board structure integrated with semiconductor chip and method for fabricating the same Download PDFInfo
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- TWI239086B TWI239086B TW093119372A TW93119372A TWI239086B TW I239086 B TWI239086 B TW I239086B TW 093119372 A TW093119372 A TW 093119372A TW 93119372 A TW93119372 A TW 93119372A TW I239086 B TWI239086 B TW I239086B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
Abstract
Description
1239086 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種整合半導體晶片之電路板結構及 其製法，尤指一種可在電路板中整合有半導體晶片之結構 及其製作方式。 【先前技術】1239086 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a circuit board structure integrated with a semiconductor wafer and a manufacturing method thereof, particularly a structure capable of integrating a semiconductor wafer into a circuit board and a manufacturing method thereof. . [Prior art]
隨著半導體封裝技術的演進，半導體裝置 (Semiconductor device)已開發出不同的封裂型態，其巾 球柵陣列式（Ball grid array，BGA)為一種先進的半導體 封裝技術，其特點在於採用一基板來安置半導體晶片，並 利用自動對位（S e 1 f - a 1 i g n m e n t )技術以於該基板背面植置 複數個成柵狀陣列排列之錫球（S ο 1 d e r b a 1 1 )，使相同單 位面積之半導體晶片承載件上可以容納更多輸入/輸出連 接端（I/O connection)以符合高度集積化（Integration) 之半導體晶片所需，以藉由此些錫球將整個封裝單元銲結 並電性連接至外部之印刷電路板。With the evolution of semiconductor packaging technology, semiconductor devices have developed different types of sealing. The Ball Grid Array (BGA) is an advanced semiconductor packaging technology, which is characterized by the use of a The substrate is used to place a semiconductor wafer, and a plurality of solder balls (S ο 1 derba 1 1) arranged in a grid array are arranged on the back of the substrate by using automatic alignment (S e 1 f-a 1 ignment) technology to make the same The semiconductor chip carrier per unit area can accommodate more I / O connections to meet the needs of highly integrated semiconductor wafers, so that the entire packaging unit can be soldered by these solder balls. And is electrically connected to an external printed circuit board.
另自IBM公司在I 9 6 0年早期引入覆晶封裝（FI ip chip p a c k a g e )技術以來，相較於打線（w i r e b ο n d )技術，覆晶 技術之特徵在於半導體晶片與基板間的電性連接係透過銲 錫凸塊而非一般之金線。而該種覆晶技術之優點在於該技 術可提高封裝密度以降低封裝元件尺寸，同時，該種覆晶 技術不需使用長度較長之金屬導線，故可提高電性性能， 以滿足南密度、高速度之半導體裝置需求。 在現行覆晶技術中，半導體積體電路丨c)晶片的表面 上配置有電極輝墊（Electrode pads)，而供承載晶片之電In addition, since IBM introduced the FI ip chip package technology in early 960, compared to wireb technology, the flip-chip technology is characterized by the electrical connection between the semiconductor wafer and the substrate. It is through solder bumps instead of ordinary gold wires. The advantage of this flip-chip technology is that it can increase the packaging density to reduce the size of package components. At the same time, this flip-chip technology does not require the use of longer metal wires, so it can improve electrical performance to meet the South Density, Demand for high-speed semiconductor devices. In the current flip-chip technology, the semiconductor integrated circuit 丨 c) is provided with electrode pads on the surface of the wafer, and is used to carry the electricity of the wafer.
1239086 ^ 五、發明說明（2) 路板上亦具有 間可以適當地讲署二的接觸銲墊，在該晶片以及電路板之 片係以電性接^ ^錫凸塊或其他導電黏著材料，使該晶 該銲錫凸塊或、首泰月下的方式設置於該電路板上，其中， 性輸入/輪出黏著材料提供該晶片以及電路板間的電 抹/出（1/0)以及機械性的連接。 圖所示H ί 1BS1，係說明一種習知的覆晶元件，如 ，以及數個由^料=Ϊ U係形成於晶片13之電極銲塾12上 1 6之接觸銲墊[5上：成的預銲錫凸塊1 4係形成於電路板 溫度條件下二;=使該預銲錫凸塊14炼融之迴銲 塊11即可ί 塊14迴鲜至相對應之金屬凸 ioint)而」 。就銲錫凸塊銲錫接（Solder bump 填入有機^膠I進一步在該晶片以及該電路板間的間隙中 異有機底骖1 8，以抑制該晶片1 3以及該電路板彳 膨脹差並降低該銲錫接的應力。 -路板16間的熱 而目前業界主要係藉由模板印刷技術（SteneU pnntmg techno l〇gy)在電路板之接觸銲墊上沈積 料以形成預銲錫凸塊。然而，在實際操作.上，由於現入雨 T且網路及電腦等各式可攜式（p〇rtable)電子產品的二二 成長，可縮小1C面積且具有高密度與多接腳化特性 、晶片尺寸封裝（CSP， Chip size package)與多晶片模组 (MCM， Multi chip module)等封裝件已日漸成為封裝市場 上的主流，並常與微處理器、晶片組、繪圖晶片等古效此 晶片搭配，以發揮更高速之運算功能，惟該些結構:: 小線路寬度與銲墊尺寸，當銲墊間隙持續縮減時，因為該1239086 ^ V. Description of the invention (2) There are also contact pads on the circuit board that can be properly described. The chip and the circuit board are electrically connected with tin bumps or other conductive adhesive materials. The solder bumps or the wafers are arranged on the circuit board in a manner such that the input / output adhesive material provides electrical wiping / out (1/0) and mechanical between the chip and the circuit board. Sexual connection. Shown in the figure is H 1BS1, which is a description of a conventional flip-chip device, such as, and several contact pads 16 formed on the electrode pad 12 of the wafer 13 by ^ material = Ϊ U system [5: Cheng The pre-soldering bumps 14 and 4 are formed under the temperature conditions of the circuit board; = the re-soldering bumps 11 of the pre-soldering bumps 14 can be melted back to the corresponding metal bumps ioint). " Regarding solder bump soldering (Solder bump is filled with organic glue I to further differentiate the organic substrate 18 in the gap between the wafer and the circuit board, to suppress the differential expansion of the wafer 13 and the circuit board and reduce the Stress of solder joints.-The heat between the boards 16 and the current industry mainly uses stencil printing technology (SteneU pnntmg techno l0gy) to deposit material on the contact pads of circuit boards to form pre-solder bumps. However, in actual practice In terms of operation, due to the current growth of various portable electronic products such as the Internet and computers, the area can be reduced by 1C, with high density and multi-pin characteristics, and chip size packaging. (CSP, Chip size package) and multi-chip module (MCM, Multi chip module) and other packages have gradually become the mainstream in the packaging market, and are often used with microprocessors, chip sets, graphics chips and other ancient chips. In order to take advantage of higher-speed computing functions, these structures: Small circuit width and pad size, when the pad gap continues to shrink, because
1239086 五、發明說明 銲墊間形 使外露出 續形成預 護層敷設 術中之模 接觸銲墊 況且模板 製程費之 對於該電 護層對於 另外 晶圓積體 一銲塊底 以供承載 複數個晶 至一電路 於該半導 layer)， 用錢錄及 將一拒鲜 數個開口 佈製程， 該拒鲜層 層，再進 (3) 成有絕 該絕緣 辉锡凸 所佔之 板開孔 上，導 之費用 增加； 路板本 該電路 ，於覆 電路製 部金屬 金屬凸 片，之 板上。 體晶圓 並曝露 電鍍形 層設置 ，用以 用以將 開口以 行回銲 緣保護層，將遮蔽住部分之銲塾面積，致 保護層之銲墊尺寸更形縮小，不僅造成後 塊之對位問題的產生，同時亦因該絕緣保 空間與其形成之高度影響，使模板印刷技 尺寸要求縮小’録錫材料亦不易沈積在該 致模板印刷技術變得良率過低而不可行， 係因銲墊尺寸、間距之縮小而增加，致使 此外’隨者鮮塾間隙的縮減，絕緣保護層 身的接觸面積則變得更小，而使該絕緣^ 板本身的黏著力有減弱的趨勢。 曰^式半導體裝置之製程中，同樣須在完成 程後，於邊晶圓内晶片之電極銲墊上形成 化（Under bump metallurgy，UBM)結構層 塊’再進行切單作業以將該晶圓切割形^ 後將該覆晶式半導體晶片接置並電性連接 其中該UBM結構層與金屬凸塊之製程首先 表面形成一絕緣保護層（Passi\ati〇n 出電極銲墊位置，接著於該電極銲墊上利 成一包含有多層金屬之UBM結構層；之後 於該絕緣保護層上，且該拒銲層預設有 曝露出該UBM結構層；然後進行一銲料塗 例如為錫鉛合金（Sn/Pb)之銲料，透過 利用、、’罔版印刷之技術而塗佈至該ubm結構 (Ref 1 ow)製程以將銲料銲結至該ubm=構1239086 V. Description of the invention The shape of the pads is exposed so that the molds in contact with the pads are continuously formed during the pre-coating process and the template process costs are incurred for the electrical protective layer and for a wafer block in the wafer stack for carrying multiple crystals. To a circuit in the semiconducting layer), use money to record and fabricate a number of openings, and then enter the (3) layer into the opening of the board occupied by the insulating tin bump. The cost of the guide is increased; the circuit board originally had the circuit on the metal-metal tab of the circuit-covering part. The body wafer is exposed with an electroplated layer, which is used to protect the opening with a back-weld edge protection layer, which will shield the welding area of the part, resulting in a smaller size of the pad of the protection layer, which not only causes the opposite block. The problem of the position problem is caused by the high impact of the insulation space and its formation, which reduces the size of the stencil printing technology. The tin recording material is also not easy to deposit. The stencil printing technology becomes too low to be feasible. The increase in the size and spacing of the bonding pads results in the shrinkage of the gap between the followers, and the contact area of the insulating protective layer becomes smaller, which tends to weaken the adhesion of the insulating sheet itself. In the manufacturing process of the semiconductor device, after the process is completed, an under bump metallurgy (UBM) structural layer block must be formed on the electrode pads of the wafer in the side wafer, and then a singulation operation is performed to cut the wafer. After forming the flip-chip semiconductor wafer and electrically connecting the UBM structure layer and the metal bumps, an insulating protective layer is first formed on the surface (Passi \ ati〇n is at the electrode pad position, and then at the electrode). A UBM structure layer containing multiple layers of metal is formed on the solder pad; then, the UBM structure layer is exposed on the insulation protection layer, and the UBM structure layer is preset to be exposed; and then a solder coating such as tin-lead alloy (Sn / Pb) is performed. ), The solder is applied to the ubm structure (Ref 1 ow) process by using the technology of stencil printing to bond the solder to the ubm = structure.
17813全戀.ptd 第8頁 !239086 五、發明說明（4) 〜 〜 言^ ’之後將該拒銲層移除，並進行第二次回銲 Λ金亍料圓球化，以在半導p日 王序以將 今入说 乂牡干♦肢日日0上形成金屬凸塊，，、；# 〜屬凸塊提供半導體晶片肖電路板間之電性 精由 與因此，對於覆晶式半導體裝置而言，需在半 二j應接置之電路板上各自形成有對應之電性連i二阳片 同^屬凸塊及預銲錫凸塊），不僅提高製程步驟與==( 日t伴隨製程中信賴性風險之增加。 /、 ’ 另無論是採用覆晶式封裝製程亦或打線式封事制 μ電路板之製程與半導體晶片之封裝形式，均需“二二: =製程機具與製程步驟，且其製程繁瑣，製造成本高；: ’於進行模壓封膠製程時，係將完成佈設晶片之電路才 ^於一封裝模具中，俾供一環氧樹脂（Ε ρ ο X y )材料注入模反 2中而形成用以包覆該晶片與銲線之封裝膠體，然而，I 貫際製程中，該模具由於受限於半導體封裝件之設計，故 f模穴尺寸與失壓位置勢必有所差異而造成無法緊密失固 =問通俟’主入樹脂材料時，谷易導致封裝膠體溢膠至节 :路板表面，非但降低該半導體封裝件之表面平整度與美 觀，同時更可能污染該電路板上後續欲植置錫球之銲 = 置，而影響該半導體封裝件之電性連接品質，嚴重影變 半導體封裝件之生產品質及產品信賴度。 s μ 此外，一般半導體裝置之製程，係首先由晶片承载件 ‘造業者（例如電路板製造商）生產適用於半導體裝置之曰 片承載件，之後，再將該些晶片承載件交由半導體封= 者進行置晶、模壓、以及植球等製程，最後，方可& 二 各17813 全 恋 .ptd Page 8! 239086 V. Description of the Invention (4) ~ ~ Word ^ 'After that, the solder resist layer is removed, and the second re-welding of the Λgold material is performed to spheroidize the pb in the semiconducting p Sun King Xu Yijin said that the metal bumps are formed on the limbs, and that the metal bumps are formed on the day 0. # ~ The bumps provide the electrical precision between the semiconductor chip and the circuit board. Therefore, for flip-chip semiconductors As for the device, the corresponding electrical connecting plate and the pre-soldering bumps need to be formed on the circuit boards to be connected respectively, which not only improves the process steps and == (day t With the increase of the reliability risk in the manufacturing process. /, 'In addition, whether it is a flip-chip packaging process or a wire-type sealing μ circuit board manufacturing process and the semiconductor chip packaging form, "two two: = process equipment and The manufacturing steps are complicated and the manufacturing cost is high; 'When the molding and sealing process is performed, the circuit for laying out the chips is completed in a packaging mold and an epoxy resin (E ρ ο X y) is supplied. The material is injected into the mold 2 to form an encapsulating gel for covering the wafer and the bonding wires. However, In the I process, the mold is limited by the design of the semiconductor package, so the size of the f cavity and the position of the pressure loss will inevitably be different, which will cause close failure. It is easy to cause the packaging colloid to overflow to the joint: the surface of the circuit board, not only reduce the surface flatness and beauty of the semiconductor package, but also contaminate the soldering of the solder balls on the circuit board, which will affect the semiconductor package. The quality of the electrical connection of the components seriously affects the production quality and product reliability of the semiconductor package. In addition, the general semiconductor device manufacturing process is first produced by the wafer carrier 'maker (such as a circuit board manufacturer) and is suitable for Chip carriers for semiconductor devices. After that, the wafer carriers are handed over to the semiconductor package for wafer placement, molding, and ball implantation. Finally, the &
17813全懋.ptd 第9頁 1239086 五、發明說明（5) 戶端所需之電子功能之半導體裝置。其間涉及不同製程業 者（即包含有晶片承載件製造業者與半導體封裝業者），因 此於實際製造過程中不僅步驟繁瑣且界面整合不易，況且 ，若客戶端欲進行變更功能設計時，其牽涉變更與整合層 面更是複雜，亦不符合需求變更彈性與經濟效益。 【發明内容】 鑒於以上所述習知技術之缺點，本發明之主'要目的係 提供一種整合半導體晶片之電路板結構及其製法，俾同時 整合晶片承載件之製造與半導體封裝技術之製程，以提供 客戶端較大需求彈性，同時得以簡化半導體業者製程與界 面整合問題。 本發明之再一目的係提供一種整合半導體晶片之電路 板結構及其製法，避免習知半導體晶片與電路板電性導接 所導致之各項問題。 本發明之又一目的係提供一種整合半導體晶片之電路 板結構及其製法，藉以簡化該電路板與半導體晶片之整合 形式，以降低製程步驟與成本。 本發明之另一目的係提供一種整合半導體晶片之電路 板結構及其製法，藉以避免習知半導體封裝作業中所產生 之溢膠問題，俾有效提昇半導體裝置之生產品質及產品信 賴度。 為達上揭及其它目的，本發明之整合半導體晶片之電 路板製法，主要係提供一支承板，該支承板可為一般之承 載板或電路板，且該支承板形成有至少一貫穿表面之開孔17813 全懋 .ptd Page 9 1239086 V. Description of the invention (5) Semiconductor device with electronic functions required by the client. Involving different process operators (that is, including wafer carrier manufacturers and semiconductor packaging manufacturers), in the actual manufacturing process, not only the steps are cumbersome and the interface integration is not easy. Moreover, if the client wants to change the functional design, it involves changes and The integration level is more complicated, and it does not meet the demand for flexibility and economic benefits. [Summary of the Invention] In view of the shortcomings of the conventional technology described above, the main purpose of the present invention is to provide a circuit board structure that integrates semiconductor wafers and a manufacturing method thereof, and simultaneously integrate manufacturing processes of wafer carrier manufacturing and semiconductor packaging technologies. In order to provide greater flexibility in client demand, at the same time, it can simplify the process and interface integration of semiconductor industry. Still another object of the present invention is to provide a circuit board structure and a method for manufacturing the same that integrate a semiconductor wafer, so as to avoid various problems caused by the conventional electrical connection between the semiconductor wafer and the circuit board. Yet another object of the present invention is to provide a circuit board structure and a manufacturing method thereof for integrating a semiconductor wafer, so as to simplify the integrated form of the circuit board and the semiconductor wafer, thereby reducing manufacturing steps and costs. Another object of the present invention is to provide a circuit board structure and a manufacturing method thereof that integrate semiconductor wafers, so as to avoid the problem of overflow of glue generated during the conventional semiconductor packaging operation, and effectively improve the production quality and product reliability of semiconductor devices. In order to achieve the disclosure and other purposes, the method for manufacturing a circuit board of an integrated semiconductor wafer according to the present invention mainly provides a support board. The support board may be a general carrier board or a circuit board, and the support board is formed with at least one penetrating surface. Cut out
画_ 17813 全懋.ptd 第10頁 1239086 五、發明說明（6) ，俾於該開孔中收納有至少 體晶片；另提供一異方性導 性連接端之電路板，以間隔 承板與電路板，並使該電路 導電膠層而電性導接至收納 接端，藉以形成一整合半導 晶片之電性連接端係包含電 上之導電凸塊，另該晶片與 内部具有多數導電粒子之異 導接，節省習知電性導通製 與成本。 具有複數電性連接端之半導 ^膠層及一表面形成有複數電 4異方性導電膠層而壓合該支 板之電性連接端透過該異方性 方、"玄支承板中之晶片之電性連 體晶片之電路板結構。其中該 極銲墊以及形成於該電極銲墊 包路，間主要係可直接透過該 =性導電膠（ACF)層加以電性 牙王中之開口、電鍍等製程步驟 透 之電路 般之承 至少 開孔中 係間隔 方性導 接端。 單層或 該收納 晶式半 接所導 因 過前述製程， 板結構，主要 載板或電路板 一具有複數電 •’以及至少一 一異方 電膠層 其中該 多層電 有半導 導體封 致製程 此，透 性導電 電性導 電路板 路板， 體晶片 裝件製 繁瑣、 過本發 本發明亦揭 係包括有一 ，且該支承 性連接端之 表面具有複 膠層而於該 接該電路板 可為已形成 俾供後續得 之支承板上 程中晶片與 成本提升與 明之整合半 板形成有 半導體晶 數電性連 支承板接 與該半導 線路佈局 以直接將 ’藉以避 電路板間 信賴性不 導體晶片 整合半導體晶片 該支承板可為一 至少一 片，係 接端之 合，俾 體晶片 之增層 該電路 免習知 之接合 佳等缺 之電路 貫穿開 收納於 電路板 透過該 之電性 或壓合 板接合 打線或 與電性 失。 板結構Painting _ 17813 Quan 懋 .ptd Page 10 1239086 V. Description of the invention (6), at least a body chip is housed in the opening; a circuit board with anisotropic conductive connection ends is also provided, and the carrier board and the spacer are spaced apart. The circuit board and the conductive adhesive layer of the circuit are electrically connected to the receiving terminal, thereby forming an integrated semiconductor chip. The electrical connection end includes electrically conductive bumps, and the chip and the inside have a large number of conductive particles. The different connection can save the conventional electrical continuity system and cost. A semiconducting adhesive layer with a plurality of electrical connection ends and a surface with a plurality of electrical anisotropic conductive adhesive layers formed thereon to press the electrical connection ends of the support plate through the anisotropic square, " xuan support plate Circuit board structure of the electrical conjoined wafer of the wafer. The electrode pad and the electrode pad formed in the electrode pad can be directly opened through the == conductive conductive adhesive (ACF) layer in the electrical tooth king, and the circuit-like bearing through the process steps such as electroplating can be opened at least. Intermediate space square lead. The single-layer or the receiving crystal semi-conductor is caused by the aforementioned process, the board structure, the main carrier board or the circuit board has a plurality of electric charges, and at least one anisotropic electric glue layer, wherein the multi-layer electricity has a semiconducting conductor seal. In this process, the transparent conductive conductive circuit board circuit board and the body wafer assembly are cumbersome. According to the invention, the present invention also includes one, and the surface of the supporting connection end has an adhesive layer to connect the circuit. The board can be a support plate that has been formed for subsequent support. The chip is integrated with the cost increase and the half of the board is formed with a semiconductor crystal number electrically connected to the support board and the semiconducting circuit layout to directly avoid the trust between circuit boards. The non-conductor wafer integrates the semiconductor wafer. The support plate may be at least one piece, which is a combination of terminals. The carcass wafer is added to the circuit. The circuit is free of conventional joints. The missing circuit is stored in the circuit board and passes through the electrical property. Or the plywood bonding wire or electrical loss. Plate structure
17813全懋邛土(117813 Quantuo soil (1
第11 I !239〇86 五、發明說明（7) 其製法，主要 之半導體晶片 俾可縮短半導 外’本發明於 導電膠層而與 該電路板之電 至收納於該支 半導體晶片之 製造與半導體 性以及簡化半 知半導體封裝 【實施方式】 為使本發 與認同，茲配 發明可以多種 施例，而非用 請參閱第 電路板製法之 如第2A圖 為金屬板、絕 板2 2形成有至 側形成有一承 承載件21可為 表面接置於該 係可 ，並 體裝 該收 一已 性連 承板 電路 封裝 導體 製程 預先 將其 置之 納有 形成 接端 中之 板結 技術 業者 中之 提供 收納 整體 半導 線路 透過 晶片 構， 之製 製程 電性 至少一表面 於一 厚度 體晶 佈局 該異 之電 藉此 程， 與界 導接 形成有 ’以達 片之支 之電路 方性導 性連接 ，即可 俾提供 面協調 與模壓 形成有電 開孔之| 輕薄短+ 承板間隔 板進行墨 電膠層而 端，以形 結合晶片 客戶端較 問題，同 等問題。 性連接端 承板中， 目的；此 一異方性 合，並使 電性導接 成一整合 承載件之 大需求彈 時避免習 鄱 明之目的、 合詳細揭露 形式實施之 以限制本發 2 A至2 E圖， 剖面示意圖 所示，首先 緣板等各式 少一貫穿開 載件2 1，藉 一膠黏層俾 承載件2 1上 斗寸彳攻及功效，能更進一步的瞭解 及圖式詳加說明如后。當然，本 ’以下所述係為本發明之較佳實 明之範圍，合先敘明。 係為本發明之整合半導體晶片之 〇 提供一支承板2 2，該支承板2 2可 承載板甚或為電路板，且該支承 孔2 2 0。另可於該支承板2 2之一 ^封閉住該開孔22〇之一側，該 可供至少一半導體晶片2 3以其一 ’且收納於該支承板2 2之開孔Article 11 I! 239〇86 V. Description of the invention (7) The manufacturing method, the main semiconductor wafer can be shortened semi-conducting. The invention is made on the conductive adhesive layer and the circuit board is stored in the semiconductor wafer. And semiconductor properties and simplified semi-known semiconductor packaging [Embodiment] In order to make the present invention and identification, the invention can be implemented in a variety of embodiments, instead of referring to the circuit board manufacturing method, as shown in Figure 2A is a metal plate, insulation board 2 2 Formed to the side is formed a bearing carrier 21 which can be placed on the surface of the system, and can be assembled with the receiving circuit board circuit packaging conductor manufacturing process in advance to accommodate it in the formation of junction technology The industry provides integrated semi-conductor circuits through the wafer structure. The manufacturing process has at least one surface electrically arranged on a thickness of the bulk crystal. The different electrical processes are used to connect the circuit to the boundary conductor to form a circuit circuit of a branch. Conductive connection, that is, to provide surface coordination and molding to form electrical openings | light and short + carrier plate spacer plate for the end of the electro-electric adhesive layer, in combination with the chip End the more problems with other issues. The purpose of this connection is the heterosexuality and the electrical connection into an integrated carrier to avoid the need for Xi Mingming. The detailed disclosure is implemented to limit the issue. 2 A to 2 E As shown in the diagram, the cross-section diagram, first of all, one of the edge plates and one other type penetrates the load-opening member 21, and by using an adhesive layer and the load-bearing member 21, it can be further understood and detailed. The description is as follows. Of course, what is described below is the scope of the preferred embodiment of the present invention, and it will be described together. It is to provide a support plate 22 for the integrated semiconductor wafer of the present invention. The support plate 22 can carry a board or even a circuit board, and the support hole 2 2 0. In addition, one side of the support plate 22 may be closed on one side of the support plate 22, and at least one semiconductor wafer 23 may be received in one of the openings of the support plate 22 and received in the support plate 22.
1239086 五、發明說明（8) 2 2 〇中，並使该半導體晶片2 3電路面之電性連接端2 3 〇得以 顯露於該支承板22之開孔2 2 0。其中，該半導體晶片23之 電性連接端2 3 0係包括在晶片之電極銲墊2 3丨上附加電鍍形 成一導電凸塊232。 如第2B圖及第2C圖所示，另提供一異方性導電膠（ACf )廣2 4以及一已形成線路佈局之電路板2 5，該電路板2 5表 面形成有複數電性連接端2 5 0，且該電路板2 5之電性連接 端2 5 0位置，係對應於收納於該支承板開孔2 2 〇中之半導體 晶片2 3之電性連接端2 3 〇。 該異方性導電膠（ACF)層24可先接置於該内埋有半導 φ 體晶片2 3並顯露出其電性連接端2 3 0之支承板2 2之一側（ 如第2 B圖所示），俾於後續提供該支承板2 2得以間隔該異 方性導電膠（A C F )層2 4而與該電路板2 5進行壓合。當然， 亦可先將該異方性導電膠（ACF)層24接置於該電路板25上 - (未圖示），再與該支承板2 2進行壓合。其中，該異方性導 電膠層2 4主要係為在一膠黏層中佈設有導電粒子，俾可提 供後續承載與電性導接使用，且該異方性導電膠層2 4係可 充填於該支承板開孔2 2 0之殘餘間隙中，亦或可先以額外 之絕緣膠充填於該支承板開孔2 2 0殘餘間隙中，再於該支 承板2 2與電路板2 5間形成該異方性導電膠層2 4。 <1 另外，雖本發明之實施態樣之圖式中，該電路板係為 一增層形式之四層電路板，然於實際上製程該電路板之形 式可為任意之增層或壓合之單層或多層電路板，且由於該 電路板之製程係為習知技術，故於此不再為文贅述。1239086 5. In the description of the invention (8) 2 2 0, the electrical connection end 2 3 0 of the circuit surface of the semiconductor wafer 2 3 can be exposed in the opening 2 2 0 of the support plate 22. Wherein, the electrical connection end 2 3 0 of the semiconductor wafer 23 includes a conductive bump 232 which is additionally plated on the electrode pads 2 3 丨 of the wafer. As shown in FIG. 2B and FIG. 2C, an anisotropic conductive adhesive (ACf) can be provided, and a circuit board 25 having a circuit layout has been formed, and a plurality of electrical connection terminals are formed on the surface of the circuit board 25. 2 50, and the position of the electrical connection terminal 250 of the circuit board 25 corresponds to the electrical connection terminal 2 3 of the semiconductor wafer 23 accommodated in the opening 220 of the support plate. The anisotropic conductive adhesive (ACF) layer 24 may be first placed on one side of the support plate 2 2 in which the semiconducting φ-body wafer 23 is embedded and the electrical connection end 2 3 0 is exposed (such as the second (Shown in FIG. B), the support plate 22 is subsequently provided to be laminated with the circuit board 25 through the anisotropic conductive adhesive (ACF) layer 24. Of course, the anisotropic conductive adhesive (ACF) layer 24 can also be first placed on the circuit board 25-(not shown), and then pressed against the support plate 22. The anisotropic conductive adhesive layer 24 is mainly provided with conductive particles in an adhesive layer, which can provide subsequent carrying and electrical conduction. The anisotropic conductive adhesive layer 24 can be filled. In the remaining gap of the supporting board opening 2 220, or may be filled with additional insulating glue in the remaining gap of the supporting board opening 2 220, and then between the supporting board 22 and the circuit board 25. The anisotropic conductive adhesive layer 24 is formed. < 1 In addition, although the circuit board in the embodiment of the present invention is a four-layer circuit board in the form of a layer, in fact, the form of the circuit board can be any layer or layer. It is a single-layer or multi-layer circuit board, and since the manufacturing process of the circuit board is a conventional technology, it will not be described in detail here.
178]3全懋邛士(1 第13頁 1239086178] 3 full martyr (1 p. 13 1239086
1239086 五、發明說明（ίο) 外，本發明於該收納有半導體晶片之支承板間隔一異方性 導電膠層而與一已形成線路佈局之電路板進行壓合，並使 該電路板之電性連接端透過該異方性導電膠層而電性導接 至收納於該支承板中之晶片之電性連接端，以形成一整合 半導體晶片之電路板結構，藉此，即可結合晶片承載件之 製造與半導體封裝技術之製程，俾提供客戶端較大需求彈 性以及簡化半導體業者製程與界面協調問題，同時避免習 知半導體封裝製程中之電性導接與模壓等問題。 惟以上所述之具體實施例，僅係用以例釋本發明之特 點及功效，而非用以限定本發明之可實施範疇，在未脫離 ❶ 本發明上揭之精神與技術範疇下，任何運用本發明所揭示 内容而完成之等效改變及修飾，均仍應為下述之申請專利 . 範圍所涵蓋。1239086 V. Description of the invention (ίο) In addition, the present invention holds the semiconductor wafer on the support board with an anisotropic conductive adhesive layer and press-fits it with a circuit board that has formed a circuit layout. The conductive connection end is electrically connected to the electrical connection end of the wafer accommodated in the support board through the anisotropic conductive adhesive layer to form a circuit board structure that integrates the semiconductor wafer, thereby, the wafer can be combined with the carrier. The process of component manufacturing and semiconductor packaging technology provides customers with greater flexibility in demand and simplifies the process of semiconductor industry process and interface coordination, while avoiding the problems of electrical conduction and molding in the conventional semiconductor packaging process. However, the specific embodiments described above are only used to illustrate the features and effects of the present invention, rather than to limit the implementable scope of the present invention. Without departing from the spirit and technical scope of the invention disclosed above, any Equivalent changes and modifications made using the disclosure of the present invention should still be covered by the following patent applications.
17813全懋.口士(1 第15頁 1239086 圖式簡單說明 【圖式簡單說明】 第1 A及1 B圖係習知之覆晶式半導體封裝件之剖面示意 圖；以及 第2 A至2 E圖係本發明之整合半導體晶片之電路板製法 之剖面示意圖。 (元科 -符 號 說 明 ) 11 金 屬 凸 塊 12 電 極 銲 墊 13 半 導 體 晶 片 14 銲 錫 凸 塊 15 接 觸 銲 墊 16 電 路 板 17 銲 錫 接 18 底 膠 材 料 21 承 載 件 22 支 承 板 220 開 孔 23 半 導 體 晶 片 230 電 性 連 接 端 231 電 極 銲 墊 232 導 電 凸 塊 24 異 方 性 導 電膠層 240 導 電 粒 子 25 電 路 板 250 電 性 連 接 端17813 Quan Yi. Mouth (1 Page 15 1239086 Brief Description of Drawings [Simplified Description of Drawings] Figures 1 A and 1 B are cross-sectional schematic diagrams of conventional flip-chip semiconductor packages; and Figures 2 A to 2 E It is a schematic cross-sectional view of the method for manufacturing a circuit board with integrated semiconductor wafers of the present invention. (Yuanke-Symbol Description) 11 Metal bumps 12 Electrode pads 13 Semiconductor wafers 14 Solder bumps 15 Contact pads 16 Circuit boards 17 Solder connections 18 Primer Material 21 Carrier 22 Support board 220 Opening hole 23 Semiconductor wafer 230 Electrical connection terminal 231 Electrode pad 232 Conductive bump 24 Anisotropic conductive adhesive layer 240 Conductive particle 25 Circuit board 250 Electrical connection terminal
17813 全懋.ptd 第16頁17813 懋 .ptd Page 16
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW093119372A TWI239086B (en) | 2004-06-30 | 2004-06-30 | Circuit board structure integrated with semiconductor chip and method for fabricating the same |
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| Application Number | Priority Date | Filing Date | Title |
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| TW093119372A TWI239086B (en) | 2004-06-30 | 2004-06-30 | Circuit board structure integrated with semiconductor chip and method for fabricating the same |
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| TWI239086B true TWI239086B (en) | 2005-09-01 |
| TW200601524A TW200601524A (en) | 2006-01-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI449657B (en) * | 2008-07-04 | 2014-08-21 | Hon Hai Prec Ind Co Ltd | Micro electro-mechanical system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI449657B (en) * | 2008-07-04 | 2014-08-21 | Hon Hai Prec Ind Co Ltd | Micro electro-mechanical system |
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| TW200601524A (en) | 2006-01-01 |
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