TW200601524A - Circuit board structure integrated with semiconductor chip and method for fabricating the same - Google Patents
Circuit board structure integrated with semiconductor chip and method for fabricating the sameInfo
- Publication number
- TW200601524A TW200601524A TW093119372A TW93119372A TW200601524A TW 200601524 A TW200601524 A TW 200601524A TW 093119372 A TW093119372 A TW 093119372A TW 93119372 A TW93119372 A TW 93119372A TW 200601524 A TW200601524 A TW 200601524A
- Authority
- TW
- Taiwan
- Prior art keywords
- circuit board
- semiconductor chip
- fabricating
- same
- structure integrated
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
Abstract
A circuit board structure integrated with semiconductor chip and a method for fabricating the same are proposed, wherein a supporting plate formed with at least an opening is provided and a semiconductor chip formed with a plurality of pads is embedded in the opening. An anisotropic conductive film and a circuit board formed with electrical connections are provided. The circuit board and the supporting plate are compressed with the anisotropic conductive film, wherein the electrical connections of the circuit board are electrically connected to the pads of the chip embedded in the supporting plate by the anisotropic film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093119372A TWI239086B (en) | 2004-06-30 | 2004-06-30 | Circuit board structure integrated with semiconductor chip and method for fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093119372A TWI239086B (en) | 2004-06-30 | 2004-06-30 | Circuit board structure integrated with semiconductor chip and method for fabricating the same |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI239086B TWI239086B (en) | 2005-09-01 |
TW200601524A true TW200601524A (en) | 2006-01-01 |
Family
ID=37001186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093119372A TWI239086B (en) | 2004-06-30 | 2004-06-30 | Circuit board structure integrated with semiconductor chip and method for fabricating the same |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI239086B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI449657B (en) * | 2008-07-04 | 2014-08-21 | Hon Hai Prec Ind Co Ltd | Micro electro-mechanical system |
-
2004
- 2004-06-30 TW TW093119372A patent/TWI239086B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TWI239086B (en) | 2005-09-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |