TWI478257B - 封裝結構及封裝製程 - Google Patents

封裝結構及封裝製程 Download PDF

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TWI478257B
TWI478257B TW098126532A TW98126532A TWI478257B TW I478257 B TWI478257 B TW I478257B TW 098126532 A TW098126532 A TW 098126532A TW 98126532 A TW98126532 A TW 98126532A TW I478257 B TWI478257 B TW I478257B
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Taiwan
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electronic component
conductive blocks
conductive
pads
insulating paste
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TW098126532A
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TW201106435A (en
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Chien Liang Lee
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Htc Corp
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Priority to TW098126532A priority Critical patent/TWI478257B/zh
Priority to US12/635,701 priority patent/US8697489B2/en
Priority to EP10150506A priority patent/EP2284880A1/en
Publication of TW201106435A publication Critical patent/TW201106435A/zh
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Publication of TWI478257B publication Critical patent/TWI478257B/zh

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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Description

封裝結構及封裝製程
本發明是有關於一種封裝結構及其製作方法，且特別是有關於一種將絕緣膠之固化與導電塊之回焊整合於同一加熱步驟進行的封裝結構及其製作方法。
近年來，積體電路技術與材料進步快速，其晶片之體積日益縮小，但功能卻日益強大，應用之廣泛可說是無遠弗屆，因此利用積體電路技術所生產之產品已漸朝向輕薄短小之型態，舉凡手持電子裝置、電子辭典、數位相機及各種數位產品等等不勝枚舉。
表面接合技術(Surface Mounting Technology,SMT)是常見用來接合積體電路電子元件與電路板或其他元件的技術，其優點在於可縮小整體封裝結構的尺寸，而有助於電子裝置的微型化發展。
已知的表面接合技術會在電子元件與電路板接合之後，對電子元件與電路板之間的導電塊進行一回焊步驟，使導電塊成為熔融狀態或半熔融狀態，以藉由導電塊連接電子元件與電路板。之後，再於電子元件與電路板之間填入底膠，並對底膠進行固化步驟。一般而言，對導電塊所進行的回焊溫度需高於導電塊的熔點，而固化底膠時的加熱溫度會遠低於導電塊的回焊溫度。
然而，已知表面接合技術需在回焊導電塊之後另外進行底膠製程，製程步驟較為複雜，容易影響製程良率。此外，由於固化底膠的製程條件與回焊導電塊的製程條件不同，因此須個別設置兩套相應的製程設備，造成生產成本上的負擔。
另一方面，已知表面接合技術形成底膠的方法是在電子元件與電路板接合之後，在接合處的外側進行點膠，使底膠藉由虹吸現象進入電子元件與電路板之間的空隙，以包覆導電塊。惟，此種點膠方式會在電子元件外側周圍殘留部分的底膠，而影響封裝結構的外觀。
本發明提供一種封裝製程，其製程步驟簡單，可降低製作成本，並且提高製程良率與生產效率。
本發明提供一種封裝結構，可避免底膠外露的問題，改善產品的外觀。
為具體描述本發明之內容，在此提出一種封裝製程。首先，提供一第一電子元件，此第一電子元件底部具有多個第一導電塊。接著，塗佈一第一絕緣膠於所述多個第一導電塊上。然後，將第一電子元件放置於一線路基板上。此線路基板具有多個基板接墊，而所述多個第一導電塊分別座落於該些基板接墊上。之後，同時對第一導電塊與第一絕緣膠進行一加熱步驟，以回焊第一導電塊，使第一導電塊連接第一電子元件以及所對應的基板接墊，並且固化第一絕緣膠。
在一實施例中，第一導電塊在進行上述加熱步驟之前保持固態。
在一實施例中，所述封裝製程更包括在進行加熱步驟之前進行下列步驟。首先，提供一第二電子元件，其底部具有多個第二導電塊。接著，塗佈一第二絕緣膠於第二導電塊上。然後，放置第二電子元件於第一電子元件上，其中第一電子元件具有多個第一接墊，而所述多個第二導電塊分別座落於該些第一接墊上。
在一實施例中，所述封裝製程更藉由該加熱步驟同時對第二導電塊以及第二絕緣膠進行加熱，以回焊第二導電塊，使第二導電塊連接第二電子元件以及所對應的第二接墊，並且固化第二絕緣膠。
在一實施例中，第二導電塊在進行該加熱步驟之前保持固態。
在一實施例中，所述加熱步驟的溫度介於200℃至260℃之間。
在一實施例中，所述封裝製程更包括在放置第一電子元件於線路基板之前，形成一預銲料於每一基板接墊上，以在回焊第一導電塊之後，使第一導電塊分別與所對應的預銲料相互結合。
本發明更提出一種封裝結構，包括一線路基板、一第一電子元件、多個第一導電塊以及一第一絕緣膠。線路基板具有多個基板接墊，而第一電子元件配置於線路基板上。所述多個第一導電塊配置於該第一電子元件與該線路基板之間，其中每一第一導電塊連接第一電子元件以及所對應的基板接墊。第一絕緣膠配置於第一電子元件與線路基板之間。此外，第一電子元件在線路基板上具有一第一垂直投影區域，且第一絕緣膠位於第一垂直投影區域內。
在一實施例中，所述封裝結構更包括一第二電子元件、多個第二導電塊以及一第二絕緣膠。第二電子元件配置於第一導電元件上，而第一導電元件具有多個第一接墊。所述多個第二導電塊位於第二電子元件與第一電子元件之間，其中每一第二導電塊連接第二電子元件以及所對應的第一接墊。第二絕緣膠配置於第二電子元件與第一電子元件之間。此外，第二電子元件在第一電子元件上具有一第二垂直投影區域，且第二絕緣膠位於第二垂直投影區域內。
基於上述，本發明的封裝製程藉由同一道加熱步驟來回焊導電塊以及固化絕緣膠，因此製程上比習知在電子元件接合後另外形成底膠的技術簡單，可避免複雜的製程步驟造成的良率問題，同時亦有助於減少製程設備、材料與人力成本，提高生產效率。另一方面，由於利用此封裝製程所形成的封裝結構是在接合電子元件之前就先在導電塊上形成絕緣膠，因此在接合電子元件並且進行加熱步驟之後，絕緣膠不會外露於電子元件之外，使得封裝結構具有良好的外觀。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
本發明是在電子元件接合之前先將液態或是半固態的絕緣膠塗佈於導電塊上，並且在電子元件接合之後而回焊導電塊的同時一併固化絕緣膠。換言之，本發明的封裝製程僅需進行一道加熱步驟便可同時完成導電塊的回焊與絕緣膠的固化，其中溫度被控制在可讓導電塊達到熔融狀態或半熔融狀態的範圍。舉例而言，導電塊的材質可以是無鉛銲料，而適用的加熱溫度例如是介於200℃至260℃之間。
另外，本發明所提出的封裝製程可應用於單一電子元件的封裝結構或是堆疊式封裝結構(package on package structure,POP structure)上。換言之，前述用以固化絕緣膠與回焊導電塊的加熱步驟不僅可用於電子元件與線路基板的接合，也可以用於兩堆疊之電子元件的接合。
以下將以多個實施例來說明本發明之封裝製程以及所形成之封裝結構。
圖1為依據本發明之一實施例的一種封裝製程的流程圖。圖2A-2D依序繪示此封裝製程的各步驟。
首先，如步驟110與圖2A所示，提供一第一電子元件210，此第一電子元件210底部具有多個第一導電塊212。在此，第一電子元件210例如是封裝完成的中央處理單元(CPU)，其包括一第一承載器214以及位於第一承載器214上的第一晶片216。第一導電塊212位於第一承載器214底部，例如是陣列配置的球狀銲料塊，其形成於第一承載器214底部的多個銲墊218上，以經由第一承載器214電連接到第一晶片216。在此，第一導電塊212例如是無鉛錫球。
接著，如步驟120與圖2B所示，塗佈一第一絕緣膠220於第一導電塊212上。在本實施例中，例如是採用浸漬(dipping)法將第一電子元件210的第一導電塊212置入一容器710盛裝的絕緣膠溶液720中，以使每一第一導電塊212同時沾附第一絕緣膠220。採用浸漬(dipping)法的優點在於步驟簡單且快速。當然，本實施例用以第一導電塊212上塗佈第一絕緣膠220的方法並不限於此，本領域中具有通常知識者可依所處時點的技術水平採用其他如印刷(printing)、噴塗(spraying)等方式來形成第一絕緣膠220於第一導電塊212上。
然後，如步驟130與圖2C所示，放置第一電子元件210於一線路基板230上。本實施例之線路基板230的一承載面230a上具有對應於第一導電塊212的多個基板接墊232。第一電子元件210被放置於承載面230a上，且第一導電塊212分別座落於基板接墊232上。本實施例還可以選擇在步驟130之前，先形成一預銲料(pre-solder)234於每一基板接墊232上，以提高後續製程中第一導電塊212的接合效果。此處的預銲料234例如是以印刷方式形成的錫膏。
之後，如步驟140與圖2D所示，同時對第一導電塊212與第一絕緣膠220進行一加熱步驟，以回焊第一導電塊212並且固化第一絕緣膠220。第一導電塊212被回焊時會先成為熔融或半熔融狀態，以分別與第一電子元件210底部的銲墊218以及線路基板230的基板接墊232接合，並且會在冷卻後連接銲墊218以及所對應的基板接墊232。此外，若如前述先在每一基板接墊232上形成預銲料234，則回焊時第一導電塊212會分別與所對應的預銲料234相互結合。另一方面，第一絕緣膠220在第一電子元件210與線路基板230接合後會填入第一導電塊212之間的空隙，並包覆第一導電塊212，且會在此加熱步驟中被固化。然而，第一絕緣膠220並不限定需填滿第一導電塊212之間的空隙，即第一絕緣膠220也可以僅填滿第一導電塊212之間的部份空隙，而不會完全包覆第一導電塊212。或者，在實際的製程中，第一絕緣膠220內部也可能會含有氣泡。
實作上，前述加熱步驟的溫度取決於第一導電塊212以及第一絕緣膠220的材質。由於第一導電塊212的熔點通常會高於第一絕緣膠220的固化溫度，因此所述加熱步驟設定的溫度需高於第一導電塊212的熔點。就本實施例而言，第一導電塊212的材質例如是無鉛銲料，其適用的加熱步驟的溫度例如是介於200℃至260℃之間。
本實施例在第一電子元件210與線路基板230接合之前先將第一絕緣膠220塗佈於第一導電塊212上，並且在第一電子元件210與線路基板230接合之後，僅藉由一道加熱步驟來同時完成第一導電塊212的回焊與第一絕緣膠220的固化。換言之，第一導電塊212例如是在加熱步驟之前保持固態，待進行加熱步驟時，才與第一電子元件210以及線路基板230接合。
本實施例的封裝製程藉由同一道加熱步驟來回焊導電塊以及固化絕緣膠，因此可以簡化製程步驟，減少製程的良率問題，同時亦有助於降低製程設備、材料與人力成本，提高生產效率。
圖3為前述實施例之封裝結構的上視圖。如圖3所示，由於利用前述封裝製程所形成的封裝結構是在接合第一電子元件210之前就先在第一導電塊212上形成第一絕緣膠220，因此在接合第一電子元件210與線路基板230並且進行加熱步驟之後，第一絕緣膠220會進入第一導電塊212之間的空隙，但不會外露於第一電子元件210之外。換言之，第一電子元件210在線路基板230上具有一第一垂直投影區域R1，且第一絕緣膠220位於第一垂直投影區域R1內。如此一來，可解決已知點膠製程會在電子元件外側周圍殘留底膠的問題，而大幅美化封裝結構的外觀。
在前述實施例的基礎上，本發明還可進一步實現堆疊式(POP)封裝製程的簡化。
圖4為依據本發明之另一實施例的一種封裝製程的流程圖。圖5A-5F依序繪示此封裝製程的各步驟。
首先，本實施例可如前述實施例步驟110~130所述，提供第一電子元件210(圖5A參照)；塗佈第一絕緣膠220於第一電子元件210底部的第一導電塊212上(圖5B參照)；以及，放置第一電子元件210於一線路基板230上(圖5C參照)。由於所述步驟與前述實施例類似，本實施例以相同標號來表示該些步驟與元件，且不再重複說明相關技術內容。惟，由於本實施例需在第一電子元件210堆疊另一第二電子元件，因此第一電子元件210上另具有多個第一接墊219，以供後續第二電子元件的接合之用。
如步驟410與圖5D所示，本實施例提供一第二電子元件510，此第二電子元件510底部具有多個第二導電塊512。在此，第二電子元件510例如是封裝完成的記憶體(MEMORY)單元，其包括一第二承載器514以及位於第二承載器514上的第二晶片516。第二導電塊512位於第一承載器514底部，例如是陣列配置的球狀銲料塊，其形成於第二承載器514底部的多個銲墊518上，以經由第二承載器514電連接到第二晶片516。在此，第二導電塊512例如是無鉛錫球。
此外，如步驟420所示，並同時參照圖5D所示，塗佈一第二絕緣膠520於第二導電塊512上。在本實施例中，例如是採用浸漬(dipping)法將第二電子元件510的第二導電塊512置入一容器810盛裝的絕緣膠溶液820中，以使每一第二導電塊512同時沾附第二絕緣膠520。此處的第二絕緣膠520可與第一絕緣膠220具有相同或是不同的材質，以滿足不同的設計需求。舉例而言，選用相同材質有助於減少材料成本、簡化製程參數的設定，而選用不同材質可達到接合處的應力緩衝或強化接合強度等效果。
然後，如步驟430與圖5E所示，放置第二電子元件510於第一電子元件210上，其中第二導電塊512分別座落於第一接墊219上。
之後，如步驟440與圖5F所示，同時對第一導電塊212、第一絕緣膠220、第二導電塊512以及第二絕緣膠520進行一加熱步驟，以回焊第一導電塊212以及第二導電塊512，並且固化第一絕緣膠220以及第二絕緣膠520。第一導電塊212被回焊時會先成為熔融或半熔融狀態，以分別與第一電子元件210底部的銲墊218以及線路基板230的基板接墊232接合，並且會在冷卻後連接銲墊218以及所對應的基板接墊232。此外，若如前述先在每一基板接墊232上形成預銲料234，則回焊時第一導電塊212會分別與所對應的預銲料234相互結合。
第二導電塊512被回焊時會先成為熔融或半熔融狀態，以分別與第二電子元件510底部的銲墊518以及第一電子元件210頂部的第一接墊219接合，並且會在冷卻後連接銲墊518以及所對應的第一接墊219。
另一方面，如同前一實施例所述，第一絕緣膠220在第一電子元件210與線路基板230接合後會進入第一導電塊212之間的空隙，並且會在此加熱步驟中被固化。
此外，第二絕緣膠520在第二電子元件510與第一電子元件210接合後會填入第二導電塊512之間的空隙，並包覆第二導電塊512，且會在此加熱步驟中被固化。類似地，此處的第二絕緣膠520並不限定需填滿第二導電塊512之間的空隙，即第二絕緣膠220也可以僅填滿第二導電塊512之間的部份空隙，而不會完全包覆第二導電塊512。或者，在實際的製程中，第二絕緣膠520內部也可能會含有氣泡。
實作上，前述加熱步驟的溫度取決於第一導電塊212、第二導電塊512、第一絕緣膠220以及第二絕緣膠520的材質。由於第一導電塊212的熔點通常會高於第一絕緣膠220的固化溫度，而第二導電塊512的熔點通常會高於第二絕緣膠520的固化溫度，因此所述加熱步驟設定的溫度需高於第一導電塊212與第二導電塊512的熔點。就本實施例而言，第一導電塊212與第二導電塊512的材質例如皆是無鉛銲料，其適用的加熱步驟的溫度例如是介於200℃至260℃之間。
本實施例在第一電子元件210與線路基板230接合之前先將第一絕緣膠220塗佈於第一導電塊212上，並且第二電子元件510與第一電子元件210接合之前先將第二絕緣膠520塗佈於第二導電塊512上，待第一電子元件210與線路基板230接合以及第二電子元件510與第一電子元件210接合之後，僅藉由一道加熱步驟來同時完成第一導電塊212的回焊、第二導電塊512的回焊、第一絕緣膠220的固化以及第二絕緣膠520的固化。換言之，第一導電塊212以及第二導電塊512可在加熱步驟之前保持固態，待進行加熱步驟時，才成為熔融或半熔融狀態。
前述實施例的堆疊式封裝製程係藉由同一道加熱步驟來回焊所有的導電塊以及固化所有的絕緣膠，因此可以簡化製程步驟，減少製程的良率問題，同時亦有助於降低製程設備、材料與人力成本，提高生產效率。
圖6為前述實施例之堆疊式封裝結構的上視圖。如圖6所示，由於利用前述封裝製程所形成的封裝結構是在接合第二電子元件510與第一電子元件210之前就先在第二導電塊512上形成第二絕緣膠520，因此在接合第二電子元件510與第一電子元件210並且進行加熱步驟之後，第二絕緣膠520會進入第二導電塊512之間的空隙，但不會外露於第二電子元件510之外。換言之，第二電子元件510在第一電子元件210上具有一第二垂直投影區域R2，且第二絕緣膠520位於第二垂直投影區域R2內。同理，請同時參見圖3，第一絕緣膠220也會進入第一導電塊212之間的空隙，但不會外露於第一電子元件210之外。換言之，第一電子元件210在線路基板230上具有一第一垂直投影區域R，且第一絕緣膠220位於第一垂直投影區域R內。如此一來，可解決已知點膠製程會在電子元件外側周圍殘留底膠的問題，而大幅美化封裝結構的外觀。
綜上所述，本發明不僅製程步驟簡單，可避免複雜製程步驟造成的良率問題，更可降低製程設備、材料與人力成本，並且提高製程良率與生產效率。在結構上，本發明的封裝結構可避免已知技術中底膠外露的問題，使得封裝結構具有良好的外觀。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
110~140、410~440．．．製程步驟
210．．．第一電子元件
212．．．第一導電塊
214．．．第一承載器
216．．．第一晶片
218．．．銲墊
219．．．第一接墊
220．．．第一絕緣膠
230．．．線路基板
230a．．．承載面
232．．．基板接墊
234．．．預銲料
510．．．第二電子元件
512．．．第二導電塊
514．．．第二承載器
516．．．第二晶片
518．．．銲墊
520．．．第二絕緣膠
710．．．容器
720．．．絕緣膠溶液
810．．．容器
820．．．絕緣膠溶液
R1．．．第一垂直投影區域
R2．．．第二垂直投影區域
圖1為依據本發明之一實施例的一種封裝製程的流程圖。
圖2A-2D依序繪示圖1的封裝製程的各步驟。
圖3為依據本發明之一實施例的一種封裝結構的上視圖。
圖4為依據本發明之另一實施例的一種封裝製程的流程圖。
圖5A-5F依序繪示圖4的封裝製程的各步驟。
圖6為依據本發明之另一實施例的一種堆疊式封裝結構的上視圖。
110~140‧‧‧製程步驟

Claims (10)

  1. 一種封裝製程，包括：提供一第一電子元件，該第一電子元件底部具有多個第一導電塊；塗佈一第一絕緣膠於該些第一導電塊上；放置該第一電子元件於一線路基板上，該線路基板具有多個基板接墊，而該些第一導電塊分別座落於該些基板接墊上，其中在使該些第一導電塊座落於該些基板接墊之前，該第一絕緣膠會覆蓋每一第一導電塊用以與相應的該基板接墊接合的末端表面；以及對該些第一導電塊與該第一絕緣膠進行一加熱步驟，以回焊該些第一導電塊，並在回焊該些第一導電塊的同時固化該第一絕緣膠，其中該些第一導電塊經由回焊而連接該第一電子元件以及所對應的該些基板接墊。
  2. 如申請專利範圍第1項所述之封裝製程，其中該些第一導電塊在進行該加熱步驟之前保持固態。
  3. 如申請專利範圍第2項所述之封裝製程，其中該加熱步驟的溫度介於200℃至260℃之間。
  4. 如申請專利範圍第1項所述之封裝製程，更包括在進行該加熱步驟之前進行下列步驟：提供一第二電子元件，該第二電子元件底部具有多個第二導電塊；塗佈一第二絕緣膠於該些第二導電塊上；以及放置該第二電子元件於該第一電子元件上，該第一電 子元件具有多個第一接墊，而該些第二導電塊分別座落於該些第一接墊上。
  5. 如申請專利範圍第4項所述之封裝製程，其中藉由該加熱步驟同時對該些第二導電塊以及該第二絕緣膠進行加熱，以回焊該些第二導電塊，使該些第二導電塊連接該第二電子元件以及所對應的該些第二接墊，並且固化該第二絕緣膠。
  6. 如申請專利範圍第5項所述之封裝製程，其中該些第二導電塊在進行該加熱步驟之前保持固態。
  7. 如申請專利範圍第6項所述之封裝製程，其中該加熱步驟的溫度介於200℃至260℃之間。
  8. 如申請專利範圍第1項所述之封裝製程，更包括在放置該第一電子元件於該線路基板之前，形成一預銲料於每一基板接墊上，以在回焊該些第一導電塊之後，使該些第一導電塊分別與所對應的該些預銲料相互結合。
  9. 一種封裝結構，包括：一線路基板，具有多個基板接墊；一第一電子元件，配置於該線路基板上；多個第一導電塊，每一第一導電塊連接該第一電子元件以及所對應的該基板接墊；以及一第一絕緣膠，配置於該第一電子元件與該線路基板之間，該第一電子元件在該線路基板上具有一第一垂直投影區域，且該第一絕緣膠位於該第一垂直投影區域內並且暴露出該第一電子元件面對該線路基板的一表面的週邊部 分以及該第一垂直投影區域的週邊部分，其中該第一電子元件用以與該第一絕緣膠的邊緣鄰接的一第一部分是平坦的，且該線路基板用以與該第一絕緣膠的邊緣鄰接的一第二部分是平坦的。
  10. 如申請專利範圍第9項所述之封裝結構，更包括：一第二電子元件，配置於該第一電子元件上，該第一電子元件具有多個第一接墊；多個第二導電塊，每一第二導電塊連接該第二電子元件以及所對應的該第一接墊；以及一第二絕緣膠，配置於該第二電子元件與該第一電子元件之間，該第二電子元件在該第一電子元件上具有一第二垂直投影區域，且該第二絕緣膠位於該第二垂直投影區域內。
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