TWI495021B - 半導體封裝結構的製造方法 - Google Patents

半導體封裝結構的製造方法 Download PDF

Info

Publication number
TWI495021B
TWI495021B TW101132467A TW101132467A TWI495021B TW I495021 B TWI495021 B TW I495021B TW 101132467 A TW101132467 A TW 101132467A TW 101132467 A TW101132467 A TW 101132467A TW I495021 B TWI495021 B TW I495021B
Authority
TW
Taiwan
Prior art keywords
wafer
cured
lead frame
conductive paste
array
Prior art date
Application number
TW101132467A
Other languages
English (en)
Other versions
TW201312669A (zh
Inventor
Geng Hsin Shen
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Publication of TW201312669A publication Critical patent/TW201312669A/zh
Application granted granted Critical
Publication of TWI495021B publication Critical patent/TWI495021B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14151—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/14155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/16257—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/16258—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/81856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

半導體封裝結構的製造方法
本發明係關於一種半導體元件封裝結構，特別是關於一導線架結構用以控制半導體元件封裝過程中的材料溢流。
隨著半導體科技的日新月異，電子產業經歷了由體積厚薄的快速變革，以及從不停歇的微小化製程改良。半導體封裝是一門建立半導體元件之間連結以形成一電路的科學，也因應半導體與電子產業的不斷進步而快速發展。
半導體封裝通常包含一導線架用以電連接一個或多個半導體元件，例如積體電路晶粒。一般而言，與該導線架連接的晶粒通常藉由打線製程與該導線架的引腳電連接，爾後一封膠體將覆蓋並密封該導線架、該連接線、以及該積體電路晶粒，以完成封裝製程。封裝的主要目的在於確保半導體元件以及其連接結構有效且妥善地被保護。
近來覆晶式封裝變成一種普遍的方法用於電連接積體電路晶片至一基板或導線架上。更明確地說，在製程中，錫凸塊被置放在該晶片的上表面，而該晶片經翻轉並使其上的導電接墊與該基板上的導電接墊相接。接續加熱該覆晶與該基板並使錫凸塊熔融於該基板的導電接墊之上，該覆晶與該基板接著冷卻以凝固該錫凸塊，以完成該電連接結構。傳統上一旦該覆晶與該基板連結，一底部充膠材料，通常是一種液體黏接用樹脂，設置於該晶片以及該基板中 間。該底部充膠材料提供該晶片以及該基板間結構上的連結以及熱穩定，並避免環境的干擾。
圖1A顯示習知的覆晶結構10剖面圖，該結構包含主動面朝下的一晶片101，用以與一導線架(未顯示)的引腳103電連接的複數個凸塊105。當該晶片稍微被下壓並加熱以進一步與該引腳103連接，該凸塊105有可能因為尚未凝固而變形。蜝至於該凸塊105會擴散溢流到(見圖1B中的107)該引腳103的下表面，這種情況會造成封裝結構的缺陷。此問題亦會在該覆晶的凸塊植入該引腳103上的導電膠時發生，由於導電膠也會擴散溢流並造成封裝結構的缺陷。因此，開發一種新型改良的導線架結構用以容納與限制該溢流材料以避免封裝缺陷確實有其必要。
本發明之其一目的在於提供一覆晶半導體封裝方法，該方法可以避免封裝缺陷並進一步增進元件封裝效率及可靠度。
本發明另一目的在於提供一覆晶半導體封裝方法，該方法可以藉由本發明之導線架引腳的一凹槽結構容納與限制半固化材料的溢流。
本發明另一目的在於提供一覆晶半導體封裝方法，該方法可以用於製造一預成型(pre-molded)半導體封裝結構。
本發明另一目的在於提供一種半導體封裝結構的製造 方法，該方法包含形成複數個導電膠於一陣列式導線架的引腳上，其中一凹槽設置於該引腳上與該各導電膠具一預定距離；半固化該導電膠，使得該導電膠處於半固化及黏稠的狀態；提供具有複數個凸塊的至少一晶片；電連接該晶片與該導線架陣列的引腳，藉由植入該凸塊至該半固化的導電膠，其中該凹槽用以容納與限制該半固化導電膠的溢流；固化該半固化導電膠以緊密接合該晶片；以及形成一封膠體覆蓋該導線架以及該晶片。
在一實施例中，其中提供具有複數個凸塊的至少一晶片的步驟包含形成金凸塊、銅凸塊、結線金凸塊、結線銅凸塊，或金/銅合金凸塊。在另一實施例中，該形成一封膠體覆蓋該導線架以及該晶片的步驟是藉由注塑成型、包覆成型、或底部注膠的方式形成。在另一實施例中，該熱固性導電膠的Tg (玻璃轉換溫度)介於攝氏-40度至175度之間。
另一方面，本發明有一種半導體封裝結構，包含一陣列式的導線架，具有複數個內引腳以及外引腳；一凹槽，設置於該任一內引腳上；一半導體晶片，具有複數個凸塊用以電性連接該半導體晶片以及該內引腳；複數個半固化的導電膠，用以接合該半導體晶片於該內引腳之上；以及一封膠體，用以密封並覆蓋該半導體晶片以及該導線架；其中該熱固性導電膠設置於引腳上與引腳邊緣具一預定距離處，且該凹槽設置於該引腳上與該各導電膠具一預定距離處。當該晶片上的凸塊嵌入該導電膠，該凹槽之配置可 用以容納與限制該半固化導電膠的溢流，且藉由該半固化的導電膠充分固化後緊密接合該陣列式導線架上的晶片。
在一實施例中，該凸塊包含金凸塊、銅凸塊、結線金凸塊、結線銅凸塊，或金/銅合金凸塊。在另一實施例中，該導線架是一預成型(pre-molded)導線架陣列。在另一實施例中，該凹槽可以利用顯影或蝕刻製程形成。
另一方面，本發明有一種預成型(pre-molded)導線架封裝的製造方法，該方法包含形成一半固化的封膠體於一陣列式導線架的複數個引腳以及一支持載體之間；藉由固化該半固化的封膠體以形成一預成型導線架；連接具有複數個凸塊的至少一晶片於該等引腳上，各晶片與部分的該引腳藉由複數個凸塊電性連接；形成一凹槽於各引腳上，該凹槽用以容納與限制該凸塊的溢流；藉由該封膠體覆蓋該晶片以及該導線架陣列；以及分離該被覆蓋的晶片以及該導線架陣列以形成一封裝結構，其中該封裝結構包含被覆蓋的該晶片的其中之一以及一部份的被覆蓋的導線架陣列。
在一實施例中，該預成型導線架封裝為一四方扁平無引腳封裝(Quad Flat Non-leaded，QFN)。在另一實施例中，該半固化的封膠體可以不高於該引腳131的上表面。在又一實施例中，各引腳具有一內引腳以及一外引腳，而該內引腳的下表面高於該外引腳的下表面。在又一實施例中，該凸塊可藉由一熱超音波製程直接連接至該導線架的一引腳上。
為能進一步了解本發明的上述與其他的優點可透過以下的實施方式與所附的實施例圖綜觀之。
以下所述的詳細內容主要是用來舉例說明本發明中所提的例示裝置或方法，所述內容不應用來限定本發明，而且對於任何與本發明概念均等的功能與元件皆不脫離本發明的精神。
除非有特別定義，本說明書中所用的技術與科學用語應與本領域技藝人士所通用的相同，任何與本說明所述相關或均等的方法、元件或材料均在本發明保護涵蓋範圍，以下說明接僅為例示說明。
所有用來描述本發明所提及並含括作為參考的公開物，如所述的設計、方法主要是用來揭示並提供對照，並作為與本發明相關的連接，但不代表本發明內容未在其先完成。
如上所述，覆晶式封裝變成一種普遍的方法用於電性連接積體電路晶片至一基板。然而，傳統的覆晶式封裝中，該凸塊或熱固性導電膠會因為尚未固化而擴散溢流到該引腳的下表面(見圖1A及圖1B)，這種情況會造成封裝結構的缺陷。本發明提供一種改良的導線架結構用以容納與限制該溢流材料以避免封裝缺陷，該結構進一步可以增進封裝效率及可靠度。甚至於，該導線架結構可以是一預成型(pre-molded)導線架。
根據圖2A至2C的實施例，一覆晶結構20包含一晶片201，導線架陣列208的複數個引腳203，位於各引腳203上表面207的一半固化熱固性導電膠202，置放於該晶片201主動面上的複數個凸塊205以及一凹槽206。當該晶片201被下壓以與該引腳203連接，該凸塊205植入至該熱固性導電膠202中，因為該熱固性導電膠202的狀態為半固化，接受壓力會造成溢流現象的發生。不同於習知的覆晶結構(如圖1A及1B所示)，該溢流的熱固性導電膠202可由本發明的一凹槽206容納。就算該半固化的熱固性導電膠202發生溢流狀況，該凹槽206將會限制溢流的材料，避免擴散至該引腳203的其它部分。本實施例中，該熱固性導電膠202被置放於距離該引腳203邊緣204的一預定距離處，以避免擴散至該引腳203的邊緣204以及兩個側壁209。本發明中該熱固性導電膠202的Tg (玻璃轉換溫度)介於攝氏零下40度至175度之間，且該半固化的導電膠202可經由充分固化以緊密接合該凸塊205以及導線架陣列上的該晶片201。一封膠體(未顯示)可用於覆蓋該導線架陣列以及該晶片，細節如後實施例所述。
圖2C顯示本發明一覆晶結構20的俯視圖。其中晶片201上的複數個凸塊20植入位於該導線架陣列引腳203上的熱固性導電膠202，而半固化的該熱固性導電膠202接受壓力會造成溢流現象的發生，並由本發明的一凹槽206容納。多種導電凸塊材料可被運用於連接覆晶以及導線架陣列引腳203，例如金凸塊、銅凸塊、結線金凸塊、結線銅凸塊，或 金/銅合金凸塊。
如圖3A所示的另一實施例，不同於將該導電膠302設置於「靠近」該凹槽，該導電膠302實際上設置於該凹槽306內。換句話說，如圖3A1所示，該導電膠302被該凹槽306圍繞，而該凹槽306用於容納大部分或全部的溢流的該導電膠302。當凸塊植入位於該熱固性導電膠302中，該熱固性導電膠302會如圖2B中所示的發生溢流現象，然而，本實施例中溢流的熱固性導電膠302並不會擴散至該引腳303的其它部分，因此不會造成封裝結構的缺陷。另一個相似的實施例如圖3B及3B1所示，一凹槽306'的深度較該凹槽306深以避免該導電膠302的溢流。另一個相似的實施例如圖3C及3C1所示，該結構存在一第二凹槽3061以避免該導電膠302的溢流。以上實施例所述之結構並不限於容納及限制溢流的導電膠，任何會在該引腳上擴散的材料(例如凸塊之溢流，見圖1A及1B)都包含在本發明的範圍之內。相同地，該半固化的導電膠302可經由充分固化以緊密接合該凸塊。一封膠體(未顯示)可用於覆蓋該導線架陣列以及該晶片。
因為尺寸小、經濟、高良率、以及質輕，導線架封裝結構在半導體封裝產業中日趨重要。四方扁平無引腳封裝(Quad Flat Non-Leaded Package，QFN)也因為快速的訊號傳遞以及較佳的散熱功效而被重視。一實施例中，如上所述的導線架結構也可以應用在QFN封裝，以及一預成型QFN封裝上。如圖4A所示，一封膠體17藉由浸漬(dipping )、網版印刷(screen-printing)、塗佈(painting)、旋塗(spin-coating)、或噴霧(spraying)等方式附著在一膠帶41的表面上。該封膠體17可由具有兩階段反應的熱固性材料，例如但不限於聚亞醯胺(polyimide)、聚喹啉(polyquinolin)、苯環丁烯(benzocyclobutene)，或其等同物。本發明所用的熱固性材料為半固化，亦即半液態或膠態，因此可以輕易塗佈於該膠帶41表面上。同時，該具有兩階段反應的熱固性材料為非導體。
如圖4B所示，一導線架陣列13可包含一支持載體31以及置放於該支持載體31上表面的複數個引腳131。各引腳131具有一內引腳131a以及一外引腳131b，而該內引腳131a的下表面高於該外引腳131b的下表面。一般而言，該內引腳131a用於後續與積體電路元件的電連接，而該外引腳131b用於後續與外部電路的電連接。
圖4C顯示本發明中一層疊步驟(lamination process)以連接圖4A及4B中的結構，其中該引腳131完全被附著於該膠帶41下表面的封膠體17包覆。更具體地說，該膠帶41置放於該引腳131的上表面，而該半固化的封膠體17塗佈於該導線架13中，包含填滿該支持載體31上表面以及該內引腳131a下表面之間的空間。該膠帶41可於圖4D中所示被移除，經過固化該封膠體後形成一預成型導線架。如圖4E所示，在完全固化之後，該半固化的封膠體17可以不高於該引腳131的上表面。
如圖4F所示，該預成型導線架可以包含位於該引腳上 的一凹槽136，用以容納與限制該半固化導電膠的溢流。如上所述，該凹槽136可具有不同的型態(見圖2A至圖2B、圖3A至圖3C)，以確保不會有材料溢流出該引腳，造成封裝上的缺陷。該凹槽136可利用顯影蝕刻製程製作形成。
如圖5A所示，一晶片元件115可包含一基板30，複數個襯墊111，一主動表面100以及一絕緣層113。一實施例中，該基板30為一矽基板而該絕緣層113為一氮化矽層(Si3 N4 )。氮化矽通常用以作為矽基材料的絕緣層。如圖5B所示，複數個凸塊15形成於襯墊111上，該凸塊15可由兩種不同的材料組成151以及153。承上所述，多種導電材料可用來製作凸塊，例如金凸塊、銅凸塊、結線金凸塊、結線銅凸塊，或金/銅合金凸塊。更甚，如圖5C所示，可進一步藉由一切割程序形成複數個分離的晶片元件11。
本發明一實施例如圖6A所示，一覆晶結構60可包含一分離的晶片11(見圖5C)置放於該預成型封裝結構上(見圖4F)。更明確地說，該晶片元件11經翻轉使得該主動面100朝下後，該凸塊15置放於該內引腳131a的上表面並電連接該晶片元件11與該預成型封裝結構。該凸塊15可由兩種不同的材料組成151以及153，且該凸塊15可藉由一熱超音波製程與該內引腳131a連接。該凸塊15也可以藉由前述的熱固化導電膠與該內引腳131a連接。
如圖6A所示，在該內引腳131a上的該凹槽136用以容納與限制該半固化導電膠的溢流，因此溢流的凸塊材料不會如圖1A及圖1B般擴散到該引腳的其它部分。該凹槽136可 具有不同的型態(見圖2A至圖2B、圖3A至圖3C)，以確保不會有材料溢流出該引腳，造成封裝上的缺陷，而且該不同的凹槽型態適用於本發明所有實施例中。
如圖6B所示，一第二封膠體17'可後續施加覆蓋於該晶片元件11、該導線架13(包含內引腳131a以及部分的外引腳131b)、以及該凸塊15上，藉以完成一預成型QFN封裝製程。一實施例中，該封膠體的表面19可不高於該導線架13的上表面。該封膠體17以及該第二封膠體17'可為相同材料。該封膠體17可藉由注塑成型(injection molding)、包覆成型(over molding)、或底部充膠成型(underfill potting)覆蓋該導線架13以及晶片11。
圖7顯示本發明一導線架陣列13的俯視圖，該導線架陣列13包含複數個引腳131(包含內引腳131a以及外引腳131b)。本發明之凹槽可形成於該內引腳131a上以容納與限制該半固化導電膠的溢流。該凹槽136可利用顯影蝕刻製程製作完成。
本發明的另一目的在於揭露一種預成型導線架封裝的製造方法800，該方法包含形成一半固化的封膠體於一導線架陣列的複數個引腳以及一支持載體之間810；藉由固化該半固化的封膠體以形成一預成型導線架820；連接具有複數個凸塊的至少一晶片於該等引腳上，各晶片與部分的該引腳藉由複數個凸塊電連接830；形成一凹槽於各引腳上，該凹槽用以容納與限制該凸塊的溢流840；藉由該封膠體覆蓋該晶片以及該導線架陣列850；以及分割該被覆蓋的晶片以 及該導線架陣列以形成一封裝結構，其中該封裝結構包含被覆蓋的該晶片的其中之一以及一部份的被覆蓋的導線架陣列860。
一實施例中，該形成一半固化的封膠體於一導線架陣列的複數個引腳以及一支持載體之間的步驟810包含塗覆一半固化封膠體於一膠帶的背面，藉由一層疊步驟置放該膠帶於該引腳的上表面，並於後續步驟中移除該膠帶。如圖4C以及4D所示，該膠帶41塗覆了一封膠體17，並置放於該導線架陣列13引腳的上表面，且該膠帶於一層疊製程後被移除。一封膠體可藉由浸漬(dipping)、網版印刷(screen-printing)、塗佈(painting)、旋塗(spin-coating)、或噴霧(spraying)等方式附著上一膠帶41的下表面。於另一實施例中，如圖3A及3B所示，於各引腳上該形成凹槽的步驟840包含形成一凹槽圍繞該凸塊。於另一實施例中，該預成型導線架封裝為一四方扁平無引腳封裝(Quad Flat Non-Leaded Package)。
本發明之技術內容及技術特點已揭示如上，然而熟悉本項技術之人士仍可能基於本發明之教示及揭示而作種種不背離本發明精神之替換及修飾。因此，本發明之保護範圍應不限於實施例所揭示者，而應包括各種不背離本發明之替換及修飾，並為以下之申請專利範圍所涵蓋。
10‧‧‧覆晶結構
100‧‧‧主動面
101‧‧‧晶片
103‧‧‧引腳
105‧‧‧凸塊
107‧‧‧溢流的凸塊
11‧‧‧晶片
111‧‧‧接墊
113‧‧‧絕緣層
115‧‧‧晶片元件
13‧‧‧導線架
131‧‧‧引腳
131a‧‧‧內引腳
131b‧‧‧外引腳
136‧‧‧凹槽
15‧‧‧凸塊
151‧‧‧材料一
153‧‧‧材料二
17‧‧‧封膠體
17'‧‧‧第二封膠體
19‧‧‧封膠體表面
20‧‧‧覆晶結構
201‧‧‧晶片
202‧‧‧熱固性導電膠
203‧‧‧引腳
204‧‧‧引腳邊緣
205‧‧‧凸塊
206‧‧‧凹槽
207‧‧‧引腳上表面
208‧‧‧導線架陣列
30‧‧‧基板
302‧‧‧熱固性導電膠
303‧‧‧引腳
306‧‧‧凹槽
306'‧‧‧凹槽
3061‧‧‧第二凹槽
31‧‧‧支持載體
41‧‧‧膠帶
60‧‧‧覆晶結構
800‧‧‧製造方法
810‧‧‧步驟
820‧‧‧步驟
830‧‧‧步驟
840‧‧‧步驟
850‧‧‧步驟
860‧‧‧步驟
圖1A及1B顯示一習知覆晶結構，該結構會因為材料溢 流問題而造成封裝缺陷；圖2A及2B根據本發明一實施例顯示當具有複數個凸塊的晶片植入引腳上半固化的導電膠中，以及引腳上的凹槽用以容納與限制該半固化導電膠的溢流；圖2C顯示圖2A及2B中實施例的俯視圖；圖3A至3C顯示本發明多種凹槽結構的剖面及俯視圖；圖4A至4F顯示本發明中一層疊步驟以形成一預成型(pre-molded)導線架結構；圖5A至5C顯示一晶片元件的剖面圖，該晶片元件可用於本發明的覆晶製程；圖6A顯示圖5C中的晶片置放於圖4F中預成型導線架結構；圖6B顯示圖6A的結構覆蓋封膠體形成的一預成型四方扁平無引腳封裝(Quad Flat Non-Leaded Package，QFN)結構；圖7顯示本發明一導線架陣列的俯視圖；以及圖8顯示一種預成型導線架封裝的製造方法。
11‧‧‧晶片
111‧‧‧接墊
13‧‧‧導線架
131‧‧‧引腳
131a‧‧‧內引腳
131b‧‧‧外引腳
15‧‧‧凸塊
151‧‧‧材料一
153‧‧‧材料二
17‧‧‧封膠體
17'‧‧‧第二封膠體
19‧‧‧封膠體表面
31‧‧‧支持載體

Claims (20)

  1. 一種覆晶半導體封裝結構的製造方法，該方法包含：形成複數個導電膠於一導線架陣列的引腳上，其中一凹槽設置於該引腳上與該各導電膠分離一預定距離處；半固化該導電膠，使得該導電膠處於半固化或黏稠的狀態；提供具有複數個凸塊的至少一晶片；電連接該晶片與該導線架陣列的引腳，藉由植入該凸塊至該半固化的導電膠，其中該凹槽用以容納與限制該半固化導電膠的溢流；固化該半固化導電膠以緊密接合該晶片；以及形成一封膠體覆蓋該導線架以及該晶片。
  2. 如申請專利範圍第1項所述之製造方法，其中提供具有複數個凸塊的至少一晶片的步驟包含形成金凸塊、銅凸塊、結線金凸塊、結線銅凸塊或金/銅合金凸塊。
  3. 如申請專利範圍第1項所述之製造方法，進一步包含固化該封膠體的步驟。
  4. 如申請專利範圍第3項所述之製造方法，進一步包含分割該導線架陣列的步驟。
  5. 如申請專利範圍第1項所述之製造方法，其中該導線架陣列是一預成型(pre-molded)導線架陣列。
  6. 如申請專利範圍第1項所述之製造方法，其中該形成一封膠體覆蓋該導線架以及該晶片的步驟是藉由注塑成型(injection molding)、包覆成型(over molding)、或底部充膠成型(underfill potting)的方式形成。
  7. 如申請專利範圍第1項所述之製造方法，其中形成複數個導電膠於一導線架陣列的引腳上，其中一凹槽設置於該引腳上與該各導電膠分離一預定距離處的步驟包含形成圍繞該導電膠的一凹槽。
  8. 一種覆晶半導體封裝結構，包含：一導線架陣列，具有複數個內引腳以及外引腳；一凹槽，設置於該內引腳上；一半導體晶片，具有複數個凸塊用以電連接該半導體晶片以及該內引腳；複數個半固化的導電膠，用以接合該半導體晶片於該內引腳之上；以及一封膠體，用以密封並覆蓋該半導體晶片以及該導線架；其中該凹槽設置於該內引腳上與該些半固化的導電膠分離一預定距離處，且當該晶片上之凸塊植入至該導電膠，該凹槽經配置以容納與限制該半固化導電膠的溢流，且該半固化的導電膠經由充分固化以緊密接合導線架陣列上的該晶片。
  9. 如申請專利範圍第8項所述之覆晶半導體封裝結構，其中該凸塊包含金凸塊、銅凸塊、結線金凸塊、結線銅凸塊，或金/銅合金凸塊。
  10. 如申請專利範圍第8項所述之覆晶半導體封裝結構，其中該封膠體進一步被固化且該導線架陣列進一步被分割。
  11. 如申請專利範圍第8項所述之覆晶半導體封裝結構，其中該導線架陣列是一預成型(pre-molded)導線架陣列。
  12. 如申請專利範圍第11項所述之覆晶半導體封裝結構，其中該預成型導線架陣列包含一支持載體、置放於該支持載體上的複數個引腳，其中引腳該包含內引腳以及外引腳、以及半固化的第二封膠體，其中該第二封膠體塗覆於一膠帶上，該膠帶置放於該內引腳的頂部表面用以塗佈與覆蓋該導線架。
  13. 如申請專利範圍第12項所述之覆晶半導體封裝結構，其中該膠帶於後續步驟中被移除且該第二封膠體被固化。
  14. 如申請專利範圍第8項所述之覆晶半導體封裝結構，其中該凹槽圍繞該導電膠以避免該導電膠溢流。
  15. 一種預成型(pre-molded)導線架封裝的製造方法，該預成型導線架封裝為一四方扁平無引腳封裝(Quad Flat Non-Leaded Package，QFN)，該方法包含：形成一半固化的封膠體於一導線架陣列的複數個引腳以及一支持載體之間；藉由固化該半固化的封膠體以形成一預成型導線架；連接具有複數個凸塊的至少一晶片於該等引腳上，各晶片與部分的該引腳藉由複數個凸塊電連接；形成一凹槽於各引腳上，該凹槽用以容納與限制該凸塊的溢流；藉由該封膠體覆蓋該晶片以及該導線架陣列；以及分割該被覆蓋的該晶片以及該導線架陣列以形成一封裝結構，其中該封裝結構包含一被覆蓋的該晶片以及一部份的被覆蓋的導線架陣列。
  16. 如申請專利範圍第15項所述之製造方法，其中形成一半固 化的封膠體的步驟包含塗覆一半固化封膠體於一膠帶的背面，藉由一層疊步驟置放該膠帶於該引腳的上表面，並於後續步驟中移除該膠帶。
  17. 如申請專利範圍第16項所述之製造方法，其中該塗覆一半固化封膠體於一膠帶的背面的步驟包含一浸漬(dipping)、網版印刷(screen-printing)、塗佈(painting)、旋塗(spin-coating)、或噴霧(spraying)製程。
  18. 如申請專利範圍第15項所述之製造方法，其中形成一凹槽的步驟包含形成一凹槽圍繞該凸塊。
  19. 如申請專利範圍第15項所述之製造方法，其中藉由該封膠體覆蓋該晶片以及該導線架陣列的步驟是藉由注塑成型(injection molding)、包覆成型(over molding)、或底部充膠成型(underfill potting)的方式形成。
  20. 如申請專利範圍第15項所述之製造方法，其中連接具有複數個凸塊的至少一晶片於該等引腳上包含藉由一熱超音波(thermo-ultrasonic)製程直接連接該凸塊與該導線架陣列的引腳。
TW101132467A 2011-09-14 2012-09-06 半導體封裝結構的製造方法 TWI495021B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/232,946 US8426255B2 (en) 2011-09-14 2011-09-14 Chip package structure and method for manufacturing the same

Publications (2)

Publication Number Publication Date
TW201312669A TW201312669A (zh) 2013-03-16
TWI495021B true TWI495021B (zh) 2015-08-01

Family

ID=47830197

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101132467A TWI495021B (zh) 2011-09-14 2012-09-06 半導體封裝結構的製造方法

Country Status (3)

Country Link
US (1) US8426255B2 (zh)
CN (1) CN103000538A (zh)
TW (1) TWI495021B (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160057855A1 (en) * 2013-04-15 2016-02-25 Heptagon Micro Optics Pte. Ltd. Accurate Positioning and Alignment of a Component During Processes Such as Reflow Soldering
CN103745967A (zh) * 2013-12-05 2014-04-23 南通富士通微电子股份有限公司 引线框架和封装结构
CN103824785B (zh) * 2013-12-05 2017-01-11 南通富士通微电子股份有限公司 封装结构的形成方法
CN103730378B (zh) * 2013-12-05 2016-08-31 南通富士通微电子股份有限公司 封装结构的形成方法
CN103730440B (zh) * 2013-12-05 2017-03-01 通富微电子股份有限公司 封装结构
US10032699B1 (en) * 2014-04-28 2018-07-24 Amkor Technology, Inc. Flip chip self-alignment features for substrate and leadframe applications
CN103972113B (zh) * 2014-05-22 2016-10-26 南通富士通微电子股份有限公司 封装方法
CN104064533A (zh) * 2014-07-03 2014-09-24 江苏东光微电子股份有限公司 一种双面半导体器件的qfn封装结构及方法
US9502337B2 (en) * 2014-10-31 2016-11-22 Nantong Fujitsu Microelectronics Co., Ltd. Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof
TWI562255B (en) * 2015-05-04 2016-12-11 Chipmos Technologies Inc Chip package structure and manufacturing method thereof
TWI657554B (zh) 2015-09-30 2019-04-21 台達電子工業股份有限公司 封裝結構
US9646853B1 (en) * 2015-10-15 2017-05-09 Freescale Semiconductor, Inc. IC device having patterned, non-conductive substrate
TWI574389B (zh) * 2015-11-05 2017-03-11 凌陽科技股份有限公司 積體電路
CN105551987A (zh) * 2015-12-09 2016-05-04 南通富士通微电子股份有限公司 一种覆晶薄膜（cof）封装方法
CN105551986A (zh) * 2015-12-09 2016-05-04 南通富士通微电子股份有限公司 一种覆晶薄膜(cof)封装方法
US9786582B2 (en) * 2016-01-29 2017-10-10 Texas Instruments Incorporated Planar leadframe substrate having a downset below within a die area
CN106252247B (zh) * 2016-09-05 2019-07-05 江苏纳沛斯半导体有限公司 半导体结构及其形成方法
CN106898670A (zh) * 2017-02-28 2017-06-27 东汉新能源汽车技术有限公司 太阳能芯片封装方法、太阳能芯片总成及太阳能汽车
CN107815807A (zh) * 2017-12-20 2018-03-20 广州市富元服装辅料有限公司 一种智能纱线封装机
CN111370315A (zh) * 2018-12-25 2020-07-03 海太半导体（无锡）有限公司 一种用于热固性导电胶焊接倒装型芯片与基板的方法
JP2020136520A (ja) * 2019-02-20 2020-08-31 トヨタ自動車株式会社 半導体装置
JP7322467B2 (ja) 2019-03-29 2023-08-08 株式会社デンソー 半導体装置
JP2021027211A (ja) * 2019-08-07 2021-02-22 ローム株式会社 電子装置
US20210066239A1 (en) * 2019-09-03 2021-03-04 Texas Instruments Incorporated Packaged semiconductor devices with uniform solder joints
TWI713168B (zh) * 2020-03-09 2020-12-11 南茂科技股份有限公司 晶片封裝結構及其製造方法
CN112551480A (zh) * 2020-11-17 2021-03-26 瑞声新能源发展(常州)有限公司科教城分公司 Mems传感器的制作方法
TWI847300B (zh) * 2022-10-12 2024-07-01 強茂股份有限公司 半導體裝置及其預成型適配器和製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5808354A (en) * 1994-11-21 1998-09-15 Samsung Electronics Co., Ltd. Lead frame for a semiconductor device comprising inner leads having a locking means for preventing the movement of molding compound against the inner lead surface
US20030045015A1 (en) * 2001-07-23 2003-03-06 Slater David B. Flip-chip bonding of light emitting devices and light emitting devices suitable for flip-chip bonding
US20060061974A1 (en) * 2000-12-21 2006-03-23 Tasao Soga Solder foil semiconductor device and electronic device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3022393B2 (ja) * 1997-04-21 2000-03-21 日本電気株式会社 半導体装置およびリードフレームならびに半導体装置の製造方法
US6423623B1 (en) * 1998-06-09 2002-07-23 Fairchild Semiconductor Corporation Low Resistance package for semiconductor devices
KR20000057810A (ko) * 1999-01-28 2000-09-25 가나이 쓰토무 반도체 장치
JP4173751B2 (ja) * 2003-02-28 2008-10-29 株式会社ルネサステクノロジ 半導体装置
CN1964086A (zh) * 2005-11-08 2007-05-16 璨圆光电股份有限公司 表面黏着型发光二极管封装结构
CN101540300A (zh) * 2008-03-20 2009-09-23 南茂科技股份有限公司 晶片封装体
CN101625986B (zh) * 2008-07-08 2012-02-22 南茂科技股份有限公司 芯片封装结构制程

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5808354A (en) * 1994-11-21 1998-09-15 Samsung Electronics Co., Ltd. Lead frame for a semiconductor device comprising inner leads having a locking means for preventing the movement of molding compound against the inner lead surface
US20060061974A1 (en) * 2000-12-21 2006-03-23 Tasao Soga Solder foil semiconductor device and electronic device
US20030045015A1 (en) * 2001-07-23 2003-03-06 Slater David B. Flip-chip bonding of light emitting devices and light emitting devices suitable for flip-chip bonding

Also Published As

Publication number Publication date
US20130065361A1 (en) 2013-03-14
US8426255B2 (en) 2013-04-23
TW201312669A (zh) 2013-03-16
CN103000538A (zh) 2013-03-27

Similar Documents

Publication Publication Date Title
TWI495021B (zh) 半導體封裝結構的製造方法
TWI550741B (zh) 四方扁平無接腳封裝及其製造方法
TWI482261B (zh) 三維系統級封裝堆疊式封裝結構
US6166434A (en) Die clip assembly for semiconductor package
US11031356B2 (en) Semiconductor package structure for improving die warpage and manufacturing method thereof
US8377745B2 (en) Method of forming a semiconductor device
TWI455269B (zh) 晶片封裝結構及其製作方法
US9111878B2 (en) Method for forming a semiconductor device assembly having a heat spreader
TWI414028B (zh) 注射封膠系統及其方法
TW200836307A (en) Thermally enhanced quad flat no leads (QFN) IC package and method
KR101352233B1 (ko) 반도체 패키지 및 그 제조방법
TWI582867B (zh) 晶片封裝製程
US20060214308A1 (en) Flip-chip semiconductor package and method for fabricating the same
US9748157B1 (en) Integrated circuit packaging system with joint assembly and method of manufacture thereof
JP2010263108A (ja) 半導体装置及びその製造方法
JP2004282042A (ja) 半導体デバイスのアセンブリ法
US10854576B2 (en) Semiconductor device and manufacturing method thereof
CN108281398B (zh) 半导体封装件及其制造方法
JP2005142452A (ja) 半導体装置及びその製造方法
TWI750082B (zh) 半導體覆晶封裝結構及方法
KR20080044518A (ko) 반도체 패키지 및 이의 제조 방법
US20080251910A1 (en) Fabricating method of semiconductor package and heat-dissipating structure applicable thereto
US20240339336A1 (en) Substrate having underfill dam and semiconductor package including the same, and method for manufacturing the semiconductor package
JPH06209071A (ja) 樹脂封止半導体装置およびその製造方法
KR100455698B1 (ko) 칩 싸이즈 패키지 및 그 제조 방법