JP2020136520A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2020136520A JP2020136520A JP2019028856A JP2019028856A JP2020136520A JP 2020136520 A JP2020136520 A JP 2020136520A JP 2019028856 A JP2019028856 A JP 2019028856A JP 2019028856 A JP2019028856 A JP 2019028856A JP 2020136520 A JP2020136520 A JP 2020136520A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 140
- 125000006850 spacer group Chemical group 0.000 claims abstract description 85
- 229910000679 solder Inorganic materials 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 31
- 230000007423 decrease Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 14
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 239000004020 conductor Substances 0.000 description 36
- 239000000463 material Substances 0.000 description 28
- 238000007789 sealing Methods 0.000 description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 238000005476 soldering Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000005304 joining Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 239000000565 sealant Substances 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
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- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
12:信号端子スペーサ
12a:第1端面
12b:第2端面
12c:底面
14、15、114:信号端子
14c、114c:フラット面
16、17、18、117:電力端子
20、40、:半導体素子
20b、20c、40b、40c:主電極
20d、40d:信号パッド
22、42、122、142:上側放熱板
24、44、124、144:下側放熱板
30、130:封止体
Claims (9)
- 信号パッドを有する半導体素子と、
前記信号パッドに対向する平坦なフラット面を有し、前記フラット面がスペーサを挟んで前記信号パッドに接合された信号端子と、
を備え、
前記フラット面は、前記フラット面に平行な少なくとも一つの方向において、前記信号パッドよりも大きい、
半導体装置。 - 前記信号パッドは、前記少なくとも一つの方向において、前記スペーサよりも大きい、請求項1に記載の半導体装置。
- 前記信号端子のうち、少なくとも前記フラット面を含む端部は、第1方向に沿って延びており、
前記少なくとも一つの方向は、前記第1方向を含む、請求項1又は2に記載の半導体装置。 - 前記少なくとも一つの方向は、前記第1方向に垂直な第2方向をさらに含む、請求項3に記載の半導体装置。
- 前記スペーサは、前記フラット面に対向する一端面と、前記信号パッドに対向する他端面とを有する柱体形状を有する、請求項1から4のいずれか一項に記載の半導体装置。
- 前記スペーサは、球体形状を有する、請求項1から4のいずれか一項に記載の半導体装置。
- 前記スペーサは、前記信号パッドに対向する底面を有するとともに、前記フラット面に向かうにつれて断面積が連続的又は段階的に減少する形状を有する、請求項1から4のいずれか一項に記載の半導体装置。
- 前記フラット面は、はんだを介して前記信号パッドに接合されており、
前記スペーサは、前記はんだの内部に位置している、請求項1から7のいずれか一項に記載の半導体装置。 - 前記信号端子の少なくとも一部は、絶縁基板上に設けられている、請求項1から8のいずれか一項に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019028856A JP2020136520A (ja) | 2019-02-20 | 2019-02-20 | 半導体装置 |
US16/745,779 US20200266130A1 (en) | 2019-02-20 | 2020-01-17 | Semiconductor device |
CN202010100770.9A CN111599781A (zh) | 2019-02-20 | 2020-02-19 | 半导体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019028856A JP2020136520A (ja) | 2019-02-20 | 2019-02-20 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2020136520A true JP2020136520A (ja) | 2020-08-31 |
Family
ID=72042267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019028856A Pending JP2020136520A (ja) | 2019-02-20 | 2019-02-20 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20200266130A1 (ja) |
JP (1) | JP2020136520A (ja) |
CN (1) | CN111599781A (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010002821A1 (en) * | 1999-12-06 | 2001-06-07 | Nec Corporation | Apparatus and method for controlling radiation of electric waves |
US20020084536A1 (en) * | 2000-12-28 | 2002-07-04 | Sundahl Robert C. | Interconnected circuit board assembly and method of manufacture therefor |
US20130043573A1 (en) * | 2011-08-15 | 2013-02-21 | Advanced Analogic Technologies (Hong Kong) Limited | Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores |
US20130065361A1 (en) * | 2011-09-14 | 2013-03-14 | Chipmos Technologies Inc. | Chip package structure and method for manufacturing the same |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5143211B2 (ja) * | 2009-12-28 | 2013-02-13 | パナソニック株式会社 | 半導体モジュール |
US10032699B1 (en) * | 2014-04-28 | 2018-07-24 | Amkor Technology, Inc. | Flip chip self-alignment features for substrate and leadframe applications |
JP6269573B2 (ja) * | 2015-05-18 | 2018-01-31 | 株式会社デンソー | 半導体装置 |
US10002821B1 (en) * | 2017-09-29 | 2018-06-19 | Infineon Technologies Ag | Semiconductor chip package comprising semiconductor chip and leadframe disposed between two substrates |
-
2019
- 2019-02-20 JP JP2019028856A patent/JP2020136520A/ja active Pending
-
2020
- 2020-01-17 US US16/745,779 patent/US20200266130A1/en not_active Abandoned
- 2020-02-19 CN CN202010100770.9A patent/CN111599781A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010002821A1 (en) * | 1999-12-06 | 2001-06-07 | Nec Corporation | Apparatus and method for controlling radiation of electric waves |
US20020084536A1 (en) * | 2000-12-28 | 2002-07-04 | Sundahl Robert C. | Interconnected circuit board assembly and method of manufacture therefor |
US20130043573A1 (en) * | 2011-08-15 | 2013-02-21 | Advanced Analogic Technologies (Hong Kong) Limited | Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores |
US20130065361A1 (en) * | 2011-09-14 | 2013-03-14 | Chipmos Technologies Inc. | Chip package structure and method for manufacturing the same |
Also Published As
Publication number | Publication date |
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US20200266130A1 (en) | 2020-08-20 |
CN111599781A (zh) | 2020-08-28 |
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