JP2019153751A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2019153751A JP2019153751A JP2018039914A JP2018039914A JP2019153751A JP 2019153751 A JP2019153751 A JP 2019153751A JP 2018039914 A JP2018039914 A JP 2018039914A JP 2018039914 A JP2018039914 A JP 2018039914A JP 2019153751 A JP2019153751 A JP 2019153751A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- joint portion
- semiconductor element
- radiator plate
- joint area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
Landscapes
- Die Bonding (AREA)
Abstract
Description
12:封止体
14:P端子
15:N端子
16:O端子
18、19:信号端子
20、40:半導体素子
22:第1上側放熱板
22c:第1継手部
22e:第1継手部のはんだ吸収溝
22g:第1上側放熱板の重心
23、25、27、43、45、47、50:はんだ(層)
24、44:導体スペーサ
26:第1下側放熱板
42:第2上側放熱板
42c:第2上側放熱板の継手部
42e:第2上側放熱板の継手部のはんだ吸収溝
46:第2下側放熱板
46c:第2継手部
E:第1継手部のはんだ吸収溝の内周縁
F:はんだの表面張力
S1:第1はんだ接合エリア
S2:第2はんだ接合エリア
X:第1積層体
θ:接触角
Claims (1)
- 第1部材と、
前記第1部材に、はんだ層を介して接合された第2部材と、
を備え、
前記第1部材の前記はんだ層に接触する範囲を第1はんだ接合エリアとし、前記第2部材の前記はんだ層に接触する範囲を第2はんだ接合エリアとしたときに、
前記第1部材には、前記第1はんだ接合エリアの周縁に沿って、はんだ吸収溝が設けられており、
前記第1はんだ接合エリアは、平面視において、前記第1部材の重心から離れて位置しており、
前記はんだ吸収溝の内周縁は、平面視において、前記第2はんだ接合エリアよりも外側に位置する、
半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018039914A JP2019153751A (ja) | 2018-03-06 | 2018-03-06 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018039914A JP2019153751A (ja) | 2018-03-06 | 2018-03-06 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2019153751A true JP2019153751A (ja) | 2019-09-12 |
Family
ID=67946986
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018039914A Pending JP2019153751A (ja) | 2018-03-06 | 2018-03-06 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2019153751A (ja) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012235081A (ja) * | 2011-04-19 | 2012-11-29 | Toyota Motor Corp | 半導体装置及びその製造方法 |
-
2018
- 2018-03-06 JP JP2018039914A patent/JP2019153751A/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012235081A (ja) * | 2011-04-19 | 2012-11-29 | Toyota Motor Corp | 半導体装置及びその製造方法 |
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