CN103000538A - 半导体封装结构的制造方法 - Google Patents

半导体封装结构的制造方法 Download PDF

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Publication number
CN103000538A
CN103000538A CN201210335695XA CN201210335695A CN103000538A CN 103000538 A CN103000538 A CN 103000538A CN 201210335695X A CN201210335695X A CN 201210335695XA CN 201210335695 A CN201210335695 A CN 201210335695A CN 103000538 A CN103000538 A CN 103000538A
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China
Prior art keywords
lead frame
pin
wafer
semi
conducting resinl
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CN201210335695XA
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沈更新
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Publication of CN103000538A publication Critical patent/CN103000538A/zh
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Abstract

本发明揭露一种半导体封装结构的制造方法，根据本发明一实施例，该方法包含形成复数个导电胶于一导线架阵列的引脚上，其中一凹槽设置于该引脚上与该各导电胶分离一预定距离处；部分固化该导电胶，使得该导电胶处于半固化及黏稠的状态；提供具有复数个凸块的至少一晶片；藉由植入该凸块至该半固化的导电胶以电连接该晶片与该导线架阵列的引脚，其中该凹槽用以容纳与限制该半固化导电胶的溢流；固化该半固化导电胶以紧密接合该晶片；以及形成一封胶体覆盖该导线架以及该晶片。该方法亦可用于预成型（pre-molded）导线架封装。

Description

半导体封装结构的制造方法
技术领域
本发明涉及一种半导体元件封装结构，特别是涉及一导线架结构用以控制半导体元件封装过程中的材料溢流。
背景技术
随着半导体科技的日新月异，电子产业经历了由体积厚到薄的快速变革，以及从不停歇的微小化制程改良。半导体封装是一门建立半导体元件之间连结以形成一电路的科学，也由于半导体与电子产业的不断进步而快速发展。
半导体封装通常包含一导线架用以电连接一个或多个半导体元件，例如集成电路晶粒。一般而言，与该导线架连接的晶粒通常藉由打线制程与该导线架的引脚电连接，然后一封胶体将覆盖并密封该导线架、该连接线、以及该集成电路晶粒，以完成封装制程。封装的主要目的在于确保半导体元件以及其连接结构有效且妥善地被保护。
近来覆晶式封装变成一种普遍的方法用于电连接集成电路晶片至一基板或导线架上。更明确地说，在制程中，锡凸块被置放在该晶片的上表面，而该晶片经翻转并使其上的导电接垫与该基板上的导电接垫相接。接续加热该覆晶与该基板并使锡凸块熔融于该基板的导电接垫之上，该覆晶与该基板接着冷却以凝固该锡凸块，以完成该电连接结构。传统上一旦该覆晶与该基板连结，一底部充胶材料，通常是一种液体黏接用树脂，设置于该晶片以及该基板中间。该底部充胶材料提供该晶片以及该基板间结构上的连结以及热稳定，并避免环境的干扰。
图1A显示习知的覆晶结构10剖面图，该结构包含有源面朝下的一晶片101，用以与一导线架（未显示）的引脚103电连接的复数个凸块105。当该晶片稍微被下压并加热以进一步与该引脚103连接，该凸块105有可能因为尚未凝固而变形。甚至于该凸块105会扩散溢流到（见图1B中的107）该引脚103的下表面，这种情况会造成封装结构的缺陷。此问题亦会在该覆晶的凸块植入该引脚103上的导电胶时发生，因为导电胶也会扩散溢流并造成封装结构的缺陷。因此，开发一种新型改良的导线架结构用以容纳与限制该溢流材料以避免封装缺陷确实有其必要。
发明内容
本发明的一个目的在于提供一覆晶半导体封装方法，该方法可以避免封装缺陷并进一步增进元件封装效率及可靠度。
本发明的另一目的在于提供一覆晶半导体封装方法，该方法可以藉由本发明的导线架引脚的一凹槽结构容纳与限制半固化材料的溢流。
本发明的另一目的在于提供一覆晶半导体封装方法，该方法可以用于制造一预成型（pre-molded）半导体封装结构。
本发明的另一目的在于提供一种半导体封装结构的制造方法，该方法包含形成复数个导电胶于一阵列式导线架的引脚上，其中一凹槽设置于该引脚上与该各导电胶具一预定距离；半固化该导电胶，使得该导电胶处于半固化及黏稠的状态；提供具有复数个凸块的至少一晶片；电连接该晶片与该导线架阵列的引脚，藉由植入该凸块至该半固化的导电胶，其中该凹槽用以容纳与限制该半固化导电胶的溢流；固化该半固化导电胶以紧密接合该晶片；以及形成一封胶体覆盖该导线架以及该晶片。
在一实施例中，其中提供具有复数个凸块的至少一晶片的步骤包含形成金凸块、铜凸块、结线金凸块、结线铜凸块，或金/铜合金凸块。在另一实施例中，该形成一封胶体覆盖该导线架以及该晶片的步骤是藉由注塑成型、包覆成型、或底部注胶的方式形成。在另一实施例中，该热固性导电胶的Tg(玻璃转换温度)介于摄氏-40度至175度之间。
另一方面，本发明有一种半导体封装结构，包含一阵列式的导线架，具有复数个内引脚以及外引脚；一凹槽，设置于该任一内引脚上；一半导体晶片，具有复数个凸块用以电性连接该半导体晶片以及该内引脚；复数个半固化的导电胶，用以接合该半导体晶片于该内引脚之上；以及一封胶体，用以密封并覆盖该半导体晶片以及该导线架；其中该热固性导电胶设置于引脚上与引脚边缘具一预定距离处，且该凹槽设置于该引脚上与该各导电胶具一预定距离处。当该晶片上的凸块嵌入该导电胶，该凹槽的配置可用以容纳与限制该半固化导电胶的溢流，且藉由该半固化的导电胶充分固化后紧密接合该阵列式导线架上的晶片。
在一实施例中，该凸块包含金凸块、铜凸块、结线金凸块、结线铜凸块，或金/铜合金凸块。在另一实施例中，该导线架是一预成型（pre-molded）导线架阵列。在另一实施例中，该凹槽可以利用显影或蚀刻制程形成。
另一方面，本发明有一种预成型（pre-molded）导线架封装的制造方法，该方法包含形成一半固化的封胶体于一阵列式导线架的复数个引脚以及一支持载体之间；藉由固化该半固化的封胶体以形成一预成型导线架；连接具有复数个凸块的至少一晶片于该等引脚上，各晶片与部分的该引脚藉由复数个凸块电性连接；形成一凹槽于各引脚上，该凹槽用以容纳与限制该凸块的溢流；藉由该封胶体覆盖该晶片以及该导线架阵列；以及分离该被覆盖的晶片以及该导线架阵列以形成一封装结构，其中该封装结构包含被覆盖的该晶片的其中之一以及一部份的被覆盖的导线架阵列。
在一实施例中，该预成型导线架封装为一四方扁平无引脚封装（QuadFlat Non-leaded，QFN）。在另一实施例中，该半固化的封胶体可以不高于该引脚的上表面。在又一实施例中，各引脚具有一内引脚以及一外引脚，而该内引脚的下表面高于该外引脚的下表面。在又一实施例中，该凸块可藉由一热超音波制程直接连接至该导线架的一引脚上。
为能进一步了解本发明的上述与其他的优点可透过以下的实施方式与所附的实施例图来综合观察。
附图说明
图1A及1B显示一习知覆晶结构，该结构会因为材料溢流问题而造成封装缺陷；
图2A及2B根据本发明一实施例显示当具有复数个凸块的晶片植入引脚上半固化的导电胶中，以及引脚上的凹槽用以容纳与限制该半固化导电胶的溢流；
图2C显示图2A及2B中实施例的俯视图；
图3A至3C显示本发明多种凹槽结构的剖面及俯视图；
图4A至4F显示本发明中一层迭步骤以形成一预成型（pre-molded）导线架结构；
图5A至5C显示一晶片元件的剖面图，该晶片元件可用于本发明的覆晶制程；
图6A显示图5C中的晶片置放于图4F中预成型导线架结构；
图6B显示图6A的结构覆盖封胶体形成的一预成型四方扁平无引脚封装（Quad Flat Non-Leaded Package，QFN）结构；
图7显示本发明一导线架阵列的俯视图；以及
图8显示一种预成型导线架封装的制造方法。
【主要元件符号说明】
10    覆晶结构
100   有源面
101   晶片
103   引脚
105   凸块
107   溢流的凸块
11    晶片
111   接垫
113   绝缘层
115   晶片元件
13    导线架
131   引脚
131a  内引脚
131b  外引脚
136   凹槽
15    凸块
151   材料一
153   材料二
17    封胶体
17'   第二封胶体
19    封胶体表面
20    覆晶结构
201   晶片
202   热固性导电胶
203   引脚
204   引脚边缘
205   凸块
206   凹槽
207   引脚上表面
208   导线架阵列
30    基板
302   热固性导电胶
303   引脚
306   凹槽
306'  凹槽
3061  第二凹槽
31    支持载体
41    胶带
60    覆晶结构
800   制造方法
810   步骤
820   步骤
830   步骤
840   步骤
850   步骤
860   步骤
具体实施方式
以下所述的详细内容主要是用来举例说明本发明中所提的例示装置或方法，所述内容不应用来限定本发明，而且对于任何与本发明概念均等的功能与元件皆不脱离本发明的精神。
除非有特别定义，本说明书中所用的技术与科学用语应与本领域技艺人士所通用的相同，任何与本说明所述相关或均等的方法、元件或材料均在本发明保护涵盖范围，以下说明接仅为例示说明。
所有用来描述本发明所提及并含括作为参考的公开物，如所述的设计、方法主要是用来揭示并提供对照，并作为与本发明相关的连接，但不代表本发明内容未在其先完成。
如上所述，覆晶式封装变成一种普遍的方法用于电性连接集成电路晶片至一基板。然而，传统的覆晶式封装中，该凸块或热固性导电胶会因为尚未固化而扩散溢流到该引脚的下表面（见图1A及图1B），这种情况会造成封装结构的缺陷。本发明提供一种改良的导线架结构用以容纳与限制该溢流材料以避免封装缺陷，该结构进一步可以增进封装效率及可靠度。甚至于，该导线架结构可以是一预成型(pre-molded)导线架。
根据图2A至2C的实施例，一覆晶结构20包含一晶片201，导线架阵列208的复数个引脚203，位于各引脚203上表面207的一半固化热固性导电胶202，置放于该晶片201主动面上的复数个凸块205以及一凹槽206。当该晶片201被下压以与该引脚203连接，该凸块205植入至该热固性导电胶202中，因为该热固性导电胶202的状态为半固化，接受压力会造成溢流现象的发生。不同于习知的覆晶结构（如图1A及1B所示），该溢流的热固性导电胶202可由本发明的一凹槽206容纳。就算该半固化的热固性导电胶202发生溢流状况，该凹槽206将会限制溢流的材料，避免扩散至该引脚203的其它部分。本实施例中，该热固性导电胶202被置放于距离该引脚203边缘204的一预定距离处，以避免扩散至该引脚203的边缘204以及两个侧壁209。本发明中该热固性导电胶202的Tg(玻璃转换温度)介于摄氏零下40度至175度之间，且该半固化的导电胶202可经由充分固化以紧密接合该凸块205以及导线架阵列上的该晶片201。一封胶体（未显示）可用于覆盖该导线架阵列以及该晶片，细节如后实施例所述。
图2C显示本发明一覆晶结构20的俯视图。其中晶片201上的复数个凸块20植入位于该导线架阵列引脚203上的热固性导电胶202，而半固化的该热固性导电胶202接受压力会造成溢流现象的发生，并由本发明的一凹槽206容纳。多种导电凸块材料可被运用于连接覆晶以及导线架阵列引脚203，例如金凸块、铜凸块、结线金凸块、结线铜凸块，或金/铜合金凸块。
如图3A所示的另一实施例，不同于将该导电胶302设置于“靠近”该凹槽，该导电胶302实际上设置于该凹槽306内。换句话说，如图3A1所示，该导电胶302被该凹槽306围绕，而该凹槽306用于容纳大部分或全部的溢流的该导电胶302。当凸块植入位于该热固性导电胶302中，该热固性导电胶302会如图2B中所示的发生溢流现象，然而，本实施例中溢流的热固性导电胶302并不会扩散至该引脚303的其它部分，因此不会造成封装结构的缺陷。另一个相似的实施例如图3B及3B1所示，一凹槽306'的深度较该凹槽306深以避免该导电胶302的溢流。另一个相似的实施例如图3C及3C1所示，该结构存在一第二凹槽3061以避免该导电胶302的溢流。以上实施例所述之结构并不限于容纳及限制溢流的导电胶，任何会在该引脚上扩散的材料（例如凸块之溢流，见图1A及1B）都包含在本发明的范围之内。相同地，该半固化的导电胶302可经由充分固化以紧密接合该凸块。一封胶体（未显示）可用于覆盖该导线架阵列以及该晶片。
因为尺寸小、经济、高良率、以及质轻，导线架封装结构在半导体封装产业中日趋重要。四方扁平无引脚封装（Quad Flat Non-Leaded Package，QFN）也因为快速的讯号传递以及较佳的散热功效而被重视。一实施例中，如上所述的导线架结构也可以应用在QFN封装，以及一预成型QFN封装上。如图4A所示，一封胶体17藉由浸渍（dipping）、网版印刷(screen-printing)、涂布(painting)、旋涂(spin-coating)、或喷雾(spraying)等方式附着在一胶带41的表面上。该封胶体17可由具有两阶段反应的热固性材料，例如但不限于聚亚酰胺（polyimide）、聚喹啉（polyquinolin）、苯环丁烯（benzocyclobutene），或其等同物。本发明所用的热固性材料为半固化，亦即半液态或胶态，因此可以轻易涂布于该胶带41表面上。同时，该具有两阶段反应的热固性材料为非导体。
如图4B所示，一导线架阵列13可包含一支持载体31以及置放于该支持载体31上表面的复数个引脚131。各引脚131具有一内引脚131a以及一外引脚131b，而该内引脚131a的下表面高于该外引脚131b的下表面。一般而言，该内引脚131a用于后续与积体电路元件的电连接，而该外引脚131b用于后续与外部电路的电连接。
图4C显示本发明中一层迭步骤（lamination process）以连接图4A及4B中的结构，其中该引脚131完全被附着于该胶带41下表面的封胶体17包覆。更具体地说，该胶带41置放于该引脚131的上表面，而该半固化的封胶体17涂布于该导线架13中，包含填满该支持载体31上表面以及该内引脚131a下表面之间的空间。该胶带41可于图4D中所示被移除，经过固化该封胶体后形成一预成型导线架。如图4E所示，在完全固化之后，该半固化的封胶体17可以不高于该引脚131的上表面。
如图4F所示，该预成型导线架可以包含位于该引脚上的一凹槽136，用以容纳与限制该半固化导电胶的溢流。如上所述，该凹槽136可具有不同的型态（见图2A至图2B、图3A至图3C），以确保不会有材料溢流出该引脚，造成封装上的缺陷。该凹槽136可利用显影蚀刻制程制作形成。
如图5A所示，一晶片元件115可包含一基板30，复数个衬垫111，一主动表面100以及一绝缘层113。一实施例中，该基板30为一硅基板而该绝缘层113为一氮化硅层（Si3N4）。氮化硅通常用以作为硅基材料的绝缘层。如图5B所示，复数个凸块15形成于衬垫111上，该凸块15可由两种不同的材料组成151以及153。承上所述，多种导电材料可用来制作凸块，例如金凸块、铜凸块、结线金凸块、结线铜凸块，或金/铜合金凸块。更甚，如图5C所示，可进一步藉由一切割程序形成复数个分离的晶片元件11。
本发明一实施例如图6A所示，一覆晶结构60可包含一分离的晶片11（见图5C）置放于该预成型封装结构上（见图4F）。更明确地说，该晶片元件11经翻转使得该有源面100朝下后，该凸块15置放于该内引脚131a的上表面并电连接该晶片元件11与该预成型封装结构。该凸块15可由两种不同的材料组成151以及153，且该凸块15可藉由一热超音波制程与该内引脚131a连接。该凸块15也可以藉由前述的热固化导电胶与该内引脚131a连接。
如图6A所示，在该内引脚131a上的该凹槽136用以容纳与限制该半固化导电胶的溢流，因此溢流的凸块材料不会如图1A及图1B般扩散到该引脚的其它部分。该凹槽136可具有不同的型态（见图2A至图2B、图3A至图3C），以确保不会有材料溢流出该引脚，造成封装上的缺陷，而且该不同的凹槽型态适用于本发明所有实施例中。
如图6B所示，一第二封胶体17'可后续施加覆盖于该晶片元件11、该导线架13（包含内引脚131a以及部分的外引脚131b）、以及该凸块15上，藉以完成一预成型QFN封装制程。一实施例中，该封胶体的表面19可不高于该导线架13的上表面。该封胶体17以及该第二封胶体17′可为相同材料。该封胶体17可藉由注塑成型（injection molding）、包覆成型(overmolding)、或底部充胶成型(underfill potting)覆盖该导线架13以及晶片11。
图7显示本发明一导线架阵列13的俯视图，该导线架阵列13包含复数个引脚131（包含内引脚131a以及外引脚131b）。本发明的凹槽可形成于该内引脚131a上以容纳与限制该半固化导电胶的溢流。该凹槽136可利用显影蚀刻制程制作完成。
本发明的另一目的在于揭露一种预成型导线架封装的制造方法800，该方法包含形成一半固化的封胶体于一导线架阵列的复数个引脚以及一支持载体之间810；藉由固化该半固化的封胶体以形成一预成型导线架820；连接具有复数个凸块的至少一晶片于该等引脚上，各晶片与部分的该引脚藉由复数个凸块电连接830；形成一凹槽于各引脚上，该凹槽用以容纳与限制该凸块的溢流840；藉由该封胶体覆盖该晶片以及该导线架阵列850；以及分割该被覆盖的晶片以及该导线架阵列以形成一封装结构，其中该封装结构包含被覆盖的该晶片的其中之一以及一部份的被覆盖的导线架阵列860。
一实施例中，该形成一半固化的封胶体于一导线架阵列的复数个引脚以及一支持载体之间的步骤810包含涂覆一半固化封胶体于一胶带的背面，藉由一层迭步骤置放该胶带于该引脚的上表面，并于后续步骤中移除该胶带。如图4C以及4D所示，该胶带41涂覆了一封胶体17，并置放于该导线架阵列13引脚的上表面，且该胶带于一层迭制程后被移除。一封胶体可藉由浸渍（dipping）、网版印刷(screen-printing)、涂布(painting)、旋涂(spin-coating)、或喷雾(spraying)等方式附着上一胶带41的下表面。于另一实施例中，如图3A及3B所示，于各引脚上该形成凹槽的步骤840包含形成一凹槽围绕该凸块。于另一实施例中，该预成型导线架封装为一四方扁平无引脚封装（Quad Flat Non-Leaded Package）。
本发明之技术内容及技术特点已揭示如上，然而熟悉本项技术之人士仍可能基于本发明之教示及揭示而作种种不背离本发明精神之替换及修饰。因此，本发明之保护范围应不限于实施例所揭示者，而应包括各种不背离本发明之替换及修饰，并为以下之申请专利范围所涵盖。

Claims (21)

1.一种半导体封装结构的制造方法，该方法包含：
形成复数个导电胶于一导线架阵列的引脚上，其中一凹槽设置于该引脚上与该各导电胶分离一预定距离处；
半固化该导电胶，使得该导电胶处于半固化或黏稠的状态；
提供具有复数个凸块的至少一晶片；
电连接该晶片与该导线架阵列的引脚，藉由植入该凸块至该半固化的导电胶，其中该凹槽用以容纳与限制该半固化导电胶的溢流；
固化该半固化导电胶以紧密接合该晶片；以及
形成一封胶体覆盖该导线架以及该晶片。
2.如权利要求1所述的制造方法，其中提供具有复数个凸块的至少一晶片的步骤包含形成金凸块、铜凸块、结线金凸块、结线铜凸块或金/铜合金凸块。
3.如权利要求1所述的制造方法，进一步包含固化该封胶体的步骤。
4.如权利要求3所述的制造方法，进一步包含分割该导线架阵列的步骤。
5.如权利要求1所述的制造方法，其中该导线架阵列是一预成型（pre-molded）导线架阵列。
6.如权利要求1所述的制造方法，其中该形成一封胶体覆盖该导线架以及该晶片的步骤是藉由注塑成型（injection molding）、包覆成型(overmolding)、或底部充胶成型(underfill potting)的方式形成。
7.如权利要求1所述的制造方法，其中形成复数个导电胶于一导线架阵列的引脚上，其中一凹槽设置于该引脚上与该各导电胶分离一预定距离处的步骤包含形成围绕该导电胶的一凹槽。
8.一种半导体封装结构，包含：
一导线架阵列，具有复数个内引脚以及外引脚；
一凹槽，设置于该内引脚上；
一半导体晶片，具有复数个凸块用以电连接该半导体晶片以及该内引脚；
复数个半固化的导电胶，用以接合该半导体晶片于该内引脚之上；以及
一封胶体，用以密封并覆盖该半导体晶片以及该导线架；
其中该凹槽设置于该引脚上与该各导电胶分离一预定距离处，且当该晶片上之凸块植入至该导电胶，该凹槽经配置以容纳与限制该半固化导电胶的溢流，且该半固化的导电胶经由充分固化以紧密接合导线架阵列上的该晶片。
9.如权利要求8所述的半导体封装结构，其中该凸块包含金凸块、铜凸块、结线金凸块、结线铜凸块，或金/铜合金凸块。
10.如权利要求8所述的半导体封装结构，其中该封胶体进一步被固化且该导线架阵列进一步被分割。
11.如权利要求8所述之半导体封装结构，其中该导线架阵列是一预成型（pre-molded）导线架阵列。
12.如权利要求11所述之半导体封装结构，其中该预成型导线架阵列包含一支持载体、置放于该支持载体上的复数个引脚，其中引脚该包含内引脚以及外引脚、以及半固化的第二封胶体，其中该第二封胶体涂覆于一胶带上，该胶带置放于该内引脚的顶部表面用以涂布与覆盖该导线架。
13.如权利要求12所述之半导体封装结构，其中该胶带于后续步骤中被移除且该第二封胶体被固化。
14.如权利要求8所述的半导体封装结构，其中该凹槽围绕该导电胶以避免该导电胶溢流。
15.一种预成型（pre-molded）导线架封装的制造方法，该方法包含：
形成一半固化的封胶体于一导线架阵列的复数个引脚以及一支持载体之间；
藉由固化该半固化的封胶体以形成一预成型导线架；
连接具有复数个凸块的至少一晶片于该等引脚上，各晶片与部分的该引脚藉由复数个凸块电连接；
形成一凹槽于各引脚上，该凹槽用以容纳与限制该凸块的溢流；
藉由该封胶体覆盖该晶片以及该导线架阵列；以及
分割该被覆盖的该晶片以及该导线架阵列以形成一封装结构，其中该封装结构包含一被覆盖的该晶片以及一部份的被覆盖的导线架阵列。
16.如权利要求15所述的制造方法，其中形成一半固化的封胶体的步骤包含涂覆一半固化封胶体于一胶带的背面，藉由一层迭步骤置放该胶带于该引脚的上表面，并于后续步骤中移除该胶带。
17.如权利要求16所述的制造方法，其中该涂覆一半固化封胶体于一胶带的背面的步骤包含一浸渍（dipping）、网版印刷(screen-printing)、涂布(painting)、旋涂(spin-coating)、或喷雾(spraying)制程。
18.如权利要求15所述的制造方法，其中形成一凹槽的步骤包含形成一凹槽围绕该凸块。
19.如权利要求15所述的制造方法，其中藉由该封胶体覆盖该晶片以及该导线架阵列的步骤是藉由注塑成型（injection molding）、包覆成型(over molding)、或底部充胶成型(underfill potting)的方式形成。
20.如权利要求15所述的制造方法，其中连接具有复数个凸块的至少一晶片于该等引脚上包含藉由一热超音波（thermo-ultrasonic）制程直接连接该凸块与该导线架阵列的引脚。
21.如权利要求15所述的制造方法，其中该预成型导线架封装为一四方扁平无引脚封装（Quad Flat Non-Leaded Package，QFN）。
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CN103730378A (zh) * 2013-12-05 2014-04-16 南通富士通微电子股份有限公司 封装结构的形成方法
CN103730378B (zh) * 2013-12-05 2016-08-31 南通富士通微电子股份有限公司 封装结构的形成方法
CN103824785B (zh) * 2013-12-05 2017-01-11 南通富士通微电子股份有限公司 封装结构的形成方法
CN103972113B (zh) * 2014-05-22 2016-10-26 南通富士通微电子股份有限公司 封装方法
CN104064533A (zh) * 2014-07-03 2014-09-24 江苏东光微电子股份有限公司 一种双面半导体器件的qfn封装结构及方法
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CN106206480B (zh) * 2015-05-04 2018-10-19 南茂科技股份有限公司 芯片封装结构及其制作方法
CN105551986A (zh) * 2015-12-09 2016-05-04 南通富士通微电子股份有限公司 一种覆晶薄膜(cof)封装方法
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CN107026143B (zh) * 2016-01-29 2022-07-12 德克萨斯仪器股份有限公司 引线框的下沉设置
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CN111599781A (zh) * 2019-02-20 2020-08-28 丰田自动车株式会社 半导体装置
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