CN101540300A - 晶片封装体 - Google Patents
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Abstract
本发明提出一种晶片封装体,包括:晶片座、多个引脚、晶片、粘着层以及封装胶体。其中,晶片座具有一顶面以及相对应的一底面,而顶面上配置有一止挡部,且这些引脚环绕晶片座配置。晶片配置在止挡部所环绕的晶片座的顶面上,且与这些引脚电性连接。而且,止挡部的一顶面高于其所环绕的顶面。另外,粘着层配置在晶片与晶片座之间。封装胶体包覆晶片、部分引脚与晶片座。
Description
技术领域
本发明是有关于一种晶片封装体,且特别是有关于一种可改善内部的粘着材料的溢胶现象而衍生的问题的晶片封装体。
背景技术
在半导体产业中,集成电路(integrated circuits,IC)的生产主要可分为三个阶段:集成电路的设计(IC design)、集成电路的制作(IC process)及集成电路的封装(IC package)。
在集成电路的封装中,裸晶片是先经由晶圆(wafer)制作、电路设计、光掩模制作以及切割晶圆等步骤而完成,而每一颗由晶圆切割所形成的裸晶片,经由裸晶片上的焊垫(bonding pad)与封装基材(substrate)电性连接,再以封装胶体(molding compound)将裸晶片加以包覆,以构成一晶片封装(chip package)结构。封装的目的在于,防止裸晶片受到外界温度、湿气的影响以及杂尘污染,并提供裸晶片与外部电路之间电性连接的媒介。
请参考图1,其绘示现有的一种晶片封装体的剖面示意图。现有晶片封装体100包括一晶片110、一导线架(lead frame)120、导电接合材料130与一封装胶体140。其中,导线架120具有一晶片座(die pad)122与多个引脚(lead)124。晶片110则是通过导电接合材料130配置于晶片座122上,并通过多条导线152而电性连接至引脚124。封装胶体140则包覆晶片110、导线152、晶片座122与各个引脚124的一部分。另外,现有晶片封装体100还包括多条接地导线154,其可电性连接晶片110与晶片座122。
然而,现有晶片封装体的导电接合材料会有溢胶现象,而造成晶片封装体的不正常电性连接以及可靠度降低等问题。一般而言,在实际进行晶片粘晶(diebond)的制程时,导电接合材料130容易产生溢胶而污染晶片座上的接地导线154(如图1所示)。而且,导电接合材料也容易因制程中的受压与受热,使得其中的导电粒子接触接地导线,而使其电性相连。
由上述可知,现有晶片封装结构100实有改进的必要性。
发明内容
有鉴于此,本发明的目的就是在提供一种晶片封装体,能够避免因晶片与晶片座之间的粘着材料的溢胶现象而造成不正常电性连接,且可提高封装体的可靠度。
为了达到上述目的,本发明提出一种晶片封装体,包括:晶片座、多个引脚、晶片、粘着层以及封装胶体。其中,晶片座具有一顶面以及相对应的一底面,而顶面上配置有一止挡部,且这些引脚环绕晶片座配置。晶片配置在止挡部所环绕的晶片座的顶面上,且与这些引脚电性连接。而且,止挡部的一顶面高于其所环绕的晶片座的顶面。另外,粘着层配置在晶片与晶片座之间。封装胶体包覆晶片、部分引脚与晶片座。
依照本发明的实施例所述的晶片封装体,上述的止挡部例如是一环形止挡部、多个子止挡部,或者是离散配置的多个条形子止挡部和多个L形子止挡部。
依照本发明的实施例所述的晶片封装体,上述的晶片座还包括具有一沟槽,且此沟槽位于晶片座的顶面。
依照本发明的实施例所述的晶片封装体,上述的晶片座的底面具有一第一开口及/或邻近晶片座的至少一引脚的一端具有一第二开口。
依照本发明的实施例所述的晶片封装体,还包括多条第一导线,其分别连接晶片与这些引脚的一端,另外还还可包括多条第二导线,其分别连接晶片与晶片座。
依照本发明的实施例所述的晶片封装体,上述的粘着层为一导电胶,而导电胶例如是银胶。
依照本发明的实施例所述的晶片封装体,上述的封装胶体的材料为高分子。
依照本发明的实施例所述的晶片封装体,上述的止挡部是由蚀刻而和晶片座一体成型,其材料与晶片座的材料相同。另外,上述的止挡部还可是由电镀方式形成,其材料为金属。上述的止挡部也可是由涂胶方式形成,其材料为高分子材料。
本发明是通过在晶片座上配置止挡部,以避免粘着层因溢胶现象而与接地导线接触,进而避免发生不正常的电性连接以提高封装体的可靠度。另外,本发明的晶片座上还可进一步具有沟槽,以更好地有助于避免因粘着层的溢胶现象而发生不正常的电性连接。此外,在晶片座的底面及/或邻近晶片座的至少一引脚的一端还可具有开口,以增加与封装胶体接触的面积,使得引脚与晶片座不易造成脱落或移位等问题。
附图说明
为让本发明的上述目的、特征和优点能更明显易懂,以下结合附图对本发明的具体实施方式作详细说明,其中:
图1所绘示为现有的一种晶片封装体的剖面示意图。
图2所绘示为本发明的一实施例的一种晶片封装体的剖面示意图
图3与图4所绘示为本发明的晶片座与止挡部的配置示意图。
图5A、图5B与图5C所绘示为本发明的具有沟槽与止挡部的晶片座的示意图。
图6A、图6B与图6C所绘示为本发明的晶片座与引脚的剖面示意图。
图7A、图7B与7C所绘示分别为本发明的止挡部的第一、第二、第三实施例的上视示意图。
主要元件符号说明:
100、200:晶片封装体
110、206、303:晶片
120:导线架
122、202、302:晶片座
124、204:引脚
130:导电接合材料
140、210:封装胶体
152、154、214、216:导线
201、207:接点
203a:顶面
203b:底面
205:焊垫
208:粘着层
212:止挡部
218:区域
220:沟槽
222、224:开口
304:矩形环状止挡部
306:线状止挡部
308:条形子止挡部
310:L形子止挡部
具体实施方式
以下将列举多个封装结构以进一步说明本发明,但这些例子并非用以限定本发明的范围。
图2所绘示为本发明的一实施例的一种晶片封装体的剖面示意图。
如图2所示,本实施例的晶片封装体200包括晶片座202、多个引脚204、晶片206、粘着层208以及封装胶体210。其中,晶片座202具有一用以承载晶片的顶面203a以及相对应的一底面203b,而这些引脚204为环绕晶片座202的周围进行配置。晶片206则是通过粘着层208配置于晶片座202上,其中此粘着层208例如是银胶或其他适用的导电胶体。
另外,晶片206是以打线接合(wire bonding,W/B)的方式,通过多条导线214连接晶片206的焊垫205与这些引脚204的接点207,以使晶片206电性连接这些引脚204的其中之一。其中,导线214例如是金线或其他合适的导电材料。此外,还包括配置有多条导线216,其作为接地导线,以电性连接晶片206的焊垫205与晶片座212的接点201。
而且,本实施例的晶片封装体200还包括配置有一止挡部212。止挡部212是配置在晶片座202的顶面203a上,且环绕晶片206的周围进行配置。特别是,止挡部212的一顶面会高于其所环绕的顶面203a(即是指,区域218的顶面203a),而此特殊的设计可避免粘着层208因溢胶现象而与接地导线接触,进而避免发生不正常的电性连接以及提高封装体的可靠度。
在本实施例中,止挡部212的顶面高于区域218的顶面203a,而止挡部212两侧的顶面高度相同。但是,在其他实施例中,止挡部212两侧的顶面高度也可以是不相同的情况。请参照图3与图4,其绘示本发明的晶片座与止挡部的配置示意图。如图3所示,止挡部212的顶面高于区域218的顶面203a,而区域218的顶面203a高度高于止挡部212的另一侧的顶面高度。如图4所示,止挡部212的顶面高于区域218的顶面203a,而区域218的顶面203a高度低于止挡部212的另一侧的顶面高度。
承上述,止挡部212的材料例如是与晶片座202的材料相同,其可例如是利用蚀刻方式而和晶片座202形成一体成型的结构。止挡部212的材料也可例如是金属材料,而其例如是由电镀方式所形成。止挡部212的材料还可例如是高分子材料,而其例如是由涂胶方式所形成。
另外,本实施例的晶片封装体200的封装胶体210,则是包覆晶片206、部分的引脚204、晶片座202、黏着层208与导线214、216。封装胶体210的材料为环氧树脂或其他合适的高分子材料。
在另一实施例中,除了上述的配置于晶片座202上的止挡部212之外,晶片座202的顶面203a上还包括具有沟槽,以更佳地助于避免因粘着层208产生溢胶现象而发生不正常的电性连接。为了便于说明,图5A、图5B与图5C中仅绘示出具有沟槽与止挡部的晶片座,而省略绘示出其他构件,且其皆是以图2的晶片座202来做进一步说明。如图5A所示,在晶片座202的顶面203a上可具有至少一沟槽220,其位于止挡部212的外缘;如图5B所示,沟槽220可例如是位于止挡部212所环绕的区域内;如图5C所示,在止挡部212的外缘与其所环绕的区域内皆可具有沟槽220。当然,沟槽不限定其尺寸、数量及形状,因此任何些微的变化均可视为未脱离本发明所涵盖的范围。
在又一实施例中,请参照图6A、图6B与图6C,其绘示本发明的晶片座与引脚的剖面示意图。同样地,为了便于说明,图式中仅绘示出具有止挡部的晶片座、引脚与封装胶体,而省略绘示出其他构件,且以图2的晶片座202来做进一步说明。如图6A所示,在晶片座202的底面203b可具有一开口222,其可增加与封装胶体接触的面积,而使得晶片座不易产生移位。如图6B所示,在邻近晶片座202的至少一引脚204的一端具有一开口224,其可增加与封装胶体接触的面积,而使得引脚不易造成脱落。另外,如图6C所示,在晶片座202的底面203b与邻近晶片座202的至少一引脚204的一端,皆可具有开口222、224。当然,在图6A、图6B与图6C的实施例中,在晶片座上还可具有上述的实施例的沟槽(未绘示),其为本领域具有通常知识者依据上述实施例能具体实施,故于此不再赘述。
接下来,为了更详细说明本发明的特征及功效,特以多个实施例配合图式具体说明本发明的止挡部,以使本领域具有通常知识者能具体实施。
请参照图7A、图7B与7C,其所绘示分别为本发明的止挡部的第一、第二、第三实施例的上视示意图,而图式中仅绘示出晶片、晶片座与止挡部,以便于说明。
如图7A所示,本发明的晶片座302上配置有一环形止挡部,其可将粘着层的溢胶限制于环形止挡部所围出的区域内,以避免粘着层的溢胶与接地导线接触。环形止挡部为配置于晶片303周围,其可例如是矩形环状止挡部304。当然,其他可具体实施的圆形、多边形等环形形状,亦在本发明所涵盖的范围内。
另外,如图7B所示,本发明的止挡部可由多个子止挡部构成,而子止挡部例如是线状止挡部306,通过将这些线状止挡部306适当排列可延长粘着层的溢胶的溢流路径,进而可阻挡粘着层的溢胶接触到接地导线。如图7C所示,本发明的止挡部还可由离散配置的多个条形子止挡部308以及多个L形子止挡部310构成。当然,止挡部不限定其排列方式、尺寸、数量及形状,因此任何些微的变化均可视为未脱离本发明所涵盖的范围。
综上所述,本发明通过晶片座上配置有止挡部的特殊设计,可避免粘着层因溢胶现象而与接地导线接触,进而避免发生不正常的电性连接以提高封装体的可靠度。另外,除了止挡部之外,本发明的晶片座上可具有沟槽,以更佳能够有助于避免因粘着层的溢胶现象而发生不正常的电性连接。此外,在晶片座的底面及/或邻近晶片座的至少一引脚的一端还可具有开口,以增加与封装胶体接触的面积,使得引脚与晶片座不易造成脱落或移位等问题。
虽然本发明已以较佳实施例揭示如上,然其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可作些许的修改和完善,因此本发明的保护范围当以权利要求书所界定的为准。
Claims (10)
1.一种晶片封装体,包括:
一晶片座,具有一顶面以及相对应的一底面,该顶面上配置有一止挡部;
多个引脚,环绕该晶片座配置;
一晶片,配置在该止挡部所环绕的该晶片座的该顶面上,且与该些引脚电性连接,其中该止挡部的一顶面高于其所环绕的该晶片座的顶面;
一粘着层,配置在该晶片与该晶片座之间;以及
一封装胶体,包覆该晶片、部分该些引脚与该晶片座。
2.如权利要求1所述的晶片封装体,其特征在于,该止挡部包括一环形止挡部。
3.如权利要求1所述的晶片封装体,其特征在于,该止挡部包括多个子止挡部。
4.如权利要求1所述的晶片封装体,其特征在于,该止挡部包括离散配置的多个条形子止挡部以及多个L形子止挡部。
5.如权利要求1所述的晶片封装体,其特征在于,该晶片座还包括具有一沟槽,且该沟槽位于该顶面。
6.如权利要求1所述的晶片封装体,其特征在于,该晶片座的该底面具有一第一开口及/或邻近该晶片座的至少一该些引脚的一端具有一第二开口。
7.如权利要求1所述的晶片封装体,其特征在于,还包括多条第一导线,分别连接该晶片与该些引脚的一端。
8.如权利要求7所述的晶片封装体,其特征在于,还包括多条第二导线,分别连接该晶片与该晶片座。
9.如权利要求1所述的晶片封装体,其特征在于,该止挡部是由电镀方式形成,其材料为金属。
10.如权利要求1所述的晶片封装体,其特征在于,该止挡部是由涂胶方式形成,其材料为高分子材料。
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CN103000538A (zh) * | 2011-09-14 | 2013-03-27 | 南茂科技股份有限公司 | 半导体封装结构的制造方法 |
CN110263655A (zh) * | 2019-05-24 | 2019-09-20 | 江苏凯尔生物识别科技有限公司 | 发光型指纹芯片模组 |
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CN103000538A (zh) * | 2011-09-14 | 2013-03-27 | 南茂科技股份有限公司 | 半导体封装结构的制造方法 |
CN110263655A (zh) * | 2019-05-24 | 2019-09-20 | 江苏凯尔生物识别科技有限公司 | 发光型指纹芯片模组 |
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