CN102208391A - 具有凹陷的单元片接合区域的引线框 - Google Patents

具有凹陷的单元片接合区域的引线框 Download PDF

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CN102208391A
CN102208391A CN2010101391269A CN201010139126A CN102208391A CN 102208391 A CN102208391 A CN 102208391A CN 2010101391269 A CN2010101391269 A CN 2010101391269A CN 201010139126 A CN201010139126 A CN 201010139126A CN 102208391 A CN102208391 A CN 102208391A
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Prior art keywords
dice
lead frame
engaging zones
thickness
face
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果立苹
贺青春
田兆君
杨洁
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NXP USA Inc
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Freescale Semiconductor Inc
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Priority to CN2010101391269A priority Critical patent/CN102208391A/zh
Priority to US13/018,438 priority patent/US20110241187A1/en
Publication of CN102208391A publication Critical patent/CN102208391A/zh
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Abstract

一种具有凹陷单元片接合区域的引线框。该引线框具有顶面和底面及被限定为顶面与底面之间的距离的第一引线框厚度。该引线框具有位于减小的单元片接合区域内的单元片接合区域表面。第二厚度被限定为单元片接合区域表面与底面之间的距离。第二引线框厚度小于第一引线框厚度，使得被设置并附接于单元片接合区域表面的半导体单元片具有减小的总封装厚度。在单元片接合区域表面与顶面之间形成的侧壁包含用来附接单元片的粘合材料，其减小粘合剂溢流并防止导线接合污染。

Description

具有凹陷的单元片接合区域的引线框
技术领域
本发明总体上涉及半导体器件，更特别地涉及封装半导体器件内的引线框和半导体集成电路单元片组件。
背景技术
在传统封装半导体器件中，诸如图1A～1C所示，封装半导体器件40通常包括引线框(lead frame)10和半导体集成电路(IC)单元片(die)12。引线框10包括单元片接合区域(bond area)(也称为单元片焊盘(pad)或标记(flag))14和围绕单元片接合区域14的多个导电区16(也称为引线指)。引线框12是器件10的中心支撑结构。单元片12通常用诸如环氧树脂材料的粘合剂18附接于单元片接合区域。在将单元片12附接于引线框12之后，在单元片12的单元片焊盘(未示出)与引线框10的导电区16之间连接导线(wire)20，以实现单元片12与诸如印刷电路板(PCB)等下面的衬底之间的电互连。陶瓷或塑料材料的模制化合物(mold compound)22密封引线框10、单元片12和导线20的至少一部分以保护单元片14和导线20不受环境影响。
半导体工业需要越来越小且越薄的半导体封装。另外，半导体封装上的导线和焊盘(有时称为引脚)的数目日益增加。这两个因素已成为问题的来源。一个问题是太厚的单元片可能不再合适，因为结果得到的封装的总厚度可能超过规格要求。另一问题是粘合剂或环氧树脂溢流(bleeding)随着导线和焊盘数目的增加及焊盘节距的减小而变成一个大问题。当使用环氧树脂来将IC单元片附接于具有金属表面的衬底或引线框时可能发送环氧树脂溢流。环氧树脂溢流污染导线接合，导致低导线剥离强度和引线上不粘结问题，则可能导致器件故障。
需要解决或至少缓解与传统封装半导体器件相关的以上问题以满足工业需要。
附图说明
为了可以借助于非限制性示例完全且更透彻地理解本发明的实施例，结合附图来进行以下说明，在附图中，相似的附图标记指示类似或相应的元件、区域和部分，并且其中：
图1A是传统引线框的顶视平面图；
图1B是具有附接单元片的图1A的引线框的横截面侧视图；
图1C是包括图1A的引线框及图1B的引线框和单元片的传统封装半导体器件的横截面侧视图；
图2A是依照本发明的实施例的引线框的顶视平面图；
图2B是具有附接单元片的图2A的引线框的横截面侧视图；
图2C是依照本发明的实施例的包括图2A的引线框及图2B的引线框和单元片的封装半导体器件的横截面侧视图；
图2D依照本发明的另一实施例的封装半导体器件的横截面侧视图；以及
图3是示出依照本发明的实施例的封装IC单元片的方法的流程图。
具体实施方式
本发明的一方面是用于接纳并电连接到半导体单元片的引线框。引线框包括顶面和底面。第一引线框厚度被限定为顶面与底面之间的距离。在顶面中设置用于接纳半导体单元片的减小的单元片接合区域。该减小的单元片接合区域具有在顶面与底面之间的单元片接合区域表面和围绕减小的单元片焊盘区域表面的周边延伸至顶面的侧壁。减小的单元片接合区域表面和底面限定第二引线框厚度。在本发明的一个实施例中，第二引线框厚度小于第一引线框厚度。引线框还包括布置在减小的单元片接合区域的周边周围并与之间隔开的多个导电区(引线指)。
在其它实施例中，第二引线框厚度可以是第一引线框厚度的一半、多于一半或小于一半。可以将减小的单元片接合区域表面和侧壁的尺寸和形状确定为接纳粘合材料以便将半导体单元片附接于减小的单元片接合区域内的减小的单元片接合区域表面并包含粘合材料。这用于防止粘合材料的溢流以便防止粘合材料污染导电区的顶面。可以将顶面和单元片接合区域表面布置为相互平行，侧壁可以垂直于顶面和单元片接合区域表面。侧壁可以具有其它结构，诸如在顶面与单元片接合区域表面之间竖直、倾斜等等。
在另一实施例中，本发明提供了包括具有顶面和底面的引线框的半导体单元片封装。第一引线框厚度被限定为顶面与底面之间的距离。引线框在顶面中具有减小的单元片接合区域。减小的单元片接合区域具有位于顶面与底面之间的单元片接合区域表面和围绕减小的单元片接合区域表面的周边延伸至顶面的侧壁。单元片接合区域表面和底面限定小于第一引线框厚度的第二引线框厚度。引线框具有布置在减小的单元片接合区域的周边周围并与之间隔开的多个导电区(引线指)。半导体单元片具有附接在减小的单元片接合区域内的第一表面。半导体单元片的第二表面包括与所述多个导电区(引线指)中的至少一个电互连的单元片焊盘。通过用模制化合物至少部分地密封半导体单元片和引线框来形成封装体。
在另一实施例中，本发明提供形成用于半导体单元片封装的引线框的方法，包括：提供引线框，其具有顶面和底面及被限定为顶面与底面之间的距离的第一引线框厚度；在顶面中形成用于接纳半导体单元片的减小的单元片接合区域，该减小的单元片接合区域具有单元片接合区域表面和围绕减小的单元片接合区域表面的周边延伸至顶面的侧壁，并具有被限定为减小的单元片焊盘区域表面与底面之间的距离的第二引线框厚度。第二引线框厚度小于第一引线框厚度。引线框还具有围绕减小的单元片接合区域的周边布置并与之间隔开的多个导电区。
在一个实施例中，所述方法还包括将具有第一表面的半导体单元片与粘合层、设置在减小的单元片接合区域内的第一表面、以及设置在半导体单元片的第一表面与单元片接合区域表面之间的粘合层附着以便形成引线框单元片组件。该方法还可以包括将半导体单元片与引线框的导电区互连，并用密封材料(encapsulation material)来密封互连的引线框单元片组件以便形成半导体封装器件。在将半导体单元片附接于减小的单元片接合区域之前，可以通过背研磨、蚀刻或背研磨与蚀刻的组合将半导体单元片的厚度减小至期望的厚度。
现在参照图2A至2C，示出了依照本发明的实施例的引线框50。图2A示出引线框50的顶视平面图，单元片52位于引线框50的减小的单元片接合区域54内。引线框50包括围绕减小的单元片接合区域54并与之间隔开的多个导电区或引线指56。
图2B示出引线框单元片组件60的横截面侧视图，其中，单元片52用粘合剂62附接于减小的单元片区域54，且单元片52的顶面或上表面上的单元片焊盘(未示出)用导线64电耦合到导电区56。粘合剂62可以是本领域中已知的环氧树脂材料。可以使用传统导线接合工艺将导线64附着于导电区56和单元片52的单元片接合焊盘。
引线框50具有顶面57(它是导电区56的顶面)和底面58(被指示于导电区56的底面)。引线框50的第一厚度被限定为顶面与底面57、58之间的距离。如所示，引线框50的单元片接合区域54已经减小。更具体地，单元片接合区域54的厚度小于以上限定的第一厚度。减小的单元片接合区域54包括位于顶面57与底面58之间的单元片接合区域表面59。通过单元片接合区域54处的引线框50的厚度的减小来形成围绕单元片接合区域表面59的周边延伸至顶面57的侧壁61。根据本发明，单元片接合区域表面59与底面58之间的距离限定小于第一引线框厚度的第二引线框厚度。在本发明的一个实施例中，第二引线框厚度是第一引线框厚度的一半，在本发明的另一实施例中，第二引线框厚度小于第一引线框厚度的一半。在又一实施例中，第二引线框厚度大于第一引线框厚度的一半。
单元片接合区域表面59和侧壁61的尺寸被确定为将用来将单元片52附接于单元片接合区域表面59的粘合材料62保持在减小的单元片接合区域54内以防止粘合材料的溢流，以便粘合材料不会污染引线框50的顶面57和多个导电区56。在本发明的一个实施例中，顶面57和单元片接合表面59处于平行平面中，且侧壁62垂直于顶面57和单元片接合区域表面59。在本发明的另一实施例中，侧壁61在顶面57与单元片接合区域表面59之间倾斜。
图2C是封装器件66的横截面侧视图，其中，陶瓷或塑料材料的模制化合物68形成半导体单元片封装体并且密封或部分地密封引线框单元片组件60。模制化合物68保护单元片52和导线64不受环境影响。
在图3中示出依照本发明的实施例的用于制造封装半导体器件56的工艺100。在步骤102处，提供具有单元片接合区域的引线框。在步骤104处，通过去除单元片接合区域的一部分来减小单元片接合区域的厚度。例如，典型的引线框由铜(Cu)片形成，所述铜(Cu)片可以涂敷诸如金(Au)、镍(Ni)、钯(Pd)等金属层或与诸如金(Au)、镍(Ni)、钯(Pd)等金属层形成合金。在去除工艺中，诸如通过选择性地向单元片接合区域涂敷和去除抗蚀剂材料直至预定量的单元片接合区域已被去除(即，至预定深度)为止来蚀刻(例如化学湿法蚀刻)单元片接合区域的标记去除的(marked out)区域。单元片接合区域不被整体地或完全蚀穿。引线框的底面保持原状。因此，在引线框的顶面中形成减小或凹陷的单元片接合区域。结果得到的凹坑的深度可以针对特定应用和根据蚀刻前的引线框初始厚度而改变。在凹陷的单元片接合区域的区域中不存在引线框的设定最小结果厚度，然而，凹陷单元片接合区域的区域中的引线框结果厚度必须具有足够的强度，以提供足以在单元片附接、导线接合、密封、以及切单的其余处理步骤期间提供充分支撑的强度或刚性。应理解的是可以使用不同的技术来去除引线框的材料以形成期望的凹陷单元片接合区域。例如，可以使用基于光刻的蚀刻工艺，或者，可以使用其它技术、化学和/或工艺来蚀刻、研磨或其它方法来形成凹陷单元片焊盘区域，且其可以依照本发明的实施例而广泛地改变。
在部分地蚀刻单元片接合区域之后，用粘合材料(例如胶带、环氧树脂、焊料等)将单元片附接于单元片接合区域，然后在步骤108处用导线接合工艺将单元片电连接到引线框。半导体单元片可以是包括集成电路和单元片接合焊盘的任何适当半导体单元片。然后，在步骤110处，用诸如环氧树脂或其它塑料或陶瓷材料的密封材料来密封组件以形成半导体封装器件。通过部分地蚀刻单元片接合区域，单元片附接的区域和在单元片的周边周围的围绕区域相对于导电区凹陷。通过减小单元片接合区域来形成侧壁使得单元片被侧壁围绕。侧壁的作用为包含用来将单元片附接于单元片接合区域的粘合剂并防止粘合材料溢流或污染引线框的导电区。侧壁可以采取不同的形状。例如，引线框的顶面和单元片接合区域表面可以是平行的，且侧壁可以垂直或与引线框的顶面和单元片接合区域表面两者形成90°角。侧壁69可以与顶面和单元片接合区域表面形成不同的角度，且可以是竖直的、弯曲的或具有其它构型。由于单元片在引线框中凹陷，总体完成的封装半导体器件更薄，或比用传统引线框封装的器件具有更低的剖面。
现在，参照图1B～1C和2B～2C，将传统封装器件40与本发明的封装器件66相比较以解释本发明实施例的差别和优点。
首先，将参照图1B和2B来进行各种宽度测量的比较。在图1B中，指示以下宽度测量：单元片宽度30、总体引线框宽度32、导电区或引线指宽度34、以及环氧树脂溢流区宽度36，其中，宽度36本质上是单元片接合区域的宽度减单元片宽度30。环氧树脂溢流区36的宽度是近似的，因为环氧溢流延伸超过区域36是可能的。某些示例性尺寸是单元片宽度30可以约为1.94mm、引线框32可以为3.0mm，引线指宽度34可以为0.15mm，而环氧树脂溢流区36可以为0.38mm。(因此，对于具有3.0mm的宽度32、0.15mm的引线指宽度、以及1.94mm的环氧树脂溢流区宽度36的引线框而言，最大单元片尺寸为1.94，当然，也可以将更小的单元片附接于此类引线框)。
在图2B中，指示以下宽度测量，单元片宽度70、总体引线框宽度72、导电区或引线指宽度74、以及环氧树脂溢流区宽度76。使用以上内容中的某些示例性尺寸，可以确定最大单元片宽度。如果总体引线框宽度72保持在3.0mm，且导电区宽度74保持在0.15mm，则树脂溢流区宽度36只需约为0.1mm宽，则将允许2.5mm的最大单元片尺寸(与使用传统引线框10的1.94mm相比)。环氧树脂溢流区可以比传统设计中所需的区域小，因为侧壁61防止环氧树脂溢流。
本发明还允许具有比使用传统引线框10组装的器件更薄的剖面的封装器件。现在将使用图1C和2C进行比较。
参照图1C，传统封装半导体器件40具有在41处指示的总封装厚度。总封装厚度41包括引线框厚度42、粘合材料厚度43、单元片厚度44、导线环高度45、以及环氧树脂或密封材料厚度46。向这些尺寸赋予某些示例性值，我们得到8密耳(0.2032mm)的引线框厚度49、1密耳(0.254mm)的粘合材料厚度43、14密耳(0.3556m)的单元片厚度44、8密耳(0.2032mm)的导线环高度45、以及4密耳(0.1016mm)的环氧树脂或密封材料厚度46，加起来等于35密耳(0.889mm)。
现在参照图2C，依照本发明的实施例的封装半导体器件66具有在81处指示的总封装厚度。总封装厚度81包括减小的引线框厚度82、粘合材料厚度83、单元片厚度84、导线环高度85、以及环氧树脂或密封材料厚度86。如上赋予类似的值，我们得到3密耳(0.0762mm)的减小的引线框厚度82、1密耳(0.254mm)的粘合材料厚度83、14密耳(0.3556mm)的单元片厚度84、8密耳(0.2032mm)的导线环高度85、以及4密耳(0.1016mm)的环氧树脂或密封材料厚度86，加起来等于30密耳(0.762mm)。因此，如图2C所示，总封装厚度81小于传统器件40的总封装厚度。
更特别地，由于凹陷单元片接合区域的凹陷区域深度约为5密耳(0.127mm)，单元片52所处位置比尚未蚀刻的引线框的部分的顶面低约5密耳(0.127mm)。因此，依照本发明的实施例的封装器件80的总封装厚度比图1C所示的传统封装半导体40小约5密耳(0.127mm).
现在参照图2D，示出依照本发明的引线框和封装半导体器件的另一实施例。在图2D中，示出封装半导体器件90的横截面侧视图。器件90包括上述第一实施例的引线框50、粘合材料62、导线64和密封剂68。单元片91被附接于引线框50，并且在本实施例中，单元片91在附接于引线框50之前经历背研磨的附加步骤以减小单元片91的厚度。用背研磨，可以将单元片91的厚度从14密耳(0.3556mm)减小至约5密耳(0.1270mm)。由于单元片厚度减小，所以封装半导体90的总厚度减小。
对于与图2C的封装半导体80的比较，使用相应尺寸。因此，我们得到3密耳(0.0762mm)的减小的引线框厚度92、1密耳(0.254mm)的粘合材料厚度93、5密耳(0.1270mm)的单元片厚度94、8密耳(0.2032mm)的导线环高度95、以及4密耳(0.1016mm)的环氧树脂或密封材料厚度96，加起来等于21密耳(0.5334mm)。因此，如图2D所示，总封装厚度97小于第一实施例的总封装厚度91并且远小于传统器件40的总封装厚度。
可以使用背表面研磨器来对诸如半导体单元片的背面或底面等的单元片表面进行背研磨，以便将单元片的厚度减小至期望的厚度，例如从14密耳(0.3556mm)等至3密耳(0.0762mm)或4密耳(0.1016mm)。减小单元片厚度的工艺可以替换为除背研磨之外的其它手段，诸如蚀刻，背研磨与蚀刻的组合等等。可以将单元片厚度减小以适合特定的设计要求，然而，也考虑诸如单元片挠曲等其它因素以确定单元片的最小厚度。
虽然已描述并示出了本发明的实施例，但本领域的技术人员应理解的是在不脱离本发明的情况下，可以进行设计或构造细节方面的许多变更或修改。

Claims (10)

1.一种用于接纳并电连接到半导体单元片的引线框，所述引线框包括：
顶面和顶面，其中，第一引线框厚度被限定为所述顶面与所述底面之间的距离；
在所述顶面中的减小的单元片接合区域，用于接纳半导体单元片，所述减小的单元片接合区域具有位于所述顶面与所述底面之间的单元片接合区域表面和围绕所述单元片接合区域表面的周边延伸至所述顶面的侧壁，其中，所述单元片接合区域表面与所述底面之间的距离限定小于所述第一引线框厚度的第二引线框厚度；以及
多个导电区，其布置在所述单元片接合区域表面的周围并与之间隔开。
2.权利要求1的引线框，其中，所述第二引线框厚度是所述第一引线框厚度的一半。
3.权利要求1的引线框，其中，所述第二引线框厚度小于所述第一引线框厚度的一半。
4.权利要求1的引线框，其中，所述单元片接合区域表面和所述侧壁的尺寸被确定为接纳用来将所述半导体单元片附接于所述减小的单元片接合区域内的所述单元片接合区域表面的粘合材料，并且所述减小的单元片接合区域内包含所述粘合材料以防止所述粘合材料的溢流，以便粘合材料不污染所述引线框的所述顶面和所述多个导电区。
5.一种半导体单元片封装，包括：
具有顶面和底面的引线框，其中，第一引线框厚度被限定为所述顶面与所述底面之间的距离，所述引线框在所述顶面中具有减小的单元片接合区域，所述减小的单元片接合区域具有位于所述顶面与所述底面之间的单元片接合区域表面和围绕所述单元片接合区域表面的周边延伸至所述顶面的侧壁，所述单元片接合区域表面和所述底面限定小于所述第一引线框厚度的第二引线框厚度，所述引线框具有布置在所述引线接合区域表面的周边的周围并与之间隔开的多个导电区；
具有第一表面和第二表面的半导体单元片，所述第一表面用粘合材料附接于所述减小的单元片接合区域内的所述单元片接合区域表面，且所述第二表面具有多个单元片接合焊盘；
将所述单元片接合焊盘与所述多个导电区电连接的多个导线；以及
密封材料，其至少部分地密封所述半导体单元片和所述引线框。
6.权利要求5的半导体单元片封装，其中，所述单元片接合区域表面和所述侧壁的尺寸被确定为接纳所述粘合材料并包含所述粘合材料，以便所述粘合材料不溢流到所述多个导电区上。
7.一种封装半导体单元片的方法，包括步骤：
提供具有顶面和底面的引线框，其中，第一引线框厚度被限定为所述顶面与所述底面之间的距离，所述引线框包括在所述顶面中的减小的单元片接合区域，用于接纳半导体单元片，所述减小的单元片接合区域具有单元片接合区域表面和围绕所述单元片接合区域表面的周边延伸至所述顶面的侧壁，其中，小于所述第一引线框厚度的第二引线框厚度被限定为所述单元片接合区域表面与所述底面之间的距离，并且，所述引线框还包括布置在所述减小的单元片接合区域的周边的周围并与之间隔开的多个导电区。
8.权利要求7的封装半导体单元片的方法，还包括以下步骤：
用粘合剂将半导体单元片的第一表面附接于所述单元片接合区域表面；
将所述半导体单元片与所述引线框的所述导电区电连接；以及
用密封材料来密封所述引线框和所述半导体单元片。
9.权利要求8的封装半导体单元片的方法，还包括在将所述半导体单元片附接于所述单元片接合区域表面之前减小所述半导体单元片的厚度。
10.权利要求9的封装半导体单元片的方法，其中，通过背研磨来减小所述半导体单元片的厚度。
CN2010101391269A 2010-03-31 2010-03-31 具有凹陷的单元片接合区域的引线框 Pending CN102208391A (zh)

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CN104681451A (zh) * 2013-12-02 2015-06-03 马克西姆综合产品公司 用于基片和裸片之间的粘合剂控制的方法
CN108281407A (zh) * 2017-01-05 2018-07-13 意法半导体公司 具有粘合剂溢流凹部的经修改的引线框架设计
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US9941219B2 (en) 2014-09-19 2018-04-10 Intel Corporation Control of warpage using ABF GC cavity for embedded die package
JP6869602B2 (ja) * 2016-09-28 2021-05-12 エイブリック株式会社 半導体装置
US20200135632A1 (en) * 2018-10-24 2020-04-30 Texas Instruments Incorporated Die isolation on a substrate

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CN104681451A (zh) * 2013-12-02 2015-06-03 马克西姆综合产品公司 用于基片和裸片之间的粘合剂控制的方法
US10056294B2 (en) 2013-12-02 2018-08-21 Maxim Integrated Products, Inc. Techniques for adhesive control between a substrate and a die
CN110600386A (zh) * 2015-11-19 2019-12-20 日月光半导体制造股份有限公司 半导体器件封装
CN110600386B (zh) * 2015-11-19 2022-05-10 日月光半导体制造股份有限公司 半导体器件封装
CN108281407A (zh) * 2017-01-05 2018-07-13 意法半导体公司 具有粘合剂溢流凹部的经修改的引线框架设计
US10957634B2 (en) 2017-01-05 2021-03-23 Stmicroelectronics, Inc. Modified leadframe design with adhesive overflow recesses
CN108281407B (zh) * 2017-01-05 2021-10-22 意法半导体公司 具有粘合剂溢流凹部的经修改的引线框架设计
US11552007B2 (en) 2017-01-05 2023-01-10 Stmicroelectronics, Inc. Modified leadframe design with adhesive overflow recesses

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