CN110600386A - 半导体器件封装 - Google Patents

半导体器件封装 Download PDF

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Publication number
CN110600386A
CN110600386A CN201910792259.7A CN201910792259A CN110600386A CN 110600386 A CN110600386 A CN 110600386A CN 201910792259 A CN201910792259 A CN 201910792259A CN 110600386 A CN110600386 A CN 110600386A
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China
Prior art keywords
conductive
semiconductor device
device package
conductive base
cavity
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CN201910792259.7A
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CN110600386B (zh
Inventor
邱基综
王盟仁
庄程淅
谢慧英
李彗华
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明提供一种半导体器件封装，其包括一导电基底和从该导电基底的一第一表面限定的一空腔。该空腔具有一底表面和一深度。一半导体裸片，其设置在该空腔的该底表面上。该半导体裸片具有一第一表面和与该第一表面相对的一第二表面。该半导体裸片的该第二表面接合到该空腔的该底表面。该半导体裸片的该第一表面和该导电基底的该第一表面之间的一距离为该空腔的该深度的约20％。

Description

半导体器件封装
本申请是申请日为2017年8月23日，申请号为“201710728601.8”，而发明名称为“半导体器件封装”的申请的分案申请。
技术领域
本发明请求于2016年8月29日申请之美国专利申请案15/250,713的权益(benefit)和优先权(priority)(Chiu等)标题为“半导体器件封装”，其内容通过引用整体并入本文中。本公开涉及一种半导体器件封装及其制造方法。更特定来说，本发明涉及包括改进的导电基底的半导体器件封装结构及其制造方法。
背景技术
半导体器件封装结构包括接合到引线框架(leadframe)的半导体裸片。可以使用绝缘材料(例如预浸复合纤维(p.p.))来覆盖和保护半导体裸片和引线框架。然而，在将绝缘材料层叠到半导体裸片和引线框架的过程中，半导体裸片可能会破裂。因此，用于形成半导体器件封装的改进技术将是有益的。
发明内容
在一或多个实施例中，一种半导体器件封装包括一导电基底和从该导电基底的一第一表面限定的一空腔。该空腔具有一底表面和一深度。一半导体裸片，其设置在该空腔的该底表面上。该半导体裸片具有一第一表面和与该第一表面相对的一第二表面。该半导体裸片的该第二表面接合到该空腔的该底表面。该半导体裸片的该第一表面和该导电基底的该第一表面之间的一距离为该空腔的该深度的约20％。
在一或多个实施例中，一种半导体器件封装包括具有一第一表面和与该第一表面相对的一第二表面的一导电基底。从该导电基底的该第一表面限定的一空腔，且该空腔具有一底表面和一深度。一半导体裸片，其设置在该空腔的该底表面上并具有一第一厚度。在该半导体裸片和该空腔的该底表面之间的一导电粘合层，且该导电粘合层具有一第二厚度。该第一厚度和该第二厚度之和与该空腔的该深度不同。
在一或多个实施例中，一种半导体器件封装包括具有一第一表面和与该第一表面相对的一第二表面的一导电基底。一空腔，其从该导电基底的该第一表面限定并具有一底表面。该导电基底限定该空腔的一侧壁。一半导体裸片，其设置在该空腔的该底表面上，该半导体裸片具有一第一表面和与该第一表面相对的一第二表面。该半导体裸片的该第二表面接合到该空腔的该底表面。一保护层，其设置在该导电基底和该半导体裸片上，该保护层具有一第一表面。从该半导体裸片的该第一表面到该保护层的该第一表面的一第一距离与从该导电基底的该第一表面到该保护层的该第一表面的一第二距离不同。
附图说明
图1A是根据本发明的一实施例的半导体器件封装的横截面图。
图1B是根据本发明的一实施例的半导体器件封装的横截面图。
图1C是根据本发明的一实施例的半导体器件封装的横截面图。
图1D示出了根据本发明的图1A的半导体器件封装1的顶视图。
图1E示出了根据本发明的图1A的半导体器件封装1的顶视图。
图1F示出了根据本发明的图1A的半导体器件封装1的顶视图。
图1G是根据本发明的一实施例的半导体器件封装的横截面图。
图2A是根据本发明的一实施例的半导体器件封装的横截面图。
图2B是根据本发明的一实施例的半导体器件封装的横截面图。
图3是根据本发明的一实施例的半导体器件封装的横截面图。
图4是根据本发明的一实施例的半导体器件封装的横截面图。
图5是根据本发明的一实施例的半导体器件封装的横截面图。
图6A、图6B、图6C、图6D、图6E、图6F、图6G及图6H示出了制造图1A的半导体器件封装的方法。
图7A、图7B、图7C、图7D、图7E、图7F、图7G及图7H示出了制造图3的半导体器件封装的方法。
图8A、图8B、图8C、图8D、图8E、图8F及图8G示出了制造图4的半导体器件封装的方法。
图9A、图9B、图9C、图9D、图9E及图9F示出了制造图5的半导体器件封装的方法。
图10A示出了根据图6A的一实施例的导电基底的横截面图。
图10B示出了根据图10A的一实施例的导电基底的顶视图。
图11A示出了根据图6A的一实施例的导电基底的横截面图。
图11B示出了根据图11A的一实施例的导电基底的顶视图。
图12A示出了根据图6A的一实施例的导电基底的横截面图。
图12B示出了根据图12A的一实施例的导电基底的顶视图。
图13A示出了根据图6B的一实施例的导电基底的顶视图。
图13B示出了根据图13A沿着A-A线的一实施例的导电基底的横截面图。
图13C示出了根据图13A沿着B-B线的一实施例的导电基底的横截面图。
图13D是根据本发明的一实施例的半导体器件封装的横截面图。
贯穿图式及详细描述使用共同参考数字以指示相同或类似元件。本发明的实施例将从结合附图进行的以下详细描述更显而易见。
具体实施方式
在本发明中描述的是用于提供具有减小的封装尺寸的器件的技术。更特定来说，本发明涉及一种半导体器件封装结构，其包括用于在层压绝缘材料的过程中避免半导体裸片的破裂的改进的导电基底。
相对于某一组件或组件的群组或组件或组件的群组的某一平面而指定空间描述，例如“之上”、“之下”、“上”、“左”、“右”、“下”、“顶部”、“底部”、“垂直”、“水平”、“侧”、“更高”“下部”、“上部”、“上方”、“下方”等，以用于定向如相关联图中所展示的组件。应理解，本文中所使用的空间描述仅是出于说明的目的，且本文中所描述的结构的实际实施可以任何定向或方式在空间上布置，其限制条件为本发明的实施例的优点是不因此布置而有偏差。
图1A是根据本发明的一实施例的半导体器件封装1的横截面图。半导体器件封装1包括导电基底101、半导体裸片(die)20、导电粘合层(conductive adhesive layer)50、额外是支撑层(support layer)的保护层70、绝缘层72和74、互连结构40,42和44、导电垫62和导电连接60。
导电基底101包括上表面101u和与上表面101u相对的表面101b。导电基底101的材料可以是例如铜或其它金属、或金属合金或其它导电材料。在一些实施例中，导电基底101可以是裸片焊盘(die paddle)。在一些实施例中，导电基底101包括导电基底101的一个或多个平滑的角32，以在相对于形成保护层70的制造操作期间减小或最小化各别角32处的应力。角32的平滑化可以进一步设计为横跨导电基底101上重新分布应力，例如跨越导电基底101更均匀地分配应力，或将应力点从导电基底101的一部分转移到导电基底101的另一部分。因此，不同的角32可以具有不同的曲率半径(radii of curvature)和/或可以相对于导电基底101的上表面101u形成不同的锥角(angles of taper)。导电基底101包括一个或多个突起80。
空腔30从导电基底101的上表面101u凹陷。空腔30具有底表面301、侧壁302和深度D。空腔30由侧壁302和底表面301限定。在一些实施例中，空腔30由三个或四个侧壁302限定。在一些实施例中，深度D可以为约80微米(μm)至约120μm。半导体裸片20设置在空腔30的底表面301上。空腔30形成在导电基底101中以接收半导体裸片20以减小封装厚度。可以通过具有空腔30的设计来实现微缩的(compact)三维(3-D)嵌入式封装。
在一些实施例中，半导体裸片20具有上表面201和与上表面201相对的表面202。半导体裸片20的表面202通过导电粘合层接合到空腔30的底表面301。导电粘合层50可以是例如导电凝胶或环氧树脂膜(epoxy film)(与导电材料混合的环氧树脂)或其它导电材料。
导电粘合层50设置在半导体裸片20的表面202和空腔30的底表面301之间。在一些实施例中，导电粘合层50完全覆盖空腔30的底表面301，并且延伸到空腔30的至少一个侧壁302并与其接触。导电粘合层50可以接触半导体裸片20的一个或多个侧壁的一部分。导电粘合层50将半导体裸片20附接到导电基底101。在图1A所示的实施例中，导电粘合层50的量被设计为足以使导电粘合层50穿过空腔30的底表面301流出(例如，在层压操作期间)，以接触半导体裸片20的侧壁和限定空腔30的侧壁302，以缩短导电电流路径。
在图1A所示的实施例中，半导体裸片20的上表面201高于导电基底101的上表面101u。在一些实施例中，半导体裸片20的上表面201与导电基底101的上表面101u之间的距离可以是空腔30的深度D的约20％、或者可以是空腔30的深度D的至少约5％或至少约10％，以及高达空腔30的深度D的约35％或高达约25％。在一些实施例中，半导体裸片20的厚度和导电粘合层50的厚度的总和可以不同于空腔30的深度D。在一些实施例中，例如图1A所示的实施例，半导体裸片20的厚度和导电粘合层50的厚度之总和大于空腔30的深度D。
保护层70设置在导电基底101和半导体裸片20上。保护层70包括上表面701和与上表面701相对的表面702。在一些实施例中，保护层70的材料是聚丙烯树脂(polypropyleneresin)；然而，可以额外地或替代地使用其它合适的材料。如上所述，半导体裸片20的上表面201可以高于导电基底101的上表面101u(例如，如图1A的实施例所示)，其可以用于在保护层70层压的实施例中，减少或防止在保护层70的层压期间形成空隙(voids)。
互连结构42电连接到半导体裸片20的上表面201上的垫。互连结构40电连接到导电基底101的上表面101u。互连结构44电连接到导电基底101的上表面101u和半导体裸片20的上表面201上的垫。在一些实施例中，互连结构40、42和44是通过保护层70形成的通孔(vias)。互连结构40、42和44的材料可以是例如铜或其它金属，或金属合金或其它导电材料。
在一些实施例中，从半导体裸片20的上表面201到保护层70的上表面701的第一距离与从导电基底101的上表面101u到保护层70的上表面701的第二距离不同。第一距离可以小于或大于第二距离。
绝缘层72设置在保护层70的上表面701上，并且设置在互连结构40、42和44上。绝缘层74设置在保护层70的表面702和导电基底101的表面101b上。在一些实施例中，绝缘层72和74中的一个或两个的材料是焊料掩模；然而，可以额外地或替代地使用聚丙烯树脂或其它绝缘材料。导电基底101限定了填充有绝缘材料34的阶梯结构。绝缘材料34可以是例如聚丙烯树脂或其它合适的材料。绝缘层74以阶梯状结构覆盖绝缘材料34。在各别半导体器件封装1从较大的封装(例如面板)分离(切割singulation)期间，阶梯结构可以最小化或防止对绝缘层74的损坏。在一些实施例中，开口可以形成在空腔30的一个或多个侧壁302中，以在保护层70的层压期间控制绝缘材料34的流动。
导电垫62形成在互连结构42上并与其电连接。导电垫62的材料可以是例如铜或其它金属，或金属合金或其它导电材料。导电连接60(例如，焊球solder ball)设置在导电垫62上。
图1B是根据本发明的一实施例的半导体器件封装2的横截面图。半导体器件封装2包括导电基底101和103、半导体裸片20和22、导电粘合层50、保护层70(其可以是多个保护层70)、绝缘层72和74、互连结构40、40a、42、44a和46、导电垫62和导电连接60。半导体器件封装2类似于图1A的半导体器件封装1，且关于图1B，相同编号的组件不再进行描述。
导电基底103设置在半导体裸片20之上并电连接到半导体裸片20，且半导体裸片22接合并电连接至导电基底103。半导体裸片22的宽度基本上与宽度设置在半导体裸片22和导电基底103之间的导电粘合层50的宽度相同，且半导体裸片22的侧壁分别与导电粘合层50的侧壁对准。导电粘合层50是合适的粘合膜。在一些实施例中，设置在半导体裸片22和导电基底103之间的导电粘合层50不是环氧材料。保护层70设置在导电基底101、半导体裸片20、导电基底103和半导体裸片22上。
互连结构46电连接到半导体裸片22。绝缘层72设置在保护层70的上表面701上并且设置在互连结构40a、44a、46之上方。导电垫62形成在互连结构40a、44a上且电连接到互连结构40a、44a。导电连接60(例如，焊球)设置在相应的导电垫62上。
图1C是根据本发明的一实施例的半导体器件封装2'的横截面图。半导体器件封装2'包括导电基底101和103、半导体裸片20和22、导电粘合层50、保护层70(其可以包括多个保护层70)、绝缘层72和74、互连结构40、42和46、导电垫62和导电连接60。
半导体器件封装2'类似于图1B的半导体器件封装2，不同之处在于半导体裸片20和导电基底103之间的导电粘合层50是环氧膜。导电粘合层50可以接触半导体裸片22的两个侧壁中的每一个的一部分。
图1D是根据本发明的图1A的实施例的半导体器件封装1的一部分3的顶视图插图。部分3是具有空腔30的导电基底101的一部分。顶视图的空腔30的形状大致为矩形(例如，正方形square)。在该实施例中，空腔30的侧壁302在横向方向上是连续的以形成完整的矩形。突起80位于导电基底101的侧壁上。
图1E是根据本发明的图1A的实施例的半导体器件封装1的一部分4的顶视图插图。部分4是具有空腔30的导电基底101的一部分。在该实施例中，空腔30在三个侧面上被导电基底101沿横向方向包围，且导电基底101限定开口304，其中空腔30的侧壁302不延伸(例如，在半导体封装器件1的边缘)。在一些实施例中，开口304可以用于在保护层70层压期间控制绝缘材料34的流动。
图1F是根据本发明的图1A的实施例的半导体器件封装1的一部分5的顶视图插图。部分5是具有空腔30的导电基底101的一部分。在该实施例中，与图1D的实施例类似，空腔30在四个侧面上被导电基底100包围，除了导电基底100还在空腔30的两侧上限定开口305之外。在一些实施例中，开口305可以用于在层压保护层70期间控制绝缘材料34的流动。
图1G是根据本发明的一实施例的半导体器件封装1'的横截面图。半导体器件封装1'类似于图1A的半导体器件封装1，且相同编号的部件不再参照图1G进行描述。在图1G中，半导体器件封装1'还包括导电层74'，且省略绝缘层74。导电层74'的材料可以是例如镍-金或其它合适的金属或合金。在本实施例中，导电层74'设置在导电基底101的表面101b上，且不与绝缘材料34接触。
图2A是根据本发明的一实施例的半导体器件封装6的横截面图。半导体器件封装6类似于图1A的半导体器件封装1，且相同编号的部件不再参照图2A进行描述。图2A中，包括另外的导电基底102，且导电基底102通过互连结构44电连接到半导体裸片20。在一些实施例中，导电基底101和102的整个结构可以是引线框架。导电基底101和102中的一个或两个的材料是例如铜或其它金属、或金属合金或其它导电材料。在图2A所示的实施例中，半导体裸片20的上表面201低于导电基底101的上表面101u。半导体裸片20的表面201与导电基底101的上表面101u之间的距离可以为空腔30的深度D的约20％，或者可以是空腔30的深度D的至少约5％或至少约10％，并且可以是空腔30的深度D的高达约35％或高达约25％。在本实施例中，半导体裸片20的厚度和导电粘合层50的厚度之总和小于空腔30的深度D。半导体裸片20的上表面201比导电基底101的上表面101u低，以在保护层70的层压期间减少或防止对半导体裸片20的损坏。
图2B是根据本发明的一实施例的半导体器件封装6的横截面图。半导体器件封装6'类似于图2A的半导体器件封装6，且相同编号的部件不再参照图2B进行描述。在图2B中，半导体器件封装6'还包括导电层74'，且省略绝缘层74。导电层74'的材料可以是例如镍-金或其它合适的金属或合金。在本实施例中，导电层74'设置在导电基底101的表面101b和导电基底102的表面102b上，且不与绝缘材料34接触。
图3是根据本发明的一实施例的半导体器件封装7的横截面图。半导体器件封装7包括半导体裸片20、导电粘合层50、保护层70、绝缘层72、互连结构42和43、导电垫62和导电连接60。
在一些实施例中，将半导体裸片20嵌入保护层70中。半导体裸片20通过导电粘合层50结合到保护层70。导电粘合层50可以是例如导电凝胶或环氧膜(与导电材料混合的环氧树脂)。
保护层70围绕半导体裸片20。半导体裸片20电连接到互连结构42和43。在一些实施例中，互连结构42是形成在保护层70中的通孔，且互连结构43是形成在保护层70和导电粘合层50中的通孔。导电垫62设置在互连结构42上并与其电连接。导电垫62的材料可以是例如铜或其它金属或金属合金或其他导电材料。导电连接60(例如，焊球)设置在相应的导电垫62上。
图4是根据本发明的一实施例的半导体器件封装8的横截面图。半导体器件封装8类似于图2A的半导体器件封装6，且相同编号的部件不再参照图4进行描述。在图4中，如图2A所示的绝缘层74和导电基底101中的空腔30被省略。也就是说，半导体裸片20通过导电粘合层50设置在导电基底101的上表面101u上。此外，设置保护层90以覆盖绝缘层72、保护层70的侧壁和导电基底101的突起80。保护层90的材料可以是聚丙烯树脂，但是也可以另外地或替代地使用其它绝缘材料。
图5是根据本发明的一实施例的半导体器件封装9的横截面图。半导体器件封装9类似于图3的半导体器件封装7，且相同编号的部件不再参照图5进行描述。在图5中，绝缘层74设置在保护层70的表面702上。导电垫62和导电连接60设置在半导体裸片20和导电粘合层50的下方。导电连接60从绝缘层74部分暴露。因此，可以通过互连结构42和43从半导体裸片20的垫到导电连接60进行电连接(例如，用于信号传输)。
图6A～图6H示出了制造图1A的半导体器件封装1的方法。
参考图6A，提供导电基底101。导电基底101包括上表面101u和与上表面101u相对的表面101b。导电基底101的材料例如是铜或其它金属、或金属合金或其它导电材料。通孔36从导电基底101的表面101b限定。至少一个空腔30从导电基底101的上表面101u限定。空腔30具有至少一个侧壁302和到空腔30的底面301的深度D。在一些实施例中，深度D可以为约80μm至约120μm。在一些实施例中，导电基底101设置有空腔30，并且不被蚀刻以形成空腔30。也就是说，导电基底101的上表面101u不通过蚀刻技术去除。可提供相对坚固或强壮的结构的导电基底101的未蚀刻结构相对更容易被处理以便于随后的电测量/测试。
导电基底101包括一个或多个突起80。导电基底101的角32被平滑以重新分布应力，以避免层压期间对保护层70的损坏。图6B示出了根据实施例的导电基座101的顶视图。从图6B中可以看出，除了从横截面图是圆形的之外，角32在顶视图中是圆形的，且通孔也被平滑化，以避免导电基底101的尖角，其可导致在随后的层压阶段应力和相应的保护层的损坏。
参考图6C，导电粘合层50设置在空腔30的底表面301上。导电粘合层50可以是例如导电凝胶或环氧膜(与导电材料混合的环氧树脂)。半导体裸片20设置在每个空腔30中的导电粘合层50上。导电粘合层50用于将半导体裸片20附接到空腔30的底表面301。
参考图6D，通过层叠技术在导体基底101和半导体裸片20上形成保护层70。保护层70的材料可以是例如聚丙烯树脂或其它合适的材料。保护层70的一部分在层压期间熔化。导电基底101的设计可以控制熔化(melting)材料的流动以形成保护层70。导电基底101的设计，不蚀刻导电基底101的上表面101u可以例如防止熔化材料形成保护层70不流入划线(scribe lines)(未示出)。
导电层42a通过涂覆、溅射、电镀或其它合适的技术设置在保护层70的上表面701上。在一个或多个实施例中，导电层42a包括铝或铜或其合金(例如AlCu)。设置绝缘材料34以填充通孔36。
参考图6E，通过保护层70从保护层70的上表面701形成通孔401。导电层42a'通过涂覆、溅射、电镀或其它合适的技术形成在导电层42a上和通孔401中。导电层42a'连接到导电基底101和半导体裸片20。在一个或多个实施例中，导电层42a'包括铝或铜或其合金(例如AlCu)。
参考图6F，互连结构40、42和44通过例如蚀刻形成。互连结构40、42和44的材料例如是铜或其它金属、或金属合金或其它导电材料。互连结构42电连接到半导体裸片20的上表面201上的垫。互连结构40电连接到导电基底101的上表面101u。互连结构44电连接到导电基底101的上表面101u和半导体管芯20的上表面201上的垫。
参考图6G，绝缘层72设置在保护层70的上表面701上并覆盖互连结构40、42和44。绝缘层74形成在保护层70的表面702、导电基底101的表面101b和绝缘材料34上。绝缘层72和74的材料可以是聚丙烯树脂；然而，也可以另外地或替代地使用其它绝缘材料。通孔36中的绝缘材料34可以在分离(切割)期间减少或避免对绝缘层74的损坏。在其中层74的材料是镍-金或其它合适的导电材料的实施例中，层74将形成在导电基底101的表面101b上，但不与绝缘材料34接触。
参考图6H，至少一个导电垫62形成在互连结构42上。导电垫62的材料可以是例如铜或其它金属、或金属合金或其它导电材料。至少一个导电连接60(例如，焊球)形成在导电垫62上。在图6H所示的实施例中，两个或更多个半导体器件封装1同时制造，然后通过导电基底101的突起80被分离，例如通过锯切或蚀刻技术。
图7A～图7H示出了制造图3的半导体器件封装7的方法。
参考图7A，提供至少一个半导体裸片20和绝缘层70a。至少一个导电粘合层50设置在半导体裸片20的表面202上。导电层43a附接在绝缘层70a的表面702上。导电层43a的材料是例如铜或其他金属、或金属合金或其它导电材料。导电粘合层50可以是例如导电性凝胶或环氧树脂膜(与导电材料混合的环氧树脂)。绝缘层70a的材料可以是例如聚丙烯树脂或其它合适的材料。
参考图7B，半导体裸片20通过导电粘合层50附接在绝缘层70a上。图案化绝缘层70b限定用于接收半导体裸片20的通孔，且图案化绝缘层70b通过层压设置以覆盖绝缘层70a。接下来，设置绝缘层70b'以覆盖半导体裸片20和图案化绝缘层70b。导电层42a附接在绝缘层70b的上表面701上。导电层42a的材料例如是铜或其他金属、或金属合金或其它导电材料。绝缘层70b的材料可以是例如聚丙烯树脂或其它合适的材料。
参考图7C，绝缘层70a、70b和70b'通过层压技术组合以形成保护层70。从导电层42a和导电层43a的表面形成至少一个通孔301和至少一个通孔302。通孔301暴露半导体裸片20的垫。通孔302穿过导电层42a、保护层70和导电层43a。通孔301和通孔302可以例如通过钻孔形成。
参考图7D，导电层42a'形成在导电层42a上和通孔301中，且导电层43a'形成在导电层43a上和通孔301中，例如通过涂覆、溅射、电镀或其它合适的技术。导电层42a'和导电层43a'一起填充通孔302。导电层42a'和43a'包括铝或铜或其合金(例如AlCu)。
参考图7E，通过分别蚀刻导电层42a'和导电层43a'来形成互连结构42和43。互连结构42电连接到半导体裸片20的上表面201上的垫。互连结构43电连接到半导体裸片20的表面202上的垫。互连结构42和43通过导电层42a'和导电层43a'电连接。
参考图7F，绝缘层72设置在保护层70的上表面701上并覆盖互连结构42。绝缘层72的材料可以是聚丙烯树脂；然而，也可以另外地或替代地使用其它绝缘材料。
参考图7G，至少一个导电垫62形成在互连结构42上。导电垫62的材料可以是例如铜或其它金属、或金属合金或其它导电材料。在导电垫62上形成至少一个导电连接60(例如，焊球)
参考图7H，在所示的实施例中，通过锯切或蚀刻技术分离两个半导体器件封装3。
在图7H所示的实施例中，两个或更多个半导体器件封装7同时制造，然后被分离，例如通过锯切或蚀刻技术。
图8A～图8G示出了制造图4的半导体器件封装8的方法。
参考图8A，提供导电基底101和导电基底102。导电基底101包括上表面101u和与上表面101u相对的表面101b。导电基底101的材料例如是铜或其它金属、或金属合金或其他导电材料。导电基底101和102的一些角32被平滑化。提供至少一个半导体裸片20。至少一个导电粘合层50设置在导电基底101的上表面101u上。导电粘合层50可以是例如导电凝胶或环氧膜(与导电材料混合的环氧树脂)。
参考图8B，半导体裸片20通过导电粘合层50结合到导电基底101的上表面101u。图案化绝缘层70b限定用于接收半导体裸片20的通孔。图案化绝缘层70b通过层压技术设置以覆盖导电基底101和102以及导电粘合层50的一部分。
绝缘层70b'设置成覆盖半导体裸片20和导电基底101、102。导电层42a'设置在绝缘层70b'的上表面701上。导电层42a'的材料例如是铜或其它金属、或金属合金或其他导电材料。绝缘层70b、70b'的材料可以是例如聚丙烯树脂或其它合适的材料。
参考图8C，通过层压技术，在绝缘层70b、70b'上的导电基底101、102和半导体裸片20上形成保护层70。保护层70的一部分在层压期间熔化。导电层42a'连接到导电基底101和102以及半导体裸片20。在一个或多个实施例中，导电层42a'包括铝或铜中的一种或多种或其合金(例如AlCu)。
参考图8D，可以通过涂覆、溅射、电镀或其它合适的技术选择地在导电层42a'上形成第二导电层。
参考图8E，通过蚀刻形成互连结构40和42。互连结构42电连接到半导体裸片20的上表面201上的垫。互连结构40电连接到导电基底102。互连结构40和42的材料例如是铜或其它金属、或金属合金或其它导电材料。
参考图8F，绝缘层72设置在保护层70的上表面701上并且覆盖互连结构40和42。绝缘层72的材料可以是聚丙烯树脂；然而，也可以另外地或替代地使用其它绝缘材料。
参考图8G，在所示的实施例中，通过锯切或蚀刻技术分离两个半导体器件封装8。
图9A～图9F示出了制造图5的半导体器件封装9的方法。
参考图9A，提供至少一个半导体裸片20。至少一个导电粘合层50设置在半导体裸片20的表面202上。导电粘合层50可以是例如导电凝胶或环氧树脂膜(与导电材料混合的环氧树脂)。半导体裸片20通过粘合层50附接到导电层43。导电层43包括上表面431和与上表面431相对的表面432。导电层43的材料例如是铜或其他金属、或金属合金或其它导电材料。保护层70覆盖半导体裸片20和导电层43。导电层42a设置在保护层70上方。通过保护层70和导电层42a形成通孔301和通孔303。绝缘层70a嵌入在导电层43中。绝缘层70a的材料可以是例如聚丙烯树脂或其它合适的材料。
参考图9B，导电层42a'通过涂覆、溅射、电镀或其它合适的技术形成在导电层42上及通孔301和通孔303中。在一个或多个实施例中，导电层42a'包括铝或铜中的一种或多种、或其合金(例如AlCu)。
参考图9C，通过蚀刻形成多个互连结构42和43。互连结构42电连接到半导体裸片20的上表面201上的垫。互连结构43电连接到互连结构42和半导体裸片20的表面202。互连结构42和43的材料是例如铜或其他金属、或金属合金或其它导电材料。
参考图9D，绝缘层72设置在保护层70的上表面701上并覆盖互连结构42。绝缘层72的材料可以是聚丙烯树脂；然而，也可以另外地或替代地使用其它绝缘材料。至少一个导电垫62形成在互连结构43上。导电焊盘62的材料可以是例如铜或其它金属、或金属合金或其它导电材料。
参考图9E，在导电垫62上形成至少一个导电连接件60(例如，焊球)。
参考图9F，在所示的实施例中，通过锯切或蚀刻技术分离两个半导体器件封装9。
图10A示出了根据图6A的一实施例的导电基底101'的横截面图，其中导电基底101'
代替图6A中的导电基底101。图10A的导电基座101'类似于图6A中的导电基座101，除了从图10A的导电基座101的表面101u限定的通孔38以外。
图10B示出了根据图10A的一实施例的导电基底101'的顶视图。在该实施例中，每个通孔38的至少一个角被平滑化。
图11A示出了根据一实施例的导电基底101”的横截面图，其中导电基座101”替图6A中的导电基座101。图11A的导电基座101”类似于图6A的导电基底101，除了从导电基底101”的表面101u限定通孔38以外，并且省略了通孔36。
图11B示出了根据图11A的一实施例的导电基底101”的顶视图。在该实施例中，每个通孔38的至少一个角被平滑化。
图12A示出了根据一实施例的导电基座101”'的横截面图，其中导电基座101”'代替图6A中的导电基座101。图12A的导电基座101”'类似于图6A的导电基底101，除了从导电基底101”'的表面101u限定通孔38以外，并且省略了通孔36。
图12B示出了根据图12A的一实施例的导电基底101”'的顶视图。
图13A示出了根据图6B的一实施例的导电基底101””的顶视图，其中导电基座101””代替图6B中的导电基座101。在此实施例中，导电基座101””类似于图6A的导电基底101，除了导电基底101””包括通孔39以外。
图13B示出了根据图13A沿着A-A线的一实施例的导电基底101””的横截面图。可以看出，图13A中的导电基底101””的横截面图基本上类似于图1中的导电基座101的横截面图。
图13C示出了根据图13A沿着B-B线的一实施例的导电基底101””的横截面图。在该实施例中，导电基座101””的部分被通孔39分离。通孔39的至少一个角被平滑。
图13D是根据本发明沿着图13A的B-B线分離後的一实施例的半导体器件封装1”的横截面图。半导体器件封装1”包括导电基底101””、半导体裸片20、导电粘合层50、保护层70、绝缘层72和74、互连结构40、42和44、导电垫62和导电连接60。
半导体器件封装1”如图13D所示且沿着图13A的B-B线基本上类似于图1A的半导体器件封装1。然而，如图13D所示，突出部80被省略。在此实施例中，保护层70的材料在层压保护层70期间也填充通孔39。因此，在保护层70层压之后，保护层70的一部分将接触绝缘层72和74。
如本文中所使用，词语“近似地”、“大体上”、“实质的”及“约”用以描述及说明小变化。当与事件或情形结合使用时，所述词语可指事件或情形明确发生的情况及事件或情形极近似于发生的情况。举例来说，当结合数值使用时，所述词语可指小于或等于彼数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。因此，关于两个值的术语“大致相等”可以指两个值在0.9和1.1之间的范围内的比例。
另外，有时在本文中按范围格式呈现量、比率及其它数值。应理解，此类范围格式是为便利及简洁起见而使用，且应灵活地理解为不仅包含明确指定为范围极限的数值，且还包含涵盖于彼范围内的所有个别数值或子范围，就如同明确指定每一数值及子范围一般。
如果两个表面之间的位移不大于0.5μm、不大于1μm、不大于5μm、不大于10μm或不大于15μm，则两个表面或侧面可以被认为是对准的微米。
尽管已参考本发明的特定实施例描述并说明本发明，但这些描述及说明并不限制本发明。所属领域的技术人员应理解，在不脱离如由所附权利要求书界定的本发明的真实精神及范畴的情况下，可作出各种改变且可用等效物取代。说明可不一定按比例绘制。归因于工艺及容限，本发明中的艺术再现与实际装置之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书及图式视为说明性而非限制性的。可作出修改，以使特定情形、材料、物质组成、方法或工艺适应于本发明的目标、精神及范畴。所有所述修改均意欲处于此处随附的权利要求书的范畴内。尽管已参看按特定次序执行的特定操作描述本文中所揭示的方法，但应理解，在不脱离本发明的教示的情况下，可组合、再分或重新定序这些操作以形成等效方法。因此，除非本文中具体指示，否则操作的次序及分组并非对本发明的限制。

Claims (20)

1.一种半导体器件封装，其包括：
一导电基底，其包括侧壁，从所述导电基底的第一表面限定的空腔，所述空腔具有底表面和深度；
设置在所述空腔的所述底表面上的半导体裸片，所述半导体裸片具有第一表面和与所述第一表面相对的第二表面，所述半导体裸片的所述第二表面接合到所述空腔的所述底表面；及
第一绝缘材料，其覆盖所述导电基底的所述侧壁且延伸至所述导电基底的底表面。
2.根据权利要求1所述的半导体器件封装，其中所述导电基底的至少一个角被平滑化。
3.根据权利要求1所述的半导体器件封装，其进一步包括第二绝缘材料(74)，其设置在所述导电基底的所述底表面上并与所述第一绝缘材料(70)接触。
4.根据权利要求1所述的半导体器件封装，其中所述半导体裸片的所述第一表面及所述导电基底的所述第一表面之间的距离约为所述空腔的所述深度的20％。
5.根据权利要求1所述的半导体器件封装，其中限定所述空腔的侧壁的所述导电基底的一部分进一步限定开口。
6.根据权利要求1所述的半导体器件封装，其中所述导电基底包括阶梯结构，其中所述阶梯结构填充有所述第一绝缘材料。
7.根据权利要求1所述的半导体器件封装，其中所述导电基底包括一或多个突起。
8.根据权利要求1所述的半导体器件封装，所述第一绝缘层进一步覆盖所述导电基底的所述底表面的一部分。
9.根据权利要求1所述的半导体器件封装，其进一步包括在所述半导体裸片的所述第二表面和所述空腔的所述底表面之间的导电粘合层，其中所述导电粘合层与限定所述空腔的侧壁的所述导电基底的一部分接触。
10.根据权利要求1所述的半导体器件封装，其进一步包括设置在所述半导体裸片上方的第二导电基底；且第二半导体裸片与所述第二导电基底接合。
11.根据权利要求1所述的半导体器件封装，其中所述半导体裸片的所述第一表面低于所述导电基底的所述第一表面。
12.根据权利要求2所述的半导体器件封装，其中所述第一绝缘材料围绕所述导电基底的所述至少一个角。
13.一种半导体器件封装，其包括：
一导电基底，其包括：
侧壁；
第一表面和与所述第一表面相对的第二表面；和
从所述导电基底的所述第一表面限定的空腔，所述空腔具有底表面、侧壁和深度；和
半导体裸片，其设置在所述空腔的所述底表面上并具有第一厚度；
其中所述导电基底的至少一个角被平滑化。
14.根据权利要求13所述的半导体器件封装，其进一步包括在所述半导体裸片和所述空腔的所述底表面之间的导电粘合层，所述导电粘合层具有第二厚度；
其中所述第一厚度和所述第二厚度的总和小于所述空腔的所述深度。
15.根据权利要求13所述的半导体器件封装，其中限定所述空腔的所述侧壁的所述导电基底的一部分进一步限定开口。
16.根据权利要求13所述的半导体器件封装，其进一步包括第一绝缘材料，其中所述导电基底包括阶梯结构，其中所述阶梯结构填充有第一绝缘材料。
17.根据权利要求16所述的半导体器件封装，其进一步包括设置在所述第一绝缘材料上方的焊料掩模层。
18.根据权利要求13所述的半导体器件封装，其中所述导电基底包括一或多个突起。
19.根据权利要求13所述的半导体器件封装，其进一步包括设置在所述半导体裸片上方的第二导电基底，且第二半导体裸片与所述第二导电基底接合。
20.根据权利要求13所述的半导体器件封装，其进一步包括第一绝缘材料，其中所述第一绝缘材料围绕所述导电基底的所述至少一个角。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10083888B2 (en) * 2015-11-19 2018-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package
EP3449502B1 (en) 2016-04-26 2021-06-30 Linear Technology LLC Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US9947552B2 (en) * 2016-04-29 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
FR3070093B1 (fr) * 2017-08-14 2019-09-06 Safran Dispositif de distribution electrique dote de condensateurs enterres.
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US10573618B1 (en) * 2018-07-31 2020-02-25 Delta Electronics, Inc. Package structures and methods for fabricating the same
DE102018128109A1 (de) * 2018-11-09 2020-05-14 Infineon Technologies Ag Ein clip mit einem diebefestigungsabschnitt, der konfiguriert ist, um das entfernen von hohlräumen beim löten zu fördern
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
CN111372369B (zh) * 2018-12-25 2023-07-07 奥特斯科技(重庆)有限公司 具有部件屏蔽的部件承载件及其制造方法
EP3866187A1 (en) * 2020-02-12 2021-08-18 Infineon Technologies Austria AG A semiconductor device comprising an embedded semiconductor die and a method for fabricating the same
TWI704668B (zh) * 2020-02-25 2020-09-11 典琦科技股份有限公司 晶粒封裝結構的製造方法
CN113571431A (zh) * 2020-04-29 2021-10-29 典琦科技股份有限公司 晶粒封装结构的制造方法
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
JP2022048118A (ja) 2020-09-14 2022-03-25 エスティーマイクロエレクトロニクス エス．アール．エル． 信頼性及び検査能力を改善したパッケージ化半導体装置及びその製造方法
CN116387169B (zh) * 2023-06-05 2023-09-05 甬矽半导体(宁波)有限公司 封装方法和封装结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4456641A (en) * 1980-10-01 1984-06-26 Narumi China Corporation Ceramic substrate for semiconductor package
US20090194856A1 (en) * 2008-02-06 2009-08-06 Gomez Jocel P Molded package assembly
US20090250795A1 (en) * 2008-04-08 2009-10-08 Freescale Semiconductor, Inc. Leadframe for packaged electronic device with enhanced mold locking capability
CN102208391A (zh) * 2010-03-31 2011-10-05 飞思卡尔半导体公司 具有凹陷的单元片接合区域的引线框
CN102244057A (zh) * 2011-03-15 2011-11-16 日月光半导体制造股份有限公司 半导体封装及其制造方法
US20160099207A1 (en) * 2014-10-07 2016-04-07 Infineon Technologies Austria Ag Electronic Module Comprising a Plurality of Encapsulation Layers and a Method for Producing It

Family Cites Families (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131863U (zh) * 1973-03-10 1974-11-13
US4472333A (en) * 1980-10-01 1984-09-18 Narumi China Corporation Ceramic substrate for semiconductor package and method of manufacture
US5258647A (en) * 1989-07-03 1993-11-02 General Electric Company Electronic systems disposed in a high force environment
US5095360A (en) * 1990-10-10 1992-03-10 Kyocera America, Inc. Ceramic chip-resistant chamfered integrated circuit package
US5282756A (en) * 1992-12-11 1994-02-01 General Electric Company Electrical lamp base and socket assembly
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
CA2140199A1 (en) * 1995-01-13 1996-07-14 Ranjith Divigalpitiya Method for controlling the electrical arcing of the x-ray detector plate
US5764484A (en) * 1996-11-15 1998-06-09 Olin Corporation Ground ring for a metal electronic package
US6323065B1 (en) * 1997-05-07 2001-11-27 Signetics Methods for manufacturing ball grid array assembly semiconductor packages
US6831352B1 (en) * 1998-10-22 2004-12-14 Azimuth Industrial Company, Inc. Semiconductor package for high frequency performance
US6246111B1 (en) * 2000-01-25 2001-06-12 Siliconware Precision Industries Co., Ltd. Universal lead frame type of quad flat non-lead package of semiconductor
JP3467454B2 (ja) * 2000-06-05 2003-11-17 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US6709898B1 (en) * 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6544812B1 (en) * 2000-11-06 2003-04-08 St Assembly Test Service Ltd. Single unit automated assembly of flex enhanced ball grid array packages
US6661083B2 (en) * 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
US20020190353A1 (en) * 2001-06-19 2002-12-19 Jyh-Sheng Pan Plastic package structure for communication component
TW554500B (en) * 2002-07-09 2003-09-21 Via Tech Inc Flip-chip package structure and the processing method thereof
DE10238523B4 (de) * 2002-08-22 2014-10-02 Epcos Ag Verkapseltes elektronisches Bauelement und Verfahren zur Herstellung
US6847102B2 (en) * 2002-11-08 2005-01-25 Freescale Semiconductor, Inc. Low profile semiconductor device having improved heat dissipation
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
US6833619B1 (en) * 2003-04-28 2004-12-21 Amkor Technology, Inc. Thin profile semiconductor package which reduces warpage and damage during laser markings
TW200425427A (en) * 2003-05-02 2004-11-16 Siliconware Precision Industries Co Ltd Leadframe-based non-leaded semiconductor package and method of fabricating the same
TWI246761B (en) * 2003-05-14 2006-01-01 Siliconware Precision Industries Co Ltd Semiconductor package with build-up layers formed on chip and fabrication method of the semiconductor package
KR100513799B1 (ko) * 2003-06-30 2005-09-13 주식회사 하이닉스반도체 트렌치형 소자분리막을 구비한 반도체 소자의 제조 방법
TWI257693B (en) * 2003-08-25 2006-07-01 Advanced Semiconductor Eng Leadless package
KR20050083322A (ko) * 2004-02-23 2005-08-26 삼성테크윈 주식회사 반도체 패키지용 리이드 프레임과 이의 제조방법
JP4417150B2 (ja) * 2004-03-23 2010-02-17 株式会社ルネサステクノロジ 半導体装置
US7208344B2 (en) * 2004-03-31 2007-04-24 Aptos Corporation Wafer level mounting frame for ball grid array packaging, and method of making and using the same
JP4361826B2 (ja) * 2004-04-20 2009-11-11 新光電気工業株式会社 半導体装置
US7411289B1 (en) * 2004-06-14 2008-08-12 Asat Ltd. Integrated circuit package with partially exposed contact pads and process for fabricating the same
US7235877B2 (en) * 2004-09-23 2007-06-26 International Rectifier Corporation Redistributed solder pads using etched lead frame
TWI249833B (en) * 2004-10-06 2006-02-21 Airoha Tech Corp Active device base, leadframe utilizing the base, and fabrication method of the leadframe
TWI245388B (en) * 2005-01-06 2005-12-11 Phoenix Prec Technology Corp Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same
US8093694B2 (en) * 2005-02-14 2012-01-10 Stats Chippac Ltd. Method of manufacturing non-leaded integrated circuit package system having etched differential height lead structures
JP4659488B2 (ja) * 2005-03-02 2011-03-30 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
KR20080027920A (ko) * 2005-07-08 2008-03-28 엔엑스피 비 브이 반도체 디바이스
US7339278B2 (en) * 2005-09-29 2008-03-04 United Test And Assembly Center Ltd. Cavity chip package
US8163604B2 (en) * 2005-10-13 2012-04-24 Stats Chippac Ltd. Integrated circuit package system using etched leadframe
US7256481B2 (en) * 2005-11-30 2007-08-14 Texas Instruments Incorporated Leadframes for improved moisture reliability and enhanced solderability of semiconductor devices
KR100739988B1 (ko) * 2006-06-28 2007-07-16 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
US20080116564A1 (en) * 2006-11-21 2008-05-22 Advanced Chip Engineering Technology Inc. Wafer level package with die receiving cavity and method of the same
US7927920B2 (en) * 2007-02-15 2011-04-19 Headway Technologies, Inc. Method of manufacturing electronic component package, and wafer and substructure used for manufacturing electronic component package
KR100891330B1 (ko) * 2007-02-21 2009-03-31 삼성전자주식회사 반도체 패키지 장치와, 반도체 패키지의 제조방법과,반도체 패키지 장치를 갖는 카드 장치 및 반도체 패키지장치를 갖는 카드 장치의 제조 방법
JP2008258541A (ja) * 2007-04-09 2008-10-23 Nec Electronics Corp 半導体装置及びその製造方法
US7759777B2 (en) * 2007-04-16 2010-07-20 Infineon Technologies Ag Semiconductor module
KR101194842B1 (ko) * 2007-09-06 2012-10-25 삼성전자주식회사 반도체 패키지가 삽입된 인쇄회로기판
US7838974B2 (en) * 2007-09-13 2010-11-23 National Semiconductor Corporation Intergrated circuit packaging with improved die bonding
JP5108496B2 (ja) * 2007-12-26 2012-12-26 三洋電機株式会社 回路基板およびその製造方法、回路装置およびその製造方法
US7955893B2 (en) * 2008-01-31 2011-06-07 Alpha & Omega Semiconductor, Ltd Wafer level chip scale package and process of manufacture
JP5224845B2 (ja) * 2008-02-18 2013-07-03 新光電気工業株式会社 半導体装置の製造方法及び半導体装置
KR101493866B1 (ko) * 2008-02-28 2015-02-16 페어차일드코리아반도체 주식회사 전력 소자 패키지 및 그 제조 방법
EP2110884B1 (en) * 2008-04-15 2013-05-29 Sub10 Systems Limited Surface-mountable antenna with waveguide connector function, communication system, adaptor and arrangement comprising the antenna device
US7863096B2 (en) * 2008-07-17 2011-01-04 Fairchild Semiconductor Corporation Embedded die package and process flow using a pre-molded carrier
KR101486420B1 (ko) * 2008-07-25 2015-01-26 삼성전자주식회사 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법
US7836586B2 (en) * 2008-08-21 2010-11-23 National Semiconductor Corporation Thin foil semiconductor package
JP5107839B2 (ja) * 2008-09-10 2012-12-26 ルネサスエレクトロニクス株式会社 半導体装置
WO2010041630A1 (ja) * 2008-10-10 2010-04-15 日本電気株式会社 半導体装置及びその製造方法
JP4634497B2 (ja) * 2008-11-25 2011-02-16 三菱電機株式会社 電力用半導体モジュール
US8119454B2 (en) * 2008-12-08 2012-02-21 Stmicroelectronics Asia Pacific Pte Ltd. Manufacturing fan-out wafer level packaging
US20100148357A1 (en) * 2008-12-16 2010-06-17 Freescale Semiconductor, Inc. Method of packaging integrated circuit dies with thermal dissipation capability
JP2010219489A (ja) * 2009-02-20 2010-09-30 Toshiba Corp 半導体装置およびその製造方法
US9070662B2 (en) * 2009-03-05 2015-06-30 Volterra Semiconductor Corporation Chip-scale packaging with protective heat spreader
JP2010245417A (ja) * 2009-04-09 2010-10-28 Renesas Electronics Corp 半導体装置およびその製造方法
US8124447B2 (en) * 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
DE102009023514A1 (de) * 2009-05-30 2010-12-02 Heinz Prof. Dr.-Ing. Lindenmeier Antenne für zirkulare Polarisation mit einer leitenden Grundfläche
TWI405306B (zh) * 2009-07-23 2013-08-11 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體
JP2011044452A (ja) * 2009-08-19 2011-03-03 Denso Corp 電子装置およびその製造方法
US8362598B2 (en) * 2009-08-26 2013-01-29 Amkor Technology Inc Semiconductor device with electromagnetic interference shielding
US8435837B2 (en) * 2009-12-15 2013-05-07 Silicon Storage Technology, Inc. Panel based lead frame packaging method and device
US8541877B2 (en) * 2009-12-16 2013-09-24 Chia-Lun Tsai Electronic device package and method for fabricating the same
US8193620B2 (en) * 2010-02-17 2012-06-05 Analog Devices, Inc. Integrated circuit package with enlarged die paddle
US8431438B2 (en) * 2010-04-06 2013-04-30 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US9006871B2 (en) * 2010-05-12 2015-04-14 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US8349658B2 (en) * 2010-05-26 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe
US8847376B2 (en) * 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
JP5500002B2 (ja) * 2010-08-31 2014-05-21 株式会社デンソー 炭化珪素半導体装置の製造方法
US20120119342A1 (en) * 2010-11-11 2012-05-17 Mediatek Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
JP5636265B2 (ja) * 2010-11-15 2014-12-03 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8343808B2 (en) * 2010-11-22 2013-01-01 Bridge Semiconductor Corporation Method of making stackable semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
JP5514134B2 (ja) * 2011-02-14 2014-06-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
EP3664167B1 (en) * 2011-03-25 2021-07-07 Samsung Electronics Co., Ltd. Light emitting diode
US20130127044A1 (en) * 2011-11-22 2013-05-23 Texas Instruments Incorporated Micro surface mount device packaging
US8598694B2 (en) * 2011-11-22 2013-12-03 Infineon Technologies Ag Chip-package having a cavity and a manufacturing method thereof
CN104025292B (zh) * 2011-12-22 2018-03-09 松下知识产权经营株式会社 半导体封装、其制造方法及模具、半导体封装的输入输出端子
US8951847B2 (en) * 2012-01-18 2015-02-10 Intersil Americas LLC Package leadframe for dual side assembly
US20130187284A1 (en) * 2012-01-24 2013-07-25 Broadcom Corporation Low Cost and High Performance Flip Chip Package
US8980687B2 (en) * 2012-02-08 2015-03-17 Infineon Technologies Ag Semiconductor device and method of manufacturing thereof
US8916968B2 (en) * 2012-03-27 2014-12-23 Infineon Technologies Ag Multichip power semiconductor device
US8815647B2 (en) * 2012-09-04 2014-08-26 Infineon Technologies Ag Chip package and a method for manufacturing a chip package
US9171794B2 (en) * 2012-10-09 2015-10-27 Mc10, Inc. Embedding thin chips in polymer
JP6100612B2 (ja) * 2013-05-27 2017-03-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9012268B2 (en) * 2013-06-28 2015-04-21 Stmicroelectronics, Inc. Leadless packages and method of manufacturing same
JP6210818B2 (ja) * 2013-09-30 2017-10-11 三菱電機株式会社 半導体装置およびその製造方法
US9437516B2 (en) * 2014-01-07 2016-09-06 Infineon Technologies Austria Ag Chip-embedded packages with backside die connection
KR101557942B1 (ko) * 2014-01-08 2015-10-12 주식회사 루멘스 발광 소자 패키지 및 발광 소자 패키지의 제조 방법
US10192849B2 (en) * 2014-02-10 2019-01-29 Infineon Technologies Ag Semiconductor modules with semiconductor dies bonded to a metal foil
KR20150108685A (ko) * 2014-03-18 2015-09-30 삼성전기주식회사 반도체모듈 패키지 및 그 제조 방법
US9431319B2 (en) * 2014-08-01 2016-08-30 Linear Technology Corporation Exposed, solderable heat spreader for integrated circuit packages
US9368435B2 (en) * 2014-09-23 2016-06-14 Infineon Technologies Ag Electronic component
DE102014114982B4 (de) * 2014-10-15 2023-01-26 Infineon Technologies Ag Verfahren zum Bilden einer Chip-Baugruppe
US9418920B2 (en) * 2015-01-05 2016-08-16 Stmicroelectronics Pte Ltd Integrated circuit (IC) package with thick die pad functioning as a heat sink
JP2016174021A (ja) * 2015-03-16 2016-09-29 株式会社東芝 半導体装置
CN104779220A (zh) * 2015-03-27 2015-07-15 矽力杰半导体技术(杭州)有限公司 一种芯片封装结构及其制造方法
DE102015104996B4 (de) * 2015-03-31 2020-06-18 Infineon Technologies Austria Ag Halbleitervorrichtungen mit Steuer- und Lastleitungen von entgegengesetzter Richtung
US9589871B2 (en) * 2015-04-13 2017-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US10008472B2 (en) * 2015-06-29 2018-06-26 Stmicroelectronics, Inc. Method for making semiconductor device with sidewall recess and related devices
JP6603538B2 (ja) * 2015-10-23 2019-11-06 新光電気工業株式会社 リードフレーム及びその製造方法
CN106684076B (zh) * 2015-11-05 2019-09-06 台达电子企业管理（上海）有限公司 封装结构及其制造方法
US10083888B2 (en) * 2015-11-19 2018-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package
DE112016005323T5 (de) * 2015-11-20 2018-09-13 Idex Asa Auf einem starren Substrat getragener elektronischer Sensor
US10707157B2 (en) * 2016-06-15 2020-07-07 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP6716363B2 (ja) * 2016-06-28 2020-07-01 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及びその製造方法
JP6823955B2 (ja) * 2016-07-14 2021-02-03 ローム株式会社 電子部品およびその製造方法
US10615105B2 (en) * 2017-10-20 2020-04-07 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN107993991A (zh) * 2017-12-20 2018-05-04 合肥矽迈微电子科技有限公司 一种芯片封装结构及其制造方法
US11328984B2 (en) * 2017-12-29 2022-05-10 Texas Instruments Incorporated Multi-die integrated circuit packages and methods of manufacturing the same
EP3531446B1 (en) * 2018-02-23 2024-04-03 Infineon Technologies Austria AG Semiconductor module, electronic component and method of manufacturing a semiconductor module
DE102018207955B4 (de) * 2018-05-22 2023-05-17 Schweizer Electronic Ag Leiterplattenmodul mit integriertem leistungselektronischen Metall-Keramik-Modul sowie Verfahren zu dessen Herstellung

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4456641A (en) * 1980-10-01 1984-06-26 Narumi China Corporation Ceramic substrate for semiconductor package
US20090194856A1 (en) * 2008-02-06 2009-08-06 Gomez Jocel P Molded package assembly
US20090250795A1 (en) * 2008-04-08 2009-10-08 Freescale Semiconductor, Inc. Leadframe for packaged electronic device with enhanced mold locking capability
CN102208391A (zh) * 2010-03-31 2011-10-05 飞思卡尔半导体公司 具有凹陷的单元片接合区域的引线框
CN102244057A (zh) * 2011-03-15 2011-11-16 日月光半导体制造股份有限公司 半导体封装及其制造方法
US20160099207A1 (en) * 2014-10-07 2016-04-07 Infineon Technologies Austria Ag Electronic Module Comprising a Plurality of Encapsulation Layers and a Method for Producing It

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