CN102244057A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

Info

Publication number
CN102244057A
CN102244057A CN2011102128491A CN201110212849A CN102244057A CN 102244057 A CN102244057 A CN 102244057A CN 2011102128491 A CN2011102128491 A CN 2011102128491A CN 201110212849 A CN201110212849 A CN 201110212849A CN 102244057 A CN102244057 A CN 102244057A
Authority
CN
China
Prior art keywords
semiconductor packages
opening
conductive carrier
dielectric layer
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011102128491A
Other languages
English (en)
Other versions
CN102244057B (zh
Inventor
凯.史提芬.艾希格
伯恩.卡尔.阿培得
李明锦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Publication of CN102244057A publication Critical patent/CN102244057A/zh
Application granted granted Critical
Publication of CN102244057B publication Critical patent/CN102244057B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/24246—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/24247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82106—Forming a build-up interconnect by subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开一种半导体封装及其制造方法。该半导体封装包括导电载体、设置于邻近于所述导电载体的上表面的芯片、图案化导电层以及包封所述芯片的介电材料。所述介电材料定义出开口，所述图案化导电层穿过所述开口电连接到所述导电载体的所述上表面。所述导电载体具有侧表面，所述侧表面包括邻近于所述导电载体的所述上表面的第一部分和邻近于所述导电载体的下表面的第二部分，其中所述第二部分相对于所述导电载体的所述下表面而向内倾斜。

Description

半导体封装及其制造方法
技术领域
本发明涉及半导体装置封装(semiconductor device package)及其制造方法。更特定来说，本发明涉及具有嵌入式芯片(embedded die)的半导体装置封装及其制造方法。
背景技术
在由较小尺寸的需求和增强处理速度的需求中的至少一部分地驱动下，半导体装置已变得越来越复杂。同时，存在使包括这些半导体装置的许多电子产品进一步微型化的需求。半导体装置通常经封装，且随后可被安装在包括电路的基底(例如，电路板)上。半导体装置也可安装在金属层上，以获得增强的热传导性(thermal dissipation)。这导致空间被半导体装置封装和基底及/或金属层所占据，且导致基底及/或金属层上的表面区域被半导体装置封装所占据。另外，以单独的工艺来执行封装、板制造和组装可能导致额外的成本。减少基底及/或金属层上由半导体装置所占据的空间以及简化和组合应用于半导体装置和基底及/或金属层的封装、板制造和组装工艺将会是令人满意的。
针对此背景技术，需要开发本文所描述的半导体封装和相关方法。
发明内容
本发明的一个方面涉及一种半导体封装。在实施例中，所述半导体封装包括：(1)导电载体，其具有上表面、下表面和侧表面，所述侧表面包括邻近于导电载体的上表面的第一部分和邻近于导电载体的下表面的第二部分，其中第二倾斜部分相对于导电载体的下表面而向内倾斜；(2)芯片，设置于邻近于导电载体的上表面；(3)图案化导电层；以及(4)介电材料，其包封芯片，其中所述介电材料定义出开口，图案化导电层穿过所述开口电连接到导电载体的上表面。
在另一实施例中，所述半导体封装包括：(1)导电载体，其具有上表面、下表面和侧表面，所述侧表面包括邻近于导电载体的上表面的第一部分、邻近于导电载体的下表面的第二部分以及位于第一部分与第二部分之间的接面处的顶点；(2)芯片，设置于邻近于导电载体的上表面；以及(3)介电材料，其具有实质上垂直的侧表面且实质上包封第一部分。第二部分具有相对于所述实质上垂直的侧表面的角偏移。
本发明的另一方面涉及一种形成半导体封装的方法。在实施例中，所述方法包括：(1)提供具有上表面和下表面的金属层；(2)形成从金属层的上表面延伸且部分地穿过金属层的第一开口；(3)将芯片设置于邻近于金属层的上表面；(4)用具有背对芯片的上表面的介电层包封芯片和金属层的上表面的至少一部分，所述介电层实质上填入第一开口；(5)在介电层中形成第二开口，所述第二开口暴露出金属层的上表面；(6)邻近于介电层的上表面而形成图案化导电层；(7)形成延伸穿过第二开口的导电孔(conductivevia)，所述导电孔将图案化导电层电连接到金属层；以及(8)形成从金属层的下表面延伸且部分地穿过金属层的第三开口，第三开口与第一开口实质上对准。
本发明的其它方面和实施例也同样被预期。上述概要和以下详细描述无意将本发明限于任一特定实施例，而是仅用于描述本发明的一些实施例。
附图说明本发明的实施例，且连同描述内容一起用以阐释本发明一些实施例的原理。现在将详细参考本发明的一些实施例，其实例在附图中得以说明。只要可能，便在附图和描述内容中使用相同参考标号来表示相同或相似特征。
附图说明
图1说明根据本发明实施例的半导体封装的剖面图。
图2说明根据本发明实施例的半导体封装的剖面图。
图3说明根据本发明实施例的半导体封装的剖面图。
图4说明根据本发明实施例的半导体封装的剖面图。
图5说明根据本发明实施例的半导体封装的剖面图。
图6A到图6P说明根据本发明实施例的制造半导体封装的方法。
附图标记说明
100、200、300、401、500：半导体封装
102：芯片                     103：有源表面
104：背面                     105：导电载体
106、124、402：上表面         107：高度
108、126、406：下表面         109：深度
110、111、128：侧表面         112：凹槽
113：厚度                     114、403：壁
115：凹槽底部                 116：芯片贴附层
120、410、413、414：介电层
121、123、132、150、152、412：开口
122：纤维                     130：图案化导电层
133、134：接触区              135、136、137：表面处理层
140：介电层                   142、144：导电孔
154：顶点                     160：侧壁
164：下半部分                 166：上半部分
170：第一平面                 172：下半部
174：上半部                   400：基体基底带
404：导电片                   420、430：虚线
具体实施方式
首先参见图1，其说明根据本发明实施例的半导体封装100的剖面图。半导体封装100可包括有源组件(例如，芯片102)、无源组件或有源和无源组件两者。在图1中，半导体封装100包括芯片102、导电载体(conductivebase)105、介电层(dielectric layer)120和图案化导电层(patterned conductivelayer)130。芯片102具有有源表面103、与有源表面103相对的背面104以及侧表面(lateral surface)111。导电载体105具有上表面106、与上表面106相对的下表面108以及侧表面110。在实施例中，芯片102的背面104设置于邻近于导电载体105的上表面106。介电层120具有上表面124、下表面126以及从上表面124延伸到下表面126的侧表面128。介电层120实质上包封导电载体105的上表面106以及芯片102的侧表面111和有源表面103，以提供机械稳定性以及对氧化、潮湿和其它环境条件的防护。图案化导电层130设置于邻近于介电层120的上表面124。介电层120位于图案化导电层130与芯片102的有源表面103之间，且位于图案化导电层130与导电载体105的上表面106之间。
导电载体105可由金属及/或金属合金(例如铜及/或铜合金)形成。导电载体105可为铜箔(copper foil)，且可称为引线框(1eadframe)。在实施例中，导电载体105的厚度113可在约100μm到约300μm的范围内，例如约200μm到约300μm的范围内。在实施例中，导电载体105的厚度113近似为250μm。
在实施例中，导电载体105定义出具有壁114的凹槽112。芯片102可至少部分地设置于凹槽112中，使得芯片102的背面104邻近于凹槽112的凹槽底部115。凹槽底部115可包括于导电载体105的上表面106中。介电层120可实质上填入凹槽的位于芯片102与壁114之间的部分。在实施例中，芯片102的高度107不大于凹槽112的深度109。凹槽112的深度109可等于或大于芯片102的高度107。或者，凹槽112的深度109可小于芯片102的高度107。在实施例中，凹槽112的深度109可在芯片102的高度107的约50％到芯片102的高度107的约100％的范围内，例如高度107的约60％到约80％的范围内、高度107的约80％到约100％的范围内和高度107的约90％到约100％的范围内。芯片102至少部分地放置于凹槽112中可允许介电层120的厚度减小，且因此允许封装100的厚度减小。另外，在实施例中，如果芯片102的高度107小于或近似等于凹槽112的深度109，那么介电层120无需预先形成以产生对应于芯片102的开口(见图6D)。或者，如果凹槽112的深度109小于芯片102的高度107，那么可能需要在介电层120中预先形成开口，但由于凹槽112的缘故，此开口可小于图6C中所示的开口。
凹槽112的壁114可倾斜。在实施例中，壁114可弯曲。凹槽112的壁114可倾斜以使得凹槽底部115处的壁114比凹槽底部115上方的壁114更靠近芯片102。
芯片102可通过芯片贴附层(die attach layer)116贴附到导电载体105。在实施例中，芯片贴附层116可由金属及/或金属合金形成，以促进从芯片102到导电载体105的热传导。在此实施例中，形成芯片贴附层116的过程可称为共晶接合(eutectic bonding)。这对于热传导性尤其重要的半导体封装(例如嵌入式芯片电力封装等)来说可为令人满意的。芯片贴附层116可由例如锡与铅的合金等软焊料(soft solder)形成。或者，芯片贴附层116可由例如金与锡的合金等硬焊料形成。由硬焊料形成芯片贴附层116可为令人满意的，因为这可使得芯片贴附层116具有较均匀的厚度和较好的热传导性能。在其它实施例中，芯片102可通过例如环氧树脂(epoxy)等芯片贴附膜贴附到导电载体105。
在实施例中，介电层120可由聚合或非聚合的介电材料形成。举例来说，介电层120可由(但不限于)液晶聚合物(liquid crystal polymer，LCP)、双马来酰亚胺三嗪(bismaleimide triazine，BT)、预浸渍体(prepreg，PP)、味的素堆积膜(Ajinomoto Build-up Film，ABF)、环氧树脂以及聚酰亚胺(polyimide)中的至少一者形成。对于某些实施方案，介电层120可由可光成像(photoimageable)或感光(photoactive)的介电材料形成。另外，介电层120可为以例如玻璃纤维或Kevlar纤维(芳族聚酸胺纤维)等纤维122加强以强化介电层120的树脂材料。在介电层120中使用的可由纤维加强的树脂材料的实例包括ABF、BT、预浸渍体、聚酰亚胺、LCP、环氧树脂和其它树脂材料。如以下在图6B和图6D所示，纤维290最初在介电层614内沿着大体水平的平面定向，之后进行层压以形成介电层214。如图2所示，纤维122在介电层120的层压之后重定向，其中邻近于芯片102的部分被沿着芯片102的垂直延伸方向推动，且远离导电载体105。
如图1中所说明，介电层120经形成而定义出开口121和123。开口121可从图案化导电层130延伸到导电载体105的上表面106，且可暴露出上表面106。图案化导电层130可穿过开口121电连接到导电载体105。开口123可暴露出芯片102的有源表面103的若干部分。开口121和123可具有若干形状中的任一者。这些形状包括柱体形状，例如圆形柱体形状、椭圆形柱体形状、正方形柱体形状或矩形柱体形状，或包括非柱体形状，例如圆锥形、漏斗形或另一锥形形状。这些开口的侧向边界可弯曲或带粗糙纹理也同样被预期。
如图1中所说明，导电孔(conductive via)142可设置于每一开口121中，且导电孔144可设置于每一开口123中。举例来说，导电孔142和144可为经电镀导电柱(plated conductive post)。或者，导电孔142可实质上填入开口121，且/或导电孔144可实质上填入开口123。虽然图1中绘示一个导电孔142，但预期封装100可含有一个以上导电孔142。导电孔142可从图案化导电层130延伸到导电载体105。导电孔142可将图案化导电层130中所包括的接触区(contact)133电连接到导电载体105。在实施例中，接触区133可为用于导电载体105的接地接触区。导电孔144可从图案化导电层130延伸到芯片102。导电孔144可将接触区134电连接到芯片102的有源表面103。在实施例中，接触区134可包括用于芯片102的电力、信号及/或接地接触区。
在实施例中，图1所示的图案化导电层和导电孔中的每一者可由金属、金属合金、其中散布有金属或金属合金的基质(matrix)或另一合适的导电材料形成。举例来说，图1所示的图案化导电层和导电孔中的每一者可由铝、铜、钛或其组合所形成。图1所示的图案化导电层和导电孔可由相同的导电材料或不同的导电材料所形成。
如图1中所说明，由图案化导电层130定义出的开口132可实质上由介电层140填入。介电层140可由例如干式膜可成像焊罩(solder mask)等焊罩(焊料光致抗蚀剂)或另一类型的可图案化层或介电层形成。开口132以及介电层140中暴露出电接触区133和134的开口可具有若干形状中的任一者。这些形状包括柱体形状，例如圆形柱体形状、椭圆形柱体形状、正方形柱体形状或矩形柱体形状，或包括非柱体形状，例如圆锥形、漏斗形或另一锥形形状。这些开口的侧向边界可弯曲或带粗糙纹理也同样被预期。
如图1中所说明，接触区133和134可分别电镀有表面处理层(surfacefinish layer)135和136。在实施例中，表面处理层135和136可采用类似于图1所示的形成图案化导电层和导电孔的方式而形成，如先前所述。或者，表面处理层135和136可采用不同方式形成。举例来说，表面处理层135和136可由锡、镍和金或包括锡或包括镍与金的合金中的至少一者形成。表面处理层135和136可由相同的导电材料或不同的导电材料形成。
图2说明根据本发明实施例的半导体封装200的剖面图。半导体封装200在许多方面类似于参见图1而描述的半导体封装100，因此在此处论述半导体封装200的不同的观点。在此实施例中，芯片102可设置于邻近于导电基座105的上表面106，而不设置于凹槽中。特定来说，凹槽112(见图1)不形成于导电基座105中。因为芯片102设置于邻近于导电基座105的上表面106，而不设置于凹槽中，所以介电层120经预先形成以产生对应于芯片102的开口(见图6B)。
参见图1，在实施例中，导电基座105定义出开口150和152。开口150和152也可称为凹槽150和152及/或凹口150和152。开口150和152各自部分地延伸穿过导电基座105，其中开口150从导电基座105的上表面106延伸，且开口152从导电基座105的下表面108延伸。每一开口150可与开口152中的对应一者相对定位。在实施例中，开口150可实质上由介电层120填入。每一开口152可暴露出介电层120。或者，在实施例中，每一开口150可通过导电基座105的一部分(未图示)与开口152中的对应一者分离。
如图1中所说明，侧表面110可包括下半部分164和上半部分166。下半部分164可倾斜，且可在导电基座105的下表面108与上半部分166之间延伸。在实施例中，下半部分164可相对于下表面108而向内倾斜。侧表面110的上半部分166可在导电基座105的上表面106与下半部分164之间延伸。下半部分164对应于开口152的边界。侧表面110的上半部分166也可倾斜，且可实质上由介电层120覆盖。在实施例中，侧表面110可包括位于下半部分164与上半部分166之间的接面处的顶点(apex)154。
在实施例中，封装100包括侧壁160。侧壁160可包括介电层120的侧表面128。在实施例中，侧壁160还可包括导电基座105的侧表面110的可从下半部分164延伸到上半部分166的部分(未图示)。侧表面110的此部分与侧表面128可实质上共面。
参见图1，下半部分164及/或上半部分166可具有实质上凹入的轮廓。下半部分164及/或上半部分166可向内朝向芯片102圆化及/或弯曲。在实施例中，下半部分164及/或上半部分166可包括呈例如粗糙体(asperity)等小峰的形式的表面不均匀性或粗糙性，其可从芯片102向外圆化及/或弯曲。
如图1中所说明，下表面108和侧表面110的下半部分164可电镀有表面处理层(电镀层)137。在实施例中，表面处理层137可类似于图1所示的图案化导电层和导电孔而形成，如先前所述。或者，表面处理层137可以不同方式形成。举例来说，表面处理层137可由锡、镍和金或包括锡或包括镍与金的合金中的至少一者形成。
在实施例中，介电层120的侧表面128可定义出第一平面170。侧表面128可实质上垂直。下半部分164可具有相对于侧表面128的角偏移。下半部分164可包括邻近于导电载体105的下表面108的下半部172，以及在下半部172与上半部分166之间延伸的上半部174。下半部172可相对于第一平面170倾斜少于或近似等于15度，例如在约5度到约10度的范围内，和约10度到约15度的范围内。
在实施例中，下半部分164可包括位于侧表面110中的凹口。举例来说，下半部172可相对于上半部174凹进。凹口可环绕封装100。
图3说明根据本发明实施例的半导体封装300的剖面图。半导体封装300在许多方面类似于参见图1而描述的半导体封装100，因此此处论述半导体封装300的不同的观点。在此实施例中，侧表面110的上半部分166可实质上与介电层120的侧表面128共面。上半部分166可被暴露出来，使得介电层120或表面处理层137均不覆盖上半部分166。表面处理层137可覆盖下半部分164，而不覆盖上半部分166。或者，上半部分166可由表面处理层137覆盖。
图4说明根据本发明实施例的半导体封装401的剖面图。半导体封装401在许多方面类似于参见图1而描述的半导体封装100，因此此处论述半导体封装401的不同的观点。不同于图1的实施例，整个侧表面110可实质上与介电层120的侧表面128共面。表面处理层137可覆盖下表面108，而不覆盖侧表面110。或者，表面处理层137可覆盖下表面108以及导电基座105的侧表面110。
或者，侧表面110可包括具有与图1所示的上半部166类似的特性的上半部(未图示)。特定来说，所述上半部(未图示)可倾斜，且可实质上由介电层120覆盖。在此实施例中，侧表面110的其余部分可实质上与介电层120的侧表面128共面。表面处理层137可覆盖下表面108以及侧表面110的其余部分。或者，表面处理层137可覆盖下表面108，而不覆盖侧表面110的任一部分。
图5说明根据本发明实施例的半导体封装500的剖面图。半导体封装500在许多方面类似于参见图4而描述的半导体封装401，因此此处论述半导体封装500的不同的观点。在此实施例中，介电层120可具有比导电基座105的侧向范围大的侧向范围，使得介电层120的侧表面128不与侧表面110共面，且不与表面处理层137共面。
或者，侧表面110可包括具有与图1所示的上半部166相似特性的上半部(未图示)。特定来说，所述上半部(未图示)可倾斜，且可实质上由介电层120覆盖。在此实施例中，介电层120可具有比导电基座105的侧向范围大的侧向范围，使得介电层120的侧表面128不与侧表面110的任一部分共面，且不与表面处理层137共面。
图6A到图6P说明根据本发明实施例的制造半导体封装的方法。为了便于呈现，参见图1的封装100及/或图2的封装200来描述以下制造操作。然而，可类似地进行制造操作以形成可具有与封装100和200不同的内部结构的其它半导体封装是可被预期的，例如图3中所说明的封装300。进行制造操作以形成基底带也同样被预期，其包括连接的半导体封装阵列，所述半导体封装各自可对应于例如图1到图3中所说明的那些封装的封装。图6A到图6L中描述方法的第一实施例。图6A到图6I和随后图6M到图6N中描述方法的第二实施例。方法的第二实施例可用以形成图4中所说明的封装401。图6A到图6I和随后图6O到图6P中描述方法的第三实施例。方法的第三实施例可用以形成图5中所说明的封装500。如图6L、图6N、图6O和图6P中所描述，连接的半导体封装阵列可单一化为例如图1到图5中所说明的封装的个别封装。
首先参见图6A，提供基体基底带400。基体基底带400具有与先前针对图1和图2的导电载体105所描述类似的材料组成和厚度特性。在实施例中，开口150可形成于基体基底带400中，且从基体基底带400的上表面402部分地延伸穿过基体基底带400。每一开口150可充当对准标记以促进单一化(见图6K和图6L)。在实施例中，开口150是通过化学蚀刻而形成。开口150的壁403可倾斜。在实施例中，壁403可弯曲。壁403远离实质上垂直于上表面402的平面的倾斜程度可取决于用于蚀刻的化学溶液。或者，开口150可不形成于基体基底带400中。
或者，如图6B中所说明，凹槽112可形成于基体基底带400中。除开口150之外还可形成凹槽112。半导体装置502可至少部分地设置于凹槽504中。在实施例中，凹槽112是通过化学蚀刻而形成。凹槽112的壁114可倾斜。在实施例中，壁114可弯曲。壁114远离实质上垂直于上表面402的平面的倾斜程度可取决于用于蚀刻的化学溶液。
如图6C中所说明，将芯片102设置于邻近于基体基底带400。芯片贴附层116可设置于芯片102与基体基底带400之间。如先前参见图1所描述，芯片102可通过共晶接合贴附到基体基底带400。在共晶接合的实施例中，芯片贴附层116可由例如锡与铅的合金等软焊料形成。在此实施例中，由锡与铅的合金形成的金属丝可熔化，且随后被分配于基体基底带400上将贴附芯片102的位置处。在共晶接合的另一实施例中，芯片贴附层116可由例如金与锡的合金等硬焊料形成。金与锡的合金可设置于半导体芯片上，使得金与锡的合金贴附到芯片102。随后可通过使金与锡的合金熔化将芯片102直接贴附到基体基底带400，而无需单独的分配步骤。或者，如果不使用共晶接合，那么芯片贴附层116可由例如环氧树脂等黏合剂材料形成。可将黏合剂材料分配于基体基底带400上将贴附芯片102的位置处。
参见图6C，提供介电层410，其中介电层410预先形成有一组开口412，且开口412的位置对应于半导体装置102的位置。介电层410具有类似于先前参见图1而描述的介电层120的特性。在实施例中，介电层410包括纤维加强的树脂材料，例如预浸渍体材料，其包括纤维122以强化介电层410。如图6C所示，纤维122最初沿介电层410内的大体水平平面定向。
或者，如图6D中所说明，芯片102至少部分地设置于凹槽112中，且邻近于凹槽底部115。芯片贴附层116可设置于芯片102与凹槽底部115之间。以类似于先前参见图6C而描述的方式，芯片102可通过共晶接合或通过使用例如环氧树脂等黏合剂来贴附到凹槽底部115。而且，提供介电层414。如先前参见图1而描述，在实施例中，介电层414无需预先形成有对应于半导体装置102的位置的任何开口。这简化了形成图1的封装100和其中芯片102设置于凹槽112中的类似封装的工艺。介电层414具有与先前参见图1而描述的介电层120类似的特性。在实施例中，介电层414包括纤维加强的树脂材料，例如预浸渍体材料，其包括纤维122以强化介电层414。如图6C所示，纤维122最初沿介电层414内的大体水平的平面定向。
如所说明，图6E到图6L接在图6C之后以形成图2的封装200，但所属领域的技术人员将了解，类似的步骤可接在图6D之后以形成图1的封装100及/或图3的封装300。
如图6E中所说明，将介电层410设置于邻近于基体基底带400，且覆盖芯片102。介电层410可实质上填入开口150。如先前参见图1而描述，对于包括凹槽112的实施例，介电层414(见图6D)也可实质上填入凹槽112的尚未由芯片102填入的剩余部分。介电层410可使导电片404与芯片102分离。图6E所示的介电层410包括图2的介电层120。在实施例中，纤维122在介电层410的层压之后经重定向，其中邻近于芯片102的部分被沿着芯片102的垂直延伸方向推动，且远离基底带400。例如铜箔等导电片404可设置于邻近于介电层410，以形成(例如)覆盖芯片102的涂覆有树脂的铜层。介电层410可具有单个树脂层，或可包括由树脂制成的第一子层和由加强树脂制成的第二子层，加强树脂例如为以玻璃纤维及/或Kevlar纤维加强的树脂。
在另一实施例中，介电层410可由预浸渍体材料形成，且可将导电片404设置于邻近于介电层410。可将预浸渍体材料设置于邻近于基体基底带400，且可经预先形成以在芯片102的位置处定义出开口(见图6C)。预浸渍体材料可由一个预浸渍体层或由两个或两个以上预浸渍体层形成。或者，介电层410可包括预浸渍体子层与树脂子层的组合，且可将导电片404设置于邻近于介电层410。可将预浸渍体子层设置于邻近于基体基底带400，且可预先形成以在芯片102的位置处定义出开口(见图6C)。可将树脂子层设置于邻近于预浸渍体子层，且也可邻近于基体基底带400而设置于由预浸渍体子层定义出的开口内(见图6C)。
在另一实施例中，介电层410可由例如包封剂材料等环氧树脂模制化合物形成，且可将导电片404设置于邻近于介电层410。
在实施例中，介电层410可层压于基体基底带400上。或者，可使用例如注射模制等若干模制技术中的任一者来形成介电层410。一但实施，便(例如)通过使温度降低到低于模制材料的熔点来使模制材料硬化或固化，进而形成介电层410。或者，可使用例如印刷、旋涂或喷涂等若干涂覆技术中的任一者来形成介电层410。
在实施例中，导电片404可贴附到介电层410，之后可将介电层410设置于邻近于基体基底带400。在实施例中，可将已贴附有导电片404的介电层410设置于邻近于基体基底带400。
如图6F中所说明，形成包括开口121和123的开口。开口121延伸穿过导电片404和介电层410，以暴露出导电载体105的上表面106。开口123延伸穿过导电片404和介电层410，以暴露出半导体装置202的有源表面103。可通过激光钻孔、机械钻孔或此项技术中已知的其它合适方法来形成开口121和123。
如图6G中所说明，开口121和123以导电材料填入以形成导电孔142和144。可使用例如无电电镀及/或电解电镀等若干涂覆技术中的任一者来形成导电孔142和144。
如图6H中所说明，包括接触区133和134的图案化导电层130邻近于介电层410而形成。可通过加成工艺、半加成工艺或削去工艺(subtractiveprocess)形成图案化导电层130。图案化导电层130可包括一组焊垫(pad)和一组迹线(trace)，其可在常见工艺操作中实质上同时形成。
如图6I中所说明，将介电层413设置于邻近于介电层410和基体基底带400。图6I中所示的介电层413包括图1的介电层140。介电层413可采用类似于先前参见图6E针对介电层410描述的方式形成。
如图6J中所说明，开口152形成于基体基底带400中。在实施例中，开口152可从下表面406延伸穿过基体基底带400，使得开口152暴露出介电层120。或者，开口152可从基体基底带400的下表面406部分地延伸穿过基体基底带400，且可通过导电载体105的一部分(未图示)与开口152中的对应一者分离。此部分(未图示)的厚度可显著小于基体基底带400的其它部分的厚度，这可促进单一化。
如先前参见图1所描述，每一开口150可与开口152中的对应一者相对定位，使得每一开口150实质上与开口152中的对应一者对准。每一开口150可具有实质上与开口152中的对应一者相同的宽度，或可具有与开口152中的对应一者不同的宽度。
在实施例中，开口152是通过化学蚀刻而形成。如先前参见图1而描述，开口152的壁的下半部分164可实质上凹入。下半部分164可朝芯片102向内圆化及/或弯曲。下半部分164远离平面170的倾斜程度(见图1)可取决于用于蚀刻的化学溶液。
如图6K中所说明，表面处理层135和136分别邻近于接触窗133和134而形成。表面处理层137邻近于导电载体105的下表面406以及侧表面110的下半部分164而形成。可使用无电镍/浸渍金(immersion gold)工艺来形成表面处理层135、136和137。
如图6L中所说明，接着可沿着虚线420执行单一化以获得例如图2的封装200等个别封装。单一化产生切割裂缝，其将基体基底带400细分为具有包括下半部分164的侧表面110的导电载体105(见图1到图3)。
参见图1，如果使用小尺寸刀及/或锯来进行参见图6L而描述的单一化及/或穿孔步骤，那么可在对应于开口150的位置处执行单一化。当使用较小的且成本较低的锯时，在此位置执行单一化可为令人满意的，因为导电载体105在此位置处的厚度由于开口150而减小。在此实施例中，由于沿着虚线420的单一化而产生的切割裂缝延伸穿过介电层120、第一开口150和对应的第二开口152。在此位置处，由于单一化而产生的封装100的侧壁160是包括介电层120的侧表面128的实质上共面表面。侧壁160可实质上垂直于介电层120的上表面124。在此实施例中，侧表面110的下半部分164对应于开口152的边界。侧表面110的上半部分166可实质上由介电层120覆盖。
参见图3，如果使用大尺寸刀及/或锯来进行参见图6L而描述的单一化及/或穿孔步骤(punch step)，那么可在从开口150移开(displace)的位置处执行单一化。在此实施例中，由于沿着虚线420的单一化而产生的切割裂缝延伸穿过介电层120、导电载体105的上半部分166以及上半部分166下方的第二开口152。在此位置处，由于单一化而产生的封装100的侧壁160是包括介电层120的侧表面128以及导电载体105的侧表面110的上半部分166的实质上共面表面。侧壁160可实质上垂直于介电层120的上表面124。在此实施例中，侧表面110的上半部分166可从介电层120的侧表面128延伸到侧表面110的下半部分164。不同于图1的实施例，单一化可从开口150移开。在实施例中，在单一化之后，表面处理层137可邻近于侧表面110的上半部分166而形成。
参见图1和图6L，在替代实施例中，由于沿着虚线420的单一化及/或穿孔而产生的切割裂缝可延伸穿过介电层120、第一开口150和第一开口150下方的对应第二开口152。在此实施例中，切割裂缝还延伸穿过导电载体105的使第一开口150与对应第二开口152分离的部分(未图示)。在单一化之后，侧表面110的半部分164可在导电载体105的下表面406与介电层120的侧表面128之间延伸。
如图6M中所说明，在替代实施例中，表面处理层135和136分别邻近于接触区133和134而形成。表面处理层137邻近于基体基底带400的下表面406而形成。可使用无电镍/浸渍金工艺来形成表面处理层135、136和137。如先前参见图6A所描述，开口150可形成于基体基底带400中，或可不形成于基体基底带400中。
如图6N中所说明，接着可沿着虚线420执行单一化以获得例如图4的封装401等个别封装。单一化产生切割裂缝，其将基体基底带400细分为具有侧表面110的导电载体105(见图4)。在此实施例中，侧表面110可实质上与介电层120的侧表面128共面。或者，侧表面110的一部分(未图示)可实质上由介电层120覆盖，且侧表面110的剩余部分可实质上与侧表面128共面。因为基体基底带400的单一化是在导电载体105的下表面406上形成表面处理层137之后发生，所以侧表面110未由表面处理层137覆盖。在实施例中，在单一化之后，可邻近于侧表面110的至少一部分而形成表面处理层137。
如图6O中所说明，在另一替代实施例中，可沿着虚线430执行基体基底带400的单一化。单一化产生将基体基底带400细分为具有侧表面110的导电载体105(见图5)的切割裂缝。可用适合于切割金属材料的第一锯来执行此单一化。在此实施例中，侧表面110可实质上为平面的。或者，侧表面110的一部分(未图示)可相对于由虚线430定义出的平面倾斜，且可实质上由介电层120覆盖。
如图6P中所说明，表面处理层135和136分别邻近于接触区133和134而形成。表面处理层137可邻近于下表面406而形成。在实施例中，表面处理层137也可邻近于导电载体105的侧表面110的至少一部分而形成。可使用无电镍/浸渍金工艺来形成表面处理层135、136和137。
接着可沿着虚线420执行介电层120的单一化以获得例如图5的封装500等个别封装。可用适合于切割介电材料的第二锯来执行此单一化，其中第二锯不同于参见图6O的使基体基底带400单一化的第一锯。如果基体基底带400中存在开口150，那么切割裂缝可与开口150对准。
虽然已参见本发明的具体实施例描述和说明了本发明，但这些描述和说明不限制本发明。所属领域的技术人员应理解，在不脱离如由权利要求界定的本发明的真实精神和范围的情况下，可进行各种改变且等同特征可被取代。附图可能不一定按比例绘制，且制造公差可能会导致偏离本文所阐述的工艺概念。可能存在未具体说明的本发明的其它实施例。因此，说明书和附图应视为说明性的而不是限制性的。另外，为了清楚，说明本发明实施例的图式可着重于某些主要特性特征。此外，可进行修改以使特定情形、材料、物质组成、方法或工艺适于本发明的目标、精神和范围。所有这些修改在权利要求的范围内。特定来说，虽然已参考以特定次序执行的特定操作而描述了本文所揭示的方法，但可理解的是，在不脱离本发明教导的情况下，这些操作可经组合、细分或重排序以形成等同方法。因此，除非本文具体指示，否则操作的次序和分组不是对本发明的限制。

Claims (20)

1.一种半导体封装，包括：
导电载体，其具有上表面、下表面和侧表面，所述侧表面包括邻近于所述导电载体的所述上表面的第一部分和邻近于所述导电载体的所述下表面的第二部分，其中所述第二部分相对于所述导电载体的所述下表面而向内倾斜；
芯片，设置于邻近于所述导电载体的所述上表面；
图案化导电层；以及
介电材料，其包封所述芯片，其中所述介电材料定义出开口，所述图案化导电层穿过所述开口电连接到所述导电载体的所述上表面。
2.如权利要求1所述的半导体封装，其中所述第一部分倾斜。
3.如权利要求2所述的半导体封装，其中所述介电材料具有侧表面，且包封所述第一部分。
4.如权利要求1所述的半导体封装，其中所述导电载体的所述侧表面包括位于所述第一部分与所述第二部分之间的接面处的顶点。
5.如权利要求1所述的半导体封装，其中：
所述介电材料具有侧表面；以及
所述第一部分与所述介电材料的所述侧表面共面。
6.如权利要求1所述的半导体封装，其中：
所述介电材料具有定义出平面的侧表面；
所述第二部分包括邻近于所述导电载体的所述下表面的下半部，以及在所述下半部与所述导电载体的所述侧表面的所述第一部分之间延伸的上半部；以及
所述第二部分的所述下半部相对于所述平面倾斜少于15度。
7.如权利要求6所述的半导体封装，其中所述第二部分包括环绕所述半导体封装的凹口。
8.如权利要求1所述的半导体封装，其还包括耦合到所述导电载体的所述下表面的电镀层。
9.如权利要求8所述的半导体封装，其中所述电镀层更耦合到所述第二部分。
10.如权利要求1所述的半导体封装，其中所述导电载体定义出包括于所述导电载体的所述上表面中的具有凹槽底部的凹槽。
11.一种半导体封装，包括：
导电载体，其具有上表面、下表面和侧表面，所述侧表面包括邻近于所述导电载体的所述上表面的第一部分、邻近于所述导电载体的所述下表面的第二部分，以及位于所述第一部分与所述第二部分之间的接面处的顶点；
芯片，设置于邻近于所述导电载体的所述上表面；以及
介电材料，其具有垂直的侧表面，且包封所述第一部分，
其中所述第二部分具有相对于所述垂直的侧表面的角偏移。
12.如权利要求11所述的半导体封装，其中：
所述导电载体定义出包括于所述导电载体的所述上表面中的凹槽；
所述凹槽具有第一高度；
所述芯片具有第二高度；以及
所述第一高度至少与所述第二高度一样大。
13.如权利要求11所述的半导体封装，其中所述第二部分包括凹口。
14.如权利要求13所述的半导体封装，其中所述凹口环绕所述半导体封装。
15.如权利要求11所述的半导体封装，其还包括耦合到所述导电载体的所述下表面的电镀层。
16.一种形成半导体封装的方法，包括：
提供具有上表面和下表面的金属层；
形成从所述金属层的所述上表面延伸且部分地穿过所述金属层的第一开口；
将芯片设置于邻近于所述金属层的所述上表面；
用具有背对所述芯片的上表面的介电层包封所述芯片和所述金属层的所述上表面的至少一部分，所述介电层填入所述第一开口；
在所述介电层中形成第二开口，所述第二开口暴露出所述金属层的所述上表面；
邻近于所述介电层的所述上表面而形成图案化导电层；
形成延伸穿过所述第二开口的导电孔，所述导电孔将所述图案化导电层电连接到所述金属层；以及
形成从所述金属层的所述下表面延伸且部分地穿过所述金属层的第三开口，所述第三开口与所述第一开口对准。
17.如权利要求16所述的形成半导体封装的方法，其中所述第三开口延伸穿过所述金属层以暴露出所述介电层。
18.如权利要求16所述的形成半导体封装的方法，其中所述金属层包括邻近于所述第三开口的倾斜部分，且所述方法还包括形成切割裂缝，所述切割裂缝延伸穿过所述介电层、所述第一开口和所述第三开口，使得所述金属层经细分以形成具有包括所述倾斜部分的侧表面的导电载体。
19.如权利要求18所述的形成半导体封装的方法，其中：
所述介电层具有定义出平面的侧表面；
所述倾斜部分包括邻近于所述导电载体的所述下表面的下半部，以及由所述介电层覆盖的上半部；以及
所述下半部相对于所述平面倾斜少于15度。
20.如权利要求16所述的形成半导体封装的方法，其还包括：
在所述金属层中形成凹槽，所述凹槽具有包括于所述金属层的所述上表面中的具有凹槽底部的凹槽；以及
将所述芯片设置于邻近于所述凹槽底部，其中所述凹槽的第一高度与所述芯片的第二高度至少一样大。
CN201110212849.1A 2011-03-15 2011-07-28 半导体封装及其制造方法 Active CN102244057B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/048,836 2011-03-15
US13/048,836 US8487426B2 (en) 2011-03-15 2011-03-15 Semiconductor package with embedded die and manufacturing methods thereof

Publications (2)

Publication Number Publication Date
CN102244057A true CN102244057A (zh) 2011-11-16
CN102244057B CN102244057B (zh) 2015-06-24

Family

ID=44962022

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110212849.1A Active CN102244057B (zh) 2011-03-15 2011-07-28 半导体封装及其制造方法

Country Status (3)

Country Link
US (1) US8487426B2 (zh)
CN (1) CN102244057B (zh)
TW (1) TWI466202B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579010A (zh) * 2012-08-08 2014-02-12 深南电路有限公司 一种侧壁金属化封装产品的制作方法
CN104835746A (zh) * 2014-02-10 2015-08-12 英飞凌科技股份有限公司 具有被结合到金属箔的半导体管芯的半导体模块
CN105845641A (zh) * 2015-02-02 2016-08-10 英飞凌科技奥地利有限公司 电子组件
CN106971988A (zh) * 2015-12-11 2017-07-21 爱思开海力士有限公司 晶圆级封装件及其制造方法
CN107527890A (zh) * 2016-06-15 2017-12-29 日月光半导体制造股份有限公司 半导体装置封装
CN107799477A (zh) * 2015-11-19 2018-03-13 日月光半导体制造股份有限公司 半导体器件封装

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8431438B2 (en) * 2010-04-06 2013-04-30 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US9064879B2 (en) * 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8936966B2 (en) 2012-02-08 2015-01-20 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US9799627B2 (en) * 2012-01-19 2017-10-24 Semiconductor Components Industries, Llc Semiconductor package structure and method
US9485870B2 (en) * 2013-01-04 2016-11-01 Apple Inc. Methods for transparent encapsulation and selective encapsulation
AT514074B1 (de) * 2013-04-02 2014-10-15 Austria Tech & System Tech Verfahren zum Herstellen eines Leiterplattenelements
US9449890B1 (en) * 2013-05-10 2016-09-20 Amkor Technology, Inc. Methods for temporary bussing of semiconductor package substrates
WO2015043495A1 (zh) * 2013-09-30 2015-04-02 南通富士通微电子股份有限公司 晶圆封装结构和封装方法
JP6711229B2 (ja) * 2016-09-30 2020-06-17 日亜化学工業株式会社 プリント基板の製造方法及び発光装置の製造方法
KR101982058B1 (ko) * 2017-12-06 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
DE112017008325T5 (de) 2017-12-29 2020-09-03 Intel Corporation Mikroelektronische anordnungen
US10763203B1 (en) * 2019-02-08 2020-09-01 Nxp B.V. Conductive trace design for smart card
US11908764B2 (en) * 2021-08-31 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including a circuit substrate having a cavity and a floor plate embedded in a dielectric material and a semiconductor die disposed in the cavity

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1267396A (zh) * 1997-08-19 2000-09-20 株式会社日立制作所 多芯片组件构造体及其制造方法
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
CN1645600A (zh) * 2003-12-24 2005-07-27 三洋电机株式会社 混合集成电路装置及其制造方法
CN101026148A (zh) * 2007-03-27 2007-08-29 日月光半导体制造股份有限公司 光电芯片的多芯片增层封装构造及其制造方法

Family Cites Families (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131863U (zh) 1973-03-10 1974-11-13
US4866501A (en) 1985-12-16 1989-09-12 American Telephone And Telegraph Company At&T Bell Laboratories Wafer scale integration
US5111278A (en) 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
US5151769A (en) * 1991-04-04 1992-09-29 General Electric Company Optically patterned RF shield for an integrated circuit chip for analog and/or digital operation at microwave frequencies
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US6400573B1 (en) 1993-02-09 2002-06-04 Texas Instruments Incorporated Multi-chip integrated circuit module
US5306670A (en) 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
TW256013B (en) 1994-03-18 1995-09-01 Hitachi Seisakusyo Kk Installation board
US5578869A (en) * 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US5945741A (en) 1995-11-21 1999-08-31 Sony Corporation Semiconductor chip housing having a reinforcing plate
WO2004100260A1 (ja) 1995-05-19 2004-11-18 Kouta Noda 高密度多層プリント配線版、マルチチップキャリア及び半導体パッケージ
US5745984A (en) 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
JP2755252B2 (ja) * 1996-05-30 1998-05-20 日本電気株式会社 半導体装置用パッケージ及び半導体装置
WO1998015977A1 (fr) * 1996-10-10 1998-04-16 Samsung Electronics Co., Ltd. Circuit integre hybride, de grande puissance et a frequences micro-ondes
US6110608A (en) 1996-12-10 2000-08-29 The Furukawa Electric Co., Ltd. Lead material for electronic part, lead and semiconductor device using the same
JP3982895B2 (ja) * 1997-04-09 2007-09-26 三井化学株式会社 金属ベース半導体回路基板
US6278181B1 (en) 1999-06-28 2001-08-21 Advanced Micro Devices, Inc. Stacked multi-chip modules using C4 interconnect technology having improved thermal management
EP1139705B1 (en) 1999-09-02 2006-11-22 Ibiden Co., Ltd. Printed wiring board and method of producing the same
JP4251421B2 (ja) 2000-01-13 2009-04-08 新光電気工業株式会社 半導体装置の製造方法
JP3813402B2 (ja) 2000-01-31 2006-08-23 新光電気工業株式会社 半導体装置の製造方法
JP2002009236A (ja) 2000-06-21 2002-01-11 Shinko Electric Ind Co Ltd 多層半導体装置及びその製造方法
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6452258B1 (en) 2000-11-06 2002-09-17 Lucent Technologies Inc. Ultra-thin composite surface finish for electronic packaging
TW457663B (en) * 2000-11-08 2001-10-01 Advanced Semiconductor Eng Substrate structure of heat spreader and its package
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
EP2315510A3 (en) 2001-06-05 2012-05-02 Dai Nippon Printing Co., Ltd. Wiring board provided with passive element
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
TW550997B (en) 2001-10-18 2003-09-01 Matsushita Electric Ind Co Ltd Module with built-in components and the manufacturing method thereof
JP3910045B2 (ja) 2001-11-05 2007-04-25 シャープ株式会社 電子部品内装配線板の製造方法
FI115285B (fi) 2002-01-31 2005-03-31 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja kontaktin muodostamiseksi
FI119215B (fi) 2002-01-31 2008-08-29 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli
US6680529B2 (en) 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7485489B2 (en) 2002-06-19 2009-02-03 Bjoersell Sten Electronics circuit manufacture
TW546800B (en) 2002-06-27 2003-08-11 Via Tech Inc Integrated moduled board embedded with IC chip and passive device and its manufacturing method
TW554500B (en) 2002-07-09 2003-09-21 Via Tech Inc Flip-chip package structure and the processing method thereof
KR100593049B1 (ko) 2002-08-09 2006-06-28 가시오게산키 가부시키가이샤 반도체 장치 및 그 제조방법
DE10238523B4 (de) * 2002-08-22 2014-10-02 Epcos Ag Verkapseltes elektronisches Bauelement und Verfahren zur Herstellung
FI119583B (fi) 2003-02-26 2008-12-31 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
TW588445B (en) 2003-03-25 2004-05-21 Advanced Semiconductor Eng Bumpless chip package
US7141884B2 (en) 2003-07-03 2006-11-28 Matsushita Electric Industrial Co., Ltd. Module with a built-in semiconductor and method for producing the same
US6876544B2 (en) 2003-07-16 2005-04-05 Kingpak Technology Inc. Image sensor module and method for manufacturing the same
FI20031201A (fi) 2003-08-26 2005-02-27 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
JP2004007006A (ja) 2003-09-16 2004-01-08 Kyocera Corp 多層配線基板
US7459781B2 (en) 2003-12-03 2008-12-02 Wen-Kun Yang Fan out type wafer level package structure and method of the same
JP3945483B2 (ja) 2004-01-27 2007-07-18 カシオ計算機株式会社 半導体装置の製造方法
JP4093186B2 (ja) 2004-01-27 2008-06-04 カシオ計算機株式会社 半導体装置の製造方法
TWI236323B (en) 2004-02-16 2005-07-11 Subtron Technology Co Ltd Fabricating process of circuit board with embedded passive component
JP4361826B2 (ja) 2004-04-20 2009-11-11 新光電気工業株式会社 半導体装置
FI20040592A (fi) 2004-04-27 2005-10-28 Imbera Electronics Oy Lämmön johtaminen upotetusta komponentista
TWI250596B (en) 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
JP2006041438A (ja) 2004-07-30 2006-02-09 Shinko Electric Ind Co Ltd 半導体チップ内蔵基板及びその製造方法
TWI253700B (en) 2004-08-03 2006-04-21 Ind Tech Res Inst Image sensor module packaging structure and method thereof
JP4473674B2 (ja) * 2004-08-06 2010-06-02 パナソニック株式会社 半導体パッケージ及びその製造方法
TWI246383B (en) 2004-09-21 2005-12-21 Advanced Semiconductor Eng A manufacturing method of a multi-layer circuit board with embedded passive components
FI20041525A (fi) 2004-11-26 2006-03-17 Imbera Electronics Oy Elektroniikkamoduuli ja menetelmä sen valmistamiseksi
TWI283553B (en) 2005-04-21 2007-07-01 Ind Tech Res Inst Thermal enhanced low profile package structure and method for fabricating the same
GB2441265B (en) 2005-06-16 2012-01-11 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
US8335084B2 (en) 2005-08-01 2012-12-18 Georgia Tech Research Corporation Embedded actives and discrete passives in a cavity within build-up layers
US7511356B2 (en) 2005-08-31 2009-03-31 Micron Technology, Inc. Voltage-controlled semiconductor inductor and method
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
TWI290349B (en) 2005-12-30 2007-11-21 Advanced Semiconductor Eng Thermally enhanced coreless thin substrate with an embedded chip and method for manufacturing the same
JP5114041B2 (ja) 2006-01-13 2013-01-09 日本シイエムケイ株式会社 半導体素子内蔵プリント配線板及びその製造方法
TWI305479B (en) 2006-02-13 2009-01-11 Advanced Semiconductor Eng Method of fabricating substrate with embedded component therein
FI20060256L (fi) 2006-03-17 2006-03-20 Imbera Electronics Oy Piirilevyn valmistaminen ja komponentin sisältävä piirilevy
US7404251B2 (en) 2006-04-18 2008-07-29 International Business Machines Corporation Manufacture of printed circuit boards with stubless plated through-holes
US7859098B2 (en) 2006-04-19 2010-12-28 Stats Chippac Ltd. Embedded integrated circuit package system
IL175011A (en) 2006-04-20 2011-09-27 Amitech Ltd Coreless cavity substrates for chip packaging and their fabrication
US7338892B2 (en) 2006-06-09 2008-03-04 Advanced Semiconductor Engineering, Inc. Circuit carrier and manufacturing process thereof
US7884464B2 (en) 2006-06-27 2011-02-08 Advanced Chip Engineering Technologies Inc. 3D electronic packaging structure having a conductive support substrate
US20080116564A1 (en) 2006-11-21 2008-05-22 Advanced Chip Engineering Technology Inc. Wafer level package with die receiving cavity and method of the same
US20080136002A1 (en) 2006-12-07 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
US20080136004A1 (en) 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chip package structure and method of forming the same
US7808797B2 (en) 2006-12-11 2010-10-05 Intel Corporation Microelectronic substrate including embedded components and spacer layer and method of forming same
TWI334747B (en) 2006-12-22 2010-12-11 Unimicron Technology Corp Circuit board structure having embedded electronic components
US7687823B2 (en) * 2006-12-26 2010-03-30 Nichia Corporation Light-emitting apparatus and method of producing the same
US8178964B2 (en) 2007-03-30 2012-05-15 Advanced Chip Engineering Technology, Inc. Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same
US8178963B2 (en) 2007-01-03 2012-05-15 Advanced Chip Engineering Technology Inc. Wafer level package with die receiving through-hole and method of the same
US7812434B2 (en) 2007-01-03 2010-10-12 Advanced Chip Engineering Technology Inc Wafer level package with die receiving through-hole and method of the same
US20080174008A1 (en) 2007-01-18 2008-07-24 Wen-Kun Yang Structure of Memory Card and the Method of the Same
US20080197474A1 (en) 2007-02-16 2008-08-21 Advanced Chip Engineering Technology Inc. Semiconductor device package with multi-chips and method of the same
KR100891330B1 (ko) * 2007-02-21 2009-03-31 삼성전자주식회사 반도체 패키지 장치와, 반도체 패키지의 제조방법과,반도체 패키지 장치를 갖는 카드 장치 및 반도체 패키지장치를 갖는 카드 장치의 제조 방법
US20080197469A1 (en) 2007-02-21 2008-08-21 Advanced Chip Engineering Technology Inc. Multi-chips package with reduced structure and method for forming the same
TWI331386B (en) 2007-03-09 2010-10-01 Advanced Semiconductor Eng Substrate process for embedded component
US7525185B2 (en) 2007-03-19 2009-04-28 Advanced Chip Engineering Technology, Inc. Semiconductor device package having multi-chips with side-by-side configuration and method of the same
US20080251908A1 (en) 2007-04-11 2008-10-16 Advanced Chip Engineering Technology Inc. Semiconductor device package having multi-chips with side-by-side configuration and method of the same
US20080258293A1 (en) 2007-04-17 2008-10-23 Advanced Chip Engineering Technology Inc. Semiconductor device package to improve functions of heat sink and ground shield
KR101336569B1 (ko) 2007-05-22 2013-12-03 삼성전자주식회사 증가된 결합 신뢰성을 갖는 반도체 패키지 및 그 제조 방법
JPWO2008155957A1 (ja) 2007-06-19 2010-08-26 株式会社村田製作所 部品内蔵基板の製造方法および部品内蔵基板
KR100907508B1 (ko) 2007-07-31 2009-07-14 (주)웨이브닉스이에스피 패키지 기판 및 그 제조방법
US20090127686A1 (en) 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
US7790576B2 (en) 2007-11-29 2010-09-07 Stats Chippac, Ltd. Semiconductor device and method of forming through hole vias in die extension region around periphery of die
US7838395B2 (en) 2007-12-06 2010-11-23 Stats Chippac, Ltd. Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the same
JP5108496B2 (ja) * 2007-12-26 2012-12-26 三洋電機株式会社 回路基板およびその製造方法、回路装置およびその製造方法
US7851246B2 (en) 2007-12-27 2010-12-14 Stats Chippac, Ltd. Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device
TWI453877B (zh) 2008-11-07 2014-09-21 Advanced Semiconductor Eng 內埋晶片封裝的結構及製程
US20100148357A1 (en) * 2008-12-16 2010-06-17 Freescale Semiconductor, Inc. Method of packaging integrated circuit dies with thermal dissipation capability
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1267396A (zh) * 1997-08-19 2000-09-20 株式会社日立制作所 多芯片组件构造体及其制造方法
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
CN1645600A (zh) * 2003-12-24 2005-07-27 三洋电机株式会社 混合集成电路装置及其制造方法
CN101026148A (zh) * 2007-03-27 2007-08-29 日月光半导体制造股份有限公司 光电芯片的多芯片增层封装构造及其制造方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579010A (zh) * 2012-08-08 2014-02-12 深南电路有限公司 一种侧壁金属化封装产品的制作方法
CN103579010B (zh) * 2012-08-08 2016-12-21 深南电路有限公司 一种侧壁金属化封装产品的制作方法
CN104835746A (zh) * 2014-02-10 2015-08-12 英飞凌科技股份有限公司 具有被结合到金属箔的半导体管芯的半导体模块
CN104835746B (zh) * 2014-02-10 2017-12-15 英飞凌科技股份有限公司 具有被结合到金属箔的半导体管芯的半导体模块
CN105845641A (zh) * 2015-02-02 2016-08-10 英飞凌科技奥地利有限公司 电子组件
CN105845641B (zh) * 2015-02-02 2019-11-12 英飞凌科技奥地利有限公司 电子组件
CN107799477A (zh) * 2015-11-19 2018-03-13 日月光半导体制造股份有限公司 半导体器件封装
CN110600386A (zh) * 2015-11-19 2019-12-20 日月光半导体制造股份有限公司 半导体器件封装
CN110600386B (zh) * 2015-11-19 2022-05-10 日月光半导体制造股份有限公司 半导体器件封装
CN106971988A (zh) * 2015-12-11 2017-07-21 爱思开海力士有限公司 晶圆级封装件及其制造方法
CN106971988B (zh) * 2015-12-11 2019-11-08 爱思开海力士有限公司 晶圆级封装件及其制造方法
CN107527890A (zh) * 2016-06-15 2017-12-29 日月光半导体制造股份有限公司 半导体装置封装

Also Published As

Publication number Publication date
CN102244057B (zh) 2015-06-24
US8487426B2 (en) 2013-07-16
TW201237971A (en) 2012-09-16
US20120235309A1 (en) 2012-09-20
TWI466202B (zh) 2014-12-21

Similar Documents

Publication Publication Date Title
CN102244057A (zh) 半导体封装及其制造方法
US10128214B2 (en) Substrate and the method to fabricate thereof
CN105228341B (zh) 印刷电路板、封装基板及其制造方法
CN101273452B (zh) 半导体器件封装
US11823911B2 (en) Process of package-then-etch three-dimensional package structure electrically connected by plated copper pillars
US8461689B2 (en) Packaging structure having embedded semiconductor element
CN102044520B (zh) 封装载板、封装结构以及封装载板制作工艺
US6522017B2 (en) Wiring board and semiconductor device
CN106165554A (zh) 印刷电路板、封装基板及其制造方法
CN107978583A (zh) 封装结构及其制造方法
KR20110027628A (ko) 전도성 필라를 구비하는 집적회로 패키지 시스템 및 그 제조 방법
CN102884623A (zh) 在介电体上具有端子的微电子封装
CN104428892A (zh) 用于基板核心层的方法和装置
KR101809521B1 (ko) 반도체 패키지 및 그 제조방법
JP2013065869A (ja) 垂直に取り付けることのできるｉｃパッケージを作る方法
US20130122216A1 (en) Structure of embedded-trace substrate and method of manufacturing the same
CN107123601A (zh) 一种高散热器件封装结构和板级制造方法
CN102569101A (zh) 无外引脚封装结构及其制作方法
CN108695269A (zh) 半导体装置封装及其制造方法
KR101944007B1 (ko) 반도체 패키지 및 그 제조방법
KR102647325B1 (ko) 회로기판 및 이를 포함하는 반도체 패키지
CN104396008A (zh) 半导体封装衬底、使用半导体封装衬底的封装系统及用于制造封装系统的方法
US20120264257A1 (en) Mold array process method to prevent exposure of substrate peripheries
CN205488088U (zh) 埋入硅基板扇出型3d封装结构
JP2008198916A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant