CN108695269A - 半导体装置封装及其制造方法 - Google Patents

半导体装置封装及其制造方法 Download PDF

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Publication number
CN108695269A
CN108695269A CN201810233866.5A CN201810233866A CN108695269A CN 108695269 A CN108695269 A CN 108695269A CN 201810233866 A CN201810233866 A CN 201810233866A CN 108695269 A CN108695269 A CN 108695269A
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Prior art keywords
electric contact
main body
installation structure
substrate
package main
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CN201810233866.5A
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CN108695269B (zh
Inventor
洪志明
王盟仁
蔡宗岳
欧任凯
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN202210450188.4A priority Critical patent/CN114758994A/zh
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    • G06—COMPUTING; CALCULATING OR COUNTING
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Abstract

本发明揭示一种表面安装结构，所述表面安装结构包含衬底、传感器、电触点以及封装主体。所述衬底具有第一表面以及与所述第一表面相对的第二表面。所述传感器经安置成邻近于所述衬底的所述第二表面。所述电触点安置在所述衬底的所述第一表面上。所述封装主体覆盖所述衬底的所述第一表面及所述第二表面、所述传感器的部分以及所述电触点的第一部分。

Description

半导体装置封装及其制造方法
相关申请案交叉参考
本申请案主张于2017年4月6日提出申请的美国临时专利申请案第62/482431号的优先权，所述美国临时专利申请案特此以全文引用的方式明确并入本文中。
技术领域
本发明一般来说涉及半导体装置封装，并且涉及扇出球(或凸块)栅格阵列(BGA)封装结构。
背景技术
需要包含具有更高效率、更高性能及更小尺寸的半导体装置封装的电子产品。
BGA封装可用于满足具有较高引线数及较小占用面积的封装需求。BGA封装可为正方形封装，带有从封装底部突出的焊球或凸块阵列形式的端子。这些端子可安装在位于印刷电路板(PCB)表面上的多个垫或其它互连结构上。BGA的迹线可被制造在层压衬底(例如，包含双马来酰亚胺三嗪(BT)的衬底)上或基于聚酰亚胺的薄膜上。因此，可以使用大面积的此衬底或薄膜来布线互连。BGA可提供低接地或功率电感，从而经由到PCB的短电流路径实施接地或电力网。为了增加结构强度，可以实施双面成型的BGA封装。
发明内容
在一些实施例中，表面安装结构包含衬底，传感器，电触点和封装主体。所述衬底具有第一表面以及与所述第一表面相对的第二表面。所述传感器经安置成邻近于所述衬底的所述第二表面。所述电触点安置在所述衬底的所述第一表面上。所述封装主体覆盖所述衬底的所述第一表面及所述第二表面、所述传感器的部分以及所述电触点的第一部分。
在一些实施例中，一种制造表面安装结构的方法包含：(a)提供具有第一表面及与所述第一表面相对的第二表面的衬底；(B)将电触点安置在所述衬底的第一表面上，所述电触点包括第一部分及第二部分；(c)将所述电触点放置在覆盖所述电触点的所述第一部分的带上，所述带暴露所述电触点的所述第二部分；(d)形成覆盖所述衬底的所述第一表面及所述第二表面以及所述电触点的所述第二部分的封装主体；及(e)移除所述电触点的所述第一部分。
附图说明
图1A说明根据本发明的一些实施例的半导体装置封装的横截面图。
图1B说明根据本发明的一些实施例的图1A中的表面安装结构的部分的放大图。
图2A、图2B、图2C及图2D说明根据本发明的一些实施例的制造表面安装结构的方法。
图3A说明根据本发明的一些实施例的表面安装结构的横截面图。
图3B说明根据本发明的一些实施例的图3A中的表面安装结构的部分的放大图。
图4A、图4B、图4C及图4D说明根据本发明的一些实施例的制造表面安装结构的方法。
贯穿图式及详细描述使用共用参考编号来指示相同或类似组件。本发明从结合附图进行的以下详细描述将更容易理解。
具体实施方式
图1A说明根据本发明的一些实施例的表面安装结构1的横截面图。表面安装结构1包含衬底10、传感器11、电子组件12a、12b、封装主体13及电触点14。
衬底10可为例如印刷电路板，例如纸基铜箔层压板，复合铜箔层压板或聚合物浸渍玻璃纤维基铜箔层压板。衬底10可包含互连结构，例如重新分配层(RDL)或接地元件。衬底10具有表面101(也被称作为第一表面)及与表面101相对的表面102(也被称作为第二表面)。
传感器11安置在衬底10内且安置在衬底10的表面102上，邻近所述表面或嵌入于所述表面中。例如，传感器11的至少部分从衬底10的表面102暴露。在一些实施例中，从衬底10的表面102暴露的传感器11的部分与衬底10的表面102基本上共面。在一些实施例中，从衬底10的表面102暴露的传感器11的部分为传感器11的感测区域。在一些实施例中，传感器11可用于例如指纹感测或任何其它光感测目的。
电子部件12a及12b安置在衬底10的表面101上。在一些实施例中，电组件12a可为有源部件，例如集成电路(IC)芯片或裸片。电组件12b可为无源电组件，例如电容器、电阻器、电感器及其组合。电子组件12a、12b中的每一个可电连接到一或多个其它电子组件12a、12b及/或连接到衬底10(例如，连接到RDL)，且电连接可通过覆晶或线接合技术获得。
电触点14安置在衬底的表面101上。电触点14可为表面安装结构1提供外部连接。
封装主体13安置在衬底10的表面101及102上。封装主体13覆盖衬底10的表面101和102。封装主体13覆盖传感器11的暴露部分。封装主体13覆盖电子组件12a。封装主体13覆盖电子部件12b。封装主体13覆盖电触点14的部分。在一些实施例中，封装主体13包含具有填料的环氧树脂，模塑料(例如环氧模塑料或其它模塑料)、聚酰亚胺、酚醛树脂化合物或材料，其中分散有硅酮的材料或其组合。在一些实施例中，封装主体13可取决于设计规格包含透明材料(例如，对于传感器11经配置以进行处理的光，透射率为约80％或更多、透射率为约90％或更多，或透射率为约95％或更多的材料)。在一些实施例中，封装主体13可取决于设计规格包含不透明材料(例如，对于传感器11经配置以进行处理的光，透射率为约20％或更少、透射率为约10％或更少，或透射率为约5％或更少的材料)。在一些实施例中，封装主体13具有基本上平面的表面131(例如，电触点14从其突出)。
参考图1B，所述图说明被虚线正方形A封围的图1A中的表面安装结构1的部分的放大图，电触点14包含两个部分，在本文中被称作为电触点14a及14b。电触点14a及14b可以构成整体式或整体形成的电触点14。电触点14a安置在衬底10的表面101上，且电触点14b安置在电触点14a上。在一些实施例中，电触点14阶段邻近于电触点14a与电触点14b之间的界面的凹部、凹陷或颈部14r。在一些实施例中，一或多个电触点14可环绕或经安置围绕电子组件12a、12b的外围，且可用于扇出或扇入电子组件12a、12b的输入及输出。在一些实施例中，电触点14a、14b为受控塌陷芯片连接(C4)凸块，BGA凸块或平面栅格阵列(LGA)凸块。
封装主体13包封电触点14a的部分。封装主体13暴露电触点14a的部分。封装主体13暴露电触点14b(例如，完全暴露电触点14b)。封装主体13与电触点14a的部分经间隔开一段距离。封装主体13与电触点14b隔开一段距离。封装主体13具有侧壁13r1，所述侧壁界定用以容纳电触点14b及电触点件14a的部分的空间或凹部13r。封装主体13的侧壁13r1与电触点14a的部分间隔开。封装主体13的侧壁13r1与电触点14b间隔开。在封装主体13的侧壁13r1与电触点14a的部分之间存在间隙。在封装主体13的侧壁13r1与电触点14b之间存在间隙。
图2A、图2B、图2C、图2D说明根据本发明的一些实施例的制造表面安装结构的方法的各种阶段。在一些实施例中，图2A、图2B、图2C及图2D中所展示的方法可用于制造图1A中的表面安装结构1。
参考图2A，在载体29上提供包含表面安装结构1'(例如，多个表面安装结构1')的多个表面安装结构。如图1A及图1B所展示，表面安装结构1'类似于表面安装结构1，其间的差异包含表面安装结构1'省略电接点14b且封装主体13'未覆盖衬底10的表面102。
在一些实施例中，图2A中的表面安装结构1'可以通过以下操作形成：(i)提供包含衬底10的衬底条；(ii)通过使用例如表面安装技术(SMT)将电子组件12a、12b及电触点14a分别安装在衬底带的衬底(包括衬底10)上；(iii)通过例如传递成型或压缩成型的成型技术形成封装主体13'以覆盖电子组件12a、12b及电触点14a；(iv)移除封装主体13'的部分以例如通过激光，钻孔或其它合适的工艺暴露电触点14a的部分；(v)将衬底条切割成包含表面安装结构1'的个别表面安装结构；及(vi)将包含表面安装结构1'的表面安装结构安置在载体29上。
参考图2B，将另一成型工艺应用于图2A中的结构(例如，在衬底10的表面102及侧表面以及封装主体13'的侧表面上)以形成封装主体13。封装主体13覆盖(例如完全覆盖)表面安装结构，包含表面安装结构1'。在一些实施例中，封装主体13可通过成型技术(例如传递成型或压缩成型)形成。
参考图2C，将包含表面安装结构1'的表面安装结构从载体29移除以露出表面安装结构1'的电触点14a。然后在表面安装结构1'的电触点14a上形成电触点14b。在一些实施例中，如图2A中所展示，包含表面安装结构1'的表面安装结构可沉入到载体29的表面中，且因此载体29的在两个邻近表面安装结构之间的表面的部分29p可高于表面安装结构安装在其上的载体29的表面的部分。因此，如图2C中所展示，在移除载体29之后，在封装主体13中(例如，在相邻的表面安装结构之间)形成凹部13h。
参考图2D，可以执行单个化以分离出个别的表面安装结构以形成图图1A及图1B中的表面安装结构1。也就是说，通过封装主体13及包含衬底10的衬底条来执行单个化。可以例如通过使用裸片切割锯、激光或其它恰当的切割技术来执行单个化。在一些实施例中，凹部13h可以用作单个化操作的标记或参考标记。
如上文所提及，在图2C中，在移除载体29之后，在封装主体13上形成凹部13h。在单个化之后，可在封装主体13的拐角处形成凹口13h'，如图2D中所展示，对应于凹部13h，这可以影响表面安装结构1的外观。为了避免形成凹口13h'，用于执行切割操作的装置(例如切割装置)的宽度可以相等或大于凹部13h的宽度。然而，使用具有此宽度的切割装置可能损坏或破裂封装主体13。
另外，如在图2A、图2B、图2C及图2D中所展示，表面安装结构1为至少由两个成型工艺，两个凸块安装工艺(一个用于形成电触点14a且另一个用于形成电触点14b)以及一个封装主体去除工艺(例如，通过激光烧蚀来移除封装主体13'的部分以暴露电触点14a)，这会增加用于制造表面安装结构1的成本及复杂性。
图3A说明根据本发明的一些实施例的表面安装结构3的横截面图。如图1中所展示，表面安装结构3类似于表面安装结构1，除了表面安装结构3的扇出结构(例如，电触点34)及表面安装结构1的扇出结构(例如，电触点14a、14b)的结构不同之外。例如，表面安装结构1的扇出结构包含两个焊料凸块，例如电触点14a、14b；而表面安装结构3的扇出结构包含一个焊料凸块，例如电触点34。
电触点34安置在衬底10的表面101上。封装主体33安置在衬底10的表面101上，并覆盖衬底10的表面101及102、传感器11的经暴露部分，电子组件12a、12b及电触点34的第一部分34a。封装主体33暴露电触点34的第二部分34b。例如，封装主体33界定开口以容纳电触点34的第一部分34a。开口的侧壁与电触点34的第一部分34a接触。在开口的侧壁与电触点34的第一部分34a之间可以存在基本上没有间隙。在一些实施例中，如图3B中所展示，其说明由虚线正方形B圈出的图3A中的表面安装结构3的部分的放大图，邻近于封装主体33的表面331、332的开口的宽度W22比封装主体33的较之表面331、332较接近于衬底10的部分处的开口的宽度W21小(例如，邻近于电触点34的部分具有最大宽度)，例如，其中W22为W21的约90％或更小，约85％或更小，或约80％或更小。在一些实施例中，具有电触点34的最大宽度的电触点34的部分(例如，第一部分34a)被封装主体33覆盖或环绕。
在一些实施例中，封装主体33包含具有填料的环氧树脂、模塑料(例如，环氧模塑料或其它模塑料)、聚酰亚胺、酚醛化合物或材料、其中分散有硅酮的材料，或其组合。在一些实施例中，封装主体33可包含透明材料(例如，针对传感器11经配置以进行处理的光，透射率为约80％或更多、透射率为约90％或更多，或透射率为约95％或更多的材料)或不透明材料(例如针对传感器11经配置以进行处理的光，透射率为约20％或更小，透射率为约10％或更小，或透射率为约5％或更小的材料)，此取决于设计规格。在一些实施例中，衬底10的表面101上面封装主体33的厚度在从约25微米(μm)到约100μm的范围内。
封装主体33具有邻近于电触点34的第一表面331，以及与电触点34间隔开的第二表面332。第二表面332可邻近于第一表面331。例如，第一表面331位于第二表面332与电触点34之间。例如，第二表面332及电触点34通过第一表面331彼此物理分离。如图3B中所展示，第一表面331及第二表面332不共面。例如，第一表面331的至少部分低于第二表面332(例如，第一表面经安置成较接近于衬底10)。例如，在封装主体33的表面中存在凹部33g。例如，凹部33g位于封装主体33的第二表面332与电触点34之间。凹部33g可由第一表面331界定。第一表面331环绕电触点件34的第一部分34a并与其接触，而电触点34的第二部分34b从第一表面331暴露。例如，电触点34的第二部分34b从封装主体33的第一表面331及/或第二表面332突出。在一些实施例中，第一表面331及第二表面332可以共同延伸，及/或可以为相同表面的部分。在一些实施例中，第一表面331为表面的第一部分，第一表面331界定凹部33g，且第二表面332为表面的第二部分。
如图3B中所展示，电触点34包含芯，其包焊弹性凸块341(其可为基本上球形的)，金属层342及势垒层343。金属层342环绕弹性凸块341。势垒层343环绕金属层342的至少部分。电触点34进一步包含外层，例如环绕芯的焊料层344。势垒层343安置在金属层342与焊料层344之间的界面处。势垒层343的厚度相对较薄。在一些实施例中，势垒层343的厚度等于或大于约2μm(例如，厚度为约2.2μm或更多，约2.4μm或更多，或约2.6μm或更多)。在一些实施例中，焊料层344的厚度为从约2μm到约15μm。
在一些实施例中，弹性凸块341可包含聚合物。金属层342可包含，例如，铜(Cu)、金(Au)、另一种金属、合金，或其组合。势垒层343可包含镍(Ni)或Ni合金。焊料层344可包含锡(Sn)基焊料或合金(例如，锡-银-铜(SAC)焊料、锡-银(SnAg)焊料等等)。在一些实施例中，电触点34可包含被Sn层覆盖的Cu芯。在一些实施例中，电触点34可包含具有相对高熔点的Sn芯，其由具有相对低熔点的Sn层覆盖。例如，相对高的熔点可以比相对低的熔点大约20摄氏度或更多，约50摄氏度或更多，约100摄氏度或更多，或约200摄氏度或更多。在一些实施例中，电触点34可包含由相对薄的Ni层覆盖的铜核(例如，具有等于或大于约2μm，例如约2.2μm或更多，约2.4μm或更多，或约2.6μm或更多的厚度)。在一些实施例中，电触点34可包含Sn芯。在一些实施例中，在使用薄膜层来塑形封装主体33的成型工艺期间，将包含凸块341、金属层342及势垒层343的芯压成椭圆形或卵形形状。
在一些实施例中，弹性凸块341的弹性模量(例如，弹性模量，拉伸模量或杨氏模量)的范围可为从大约1GPa到大约50GPa，从大约0.5GPa到大约100GPa，或从大约0.1GPa至大约500GPa内，且弹性图块341可以在移除薄膜层(例如，具有约1的纵横比，或具有在约0.5到约1.5的范围内的纵横比)之后从压制的椭圆形或卵形形状恢复成球形形状。然而，金属层342及势垒层343可能不会从椭圆形或卵形形状恢复成球形形状，这是因为与弹性凸块341的弹性模量相比，金属层342及势垒层343的弹性模量(例如，弹性模量，拉伸模量或杨氏模量)可为相对较高(例如，高出约1.5或更多倍，约2或更多倍，约5或更多倍，或约10或更多倍)。这种差异可能导致弹性凸块341通过空间34s与金属层342分离。金属层342界定椭圆形或卵形空间34s。在空间34s中可能具有很少或没有物质，且可为基本上真空的。在氧化金属层342的空间34s中可能存在很少或没有空气或其它气体。
此外，由于弹性凸块341的相对较低的弹性模量，由图3B中的封装主体33暴露的电触点34的部分(例如，第二部分34b)的高度可以容易地控制。如图3的实施例中所展示，由封装主体33暴露的电触点34的部分(例如，第二部分34b)的高度可为至少(或大于)例如约100μm，约200μm或约400μm。
图4A、图4B、图4C及图4D说明根据本发明的一些实施例的制造表面安装结构的方法的各种阶段。在一些实施例中，图4A、图4B、图4C及图4D中所展示的方法可用于制造图3A中的表面安装结构4。
参考图4A，提供表面安装结构3'。在一些实施例中，图4A中的表面安装结构3'可通过以下操作形成：(i)提供包含衬底10的衬底条；(ii)通过例如表面安装技术(SMT)将电子部件12a、12b及电触点34安装在衬底条上；及(iii)将衬底条切割成包含表面安装结构3'的个别表面安装结构。
参考图4B，将经单个化的表面安装结构3'放置在载体(或带)49上。在一些实施例中，载体49包含表面安装结构3'安置在其上的粘合剂层49a及通过粘合剂层49a与表面安装结构3'间隔开的硬层(稳固层)49b。硬层49b用于为以下操作提供支撑。在一些实施例中，黏合剂层49a的厚度为从约13μm到约200μm。在一些实施例中，表面安装结构3'经按压以使得电触点34的部分(例如，第二部分34b)沉入到粘合剂层49a中，而另一部分(例如，第一部分34a)从粘合剂层49a暴露。
参考图4C，封装主体33通过例如压缩成型技术形成以覆盖粘合剂层49a及表面安装结构3'的至少部分。例如，硬层49b连同表面安装结构3'可被放置在成型装置(或设备)48的第一部分48a(例如，上部槽)上，且然后将成型材料从成型装置48的第二部分48b(例如，下部槽)朝向成型装置48的第一部分48a注入，因此成型材料从成型装置48第二部分48b的朝向成型装置48的第一部分48a流动以覆盖粘合剂层49a及表面安装结构3'。在一些实施例中，第二槽48b朝向第一槽48b移动以形成封装主体33。
参考图4D，将载体49从表面安装结构3'移除以暴露电触点34的第二部分34b。然后，可以执行单个化以分离个别的表面安装结构以形成图3A中的表面安装结构3。。也就是说，通过封装主体33及包含衬底10的衬底条进行单个化。可例如通过使用裸片切割锯，激光或其它恰当的切割技术来执行单个化。
如图4A、图4B、图4C及图4D中所展示，表面安装结构3通过一种成型工艺及一种凸块安装工艺(例如，通过单个成型工艺及单个凸块安装工艺)形成。另外，可省略封装主体移除过程(例如激光烧蚀)。因此，与图2A、图2B、图2C及图2D中所展示的方法相比，图4A、图4B、图4C及图4D中所展示的方法将减少制造表面安装结构3的成本及复杂性。
如本文中所使用，相对术语，例如，“内”、“内部”、“外”、“外部”、“顶部”、“底部”、“前”、“后”、“上部”、“向上”、“下部”、“向下”、“垂直”、“垂直地”、“侧向”、“侧向地”、“在...上面”及“在...下面”是指一组组件相对于彼此的定向；此定向是根据图式，在非制造或使用器件所要求的。
如本文中所使用，除非上下文另有明确指示，否则单数术语“一(a)”、“一(an)”和“所述”可包含复数对象。
如本文中所使用，术语“连接”、“经连接”及“连接”是指操作耦合或链接。经连接组件可为直接或间接(例如，通过另一组件组)彼此耦合。
如本文中所使用，术语“大约”、“基本上”、“基本”和“约”用于描述及考虑小变化。在结合事件或情形使用时，所述术语可以指其中事件或情形明确发生的情况以及其中事件或情形接近于发生的情况。例如，当结合数值使用时，所述术语可以指小于或等于所述数值±10％的变化范围，例如小于或等于±5％，小于或等于±4％，小于或等于±3％，小于或等于±2％，小于或等于±1％，小于或等于±0.5％，小于或等于±0.1％或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％，小于或等于±4％，小于或等于±3％，小于或等于±2％，小于或等于±1％，小于或等于±0.5％，小于或等于±0.1％或小于或等于±0.05％)，那么所述值可被认为“基本上”相同或相等。
如果两个表面之间的位移不大于5μm，不大于2μm，不大于1μm或不大于0.5μm，那么两个表面可被认为是共面或基本上共面。
如果表面上的最高点与最低点不大于5μm，不大于2μm，不大于1μm，或不大于0.5μm，那么表面可被认为是共面或基本上共面。
另外，数量、比率及其它数值有时在本文中以范围格式呈现。应理解，此范围格式是出于便利及简洁起见而使用，且应灵活地解释为包含明确规定为范围的限制的数值，以及所述范围内囊括的所有个别数值或子范围，犹如每一数值及子范围是明确规定的。
在一些实施例的描述中，提供在另一组件的“上”或“上方”的组件可囊括其中后一组件直接在前一组件上(例如，物理接触)的状况，以及其中一或多个介入组件可位于前一组件与后一组件之间的状况。
虽然已参考本发明的特定实施例描述并说明本发明，但这些描述及说明并不限制本发明。所属领域的技术人员应理解，在不背离如随附权利要求书所界定的本发明的真实精神及范围的情况下，可做出各种改变且可替代等效物。说明可不必按比例绘制。由于制造过程中之变数等等，因此本发明中之精巧呈现与实际设备之间可存在差异。可存在本发明的未具体说明的其它实施例。说明书及图式应视为说明性而非限制性。可进行修改以使特定情况，材料，物质组合物，方法或工艺适应本发明的目的，精神及范围。所有此些修改意欲属于随附的权利要求书的范围内。虽然已参考以特定次序执行的特定操作来描述本文中所揭示的方法，但应理解，可在不背离本发明的教示的情况下将这些操作组合，细分或重新排序以形成等效方法。因此，除非本文中特别指明，否则操作之次序及分组并非本发明的限制。

Claims (21)

1.一种表面安装结构，其包括：
衬底，其具有第一表面以及与所述第一表面相对的第二表面；
传感器，其经安置成邻近于所述衬底的所述第二表面；
电触点，其安置在所述衬底的所述第一表面上；以及
封装主体，其覆盖所述衬底的所述第一表面及所述第二表面、所述传感器的部分以及所述电触点的第一部分。
2.根据权利要求1所述的表面安装结构，其中
所述传感器安置在所述衬底内；以及
所述传感器的表面从所述衬底的所述第二表面暴露并被所述封装主体覆盖。
3.根据权利要求1所述的表面安装结构，其中
覆盖所述衬底的所述第一表面的所述封装主体具有环绕所述电触点的第一表面及通过所述第一表面与所述电触点分离的第二表面；以及
所述封装主体的所述第一表面及所述封装主体的所述第二表面不共面。
4.根据权利要求3所述的表面安装结构，其中所述封装主体的所述第一表面比所述封装主体的所述第二表面更接近于所述衬底。
5.根据权利要求3所述的表面安装结构，其中所述电触点包括从所述封装主体的所述第一表面或所述第二表面突出的第二部分。
6.根据权利要求3所述的表面安装结构，其中凹部是通过所述封装主体的所述第一表面界定，且位于所述电触点与所述封装主体的所述第二表面之间。
7.根据权利要求3所述的表面安装结构，其中所述封装主体的所述第一表面与所述电触点的所述第一部分的侧壁接触。
8.根据权利要求3所述的表面安装结构，其中
所述第一封装主体界定开口，所述电触点的所述第一部分安置在所述开口中；以及
所述开口的至少部分的宽度朝向所述封装主体的所述第一表面渐缩。
9.根据权利要求1所述的表面安装结构，其中所述电触点的最大宽度包含在由所述封装主体覆盖的所述电触点的所述第一部分中。
10.根据权利要求1所述的表面安装结构，其中所述封装主体在所述衬底的所述第一表面上方的厚度在约25微米(μm)到约100μm的范围内。
11.根据权利要求1所述的表面安装结构，其中所述电触点包括芯及覆盖所述芯的外层。
12.根据权利要求11所述的表面安装结构，其中所述芯的熔点高于所述外层的熔点。
13.根据权利要求11所述的表面安装结构，其中所述芯及所述外层包含锡或锡合金。
14.根据权利要求11所述的表面安装结构，其中所述芯包含铜且所述外层包含锡或锡合金。
15.根据权利要求11所述的表面安装结构，其中所述芯包括邻近于所述外层的势垒层，且所述势垒层包含镍或镍合金。
16.根据权利要求15所述的表面安装结构，其中所述势垒层的厚度等于或大于约2μm。
17.根据权利要求11所述的表面安装结构，其中所述外层的厚度在约2μm到约15μm的范围内。
18.一种制造表面安装结构的方法，所述方法包括：
(a)提供衬底，所述衬底具有第一表面及与所述第一表面相对的第二表面；
(b)在所述衬底的所述第一表面上安置电触点，所述电触点包括第一部分及第二部分；
(c)将所述电触点放置在覆盖所述电触点的所述第一部分并暴露所述电触点的所述第二部分的带上；
(d)形成覆盖所述衬底的所述第一表面及所述第二表面以及所述电触点的所述第二部分的封装主体；以及
(e)移除所述带以暴露所述电触点的所述第一部分。
19.根据权利要求18所述的方法，其中操作(d)进一步包括：
将所述带放置在成型设备的第一槽上；及
使所述成型设备的第二槽朝向所述成型设备的所述第一槽移动以形成覆盖所述衬底的所述第一表面及所述第二表面的所述封装主体。
20.根据权利要求18所述的方法，其中所述带包含稳固层，及所述电触点安置在其上的粘合剂层，且所述粘合剂层的厚度为从约13μm到约200μm。
21.根据权利要求18所述的方法，其中操作(c)进一步包括将所述电触点按压到所述带中。
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