CN104835746B - 具有被结合到金属箔的半导体管芯的半导体模块 - Google Patents
具有被结合到金属箔的半导体管芯的半导体模块 Download PDFInfo
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- CN104835746B CN104835746B CN201510071017.0A CN201510071017A CN104835746B CN 104835746 B CN104835746 B CN 104835746B CN 201510071017 A CN201510071017 A CN 201510071017A CN 104835746 B CN104835746 B CN 104835746B
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- metal
- metal foil
- semiconductor element
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- electrically insulating
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Abstract
具有被结合到金属箔的半导体管芯的半导体模块。一种制造半导体模块的方法包括提供包括被附着于金属层的金属箔的金属复合材料衬底,该金属箔比金属层更薄且包括与之不同的材料,在将金属箔结构化之前将多个半导体管芯的第一表面附着于金属箔,并将被附着于金属箔的半导体管芯装入电绝缘材料中。在用电绝缘材料包住半导体管芯之后将金属层和金属箔结构化,使得电绝缘材料的表面区没有金属箔和金属层。沿着没有金属箔和金属层的表面区划分电绝缘材料以形成单个模块。
Description
技术领域
本申请涉及半导体模块、特别是具有被结合到金属箔的半导体管芯的半导体模块的制造。
背景技术
功率半导体管芯(芯片)封装技术中的最新进步利用芯片嵌入概念。用电流过程(galvanic process)来替换标准封装过程,诸如导线或夹持结合以及公共成型技术。还用层压件来保护半导体管芯。结果是明显减小的封装占位空间(footprint)、封装电阻和电感以及低热阻。例如,通常将管芯焊接到结构化引线框架。在嵌板层压过程期间,将几个引线框架连同FR4层压件层压在一起。
由于由使将引线框架保持在原位的固定插脚对准所引起的层压过程期间的非线性收缩/膨胀和引线框架之间的对准公差,要求管芯和引线框架位置的光学测量和对应的数据文件修正。并且,管芯、引线框架和嵌板的翘曲由于引线框架与管芯之间的CTE(热膨胀系数)失配和厚度差而相对高,引起微过孔高度的差及层压和微过孔镀敷过程中的挑战。
此外,按照惯例,在扩散焊接的情况下在管芯单体化(分离)之前在晶片背表面上沉积管芯附着焊料,或者也将其分配在被印刷到晶片背表面的蜡纸或引线框架的管芯焊盘上。在晶片的背面上通过厚金属层的切割是具有挑战性的,并降低切割质量、降低生产量(throughput)且减少切割刀片的寿命。并且,在结合过程期间挤出管芯背面上的焊料的一部分。管芯背面焊料的此‘挤出’并不是均匀的,不容易控制且是不可重复的。
发明内容
根据制造半导体模块的方法的实施例,该方法包括:
提供包括被附着于金属层的金属箔的金属复合材料衬底,该金属箔比金属层更薄且包括与之不同的材料;
在将金属箔结构化之前将多个半导体管芯的第一表面附着于金属箔;
将被附着于金属箔的半导体管芯装入电绝缘材料中;
在用电绝缘材料包住半导体管芯之后将金属层和金属箔结构化,使得电绝缘材料的表面区没有金属箔和金属层;以及
沿着没有金属箔和金属层的表面区划分电绝缘材料以形成单个模块。
根据半导体模块的实施例,该半导体模块包括金属复合材料衬底,其包括被附着于结构化金属箔的第一表面的金属层。结构化金属箔具有与第一表面相对的第二表面且比金属层更薄。金属层具有从结构化金属箔的第一表面向外延伸的锥形侧壁。该半导体模块还包括至少一个半导体管芯,其具有被附着于结构化金属箔的第二表面的第一表面、被附着于结构化金属箔的第二表面且包住所述至少一个半导体管芯的层压件、以及在背对金属复合材料衬底的层压件表面上的结构化金属层。该结构化金属箔具有从层压件向外延伸的侧壁。结构化金属箔的侧壁未被层压件覆盖且与金属复合材料衬底的金属层的侧壁对准。层压件具有在层压件的相对第一和第二主表面之间延伸的边缘。层压件的边缘未被金属覆盖。
根据将半导体管芯附着于金属复合材料衬底的方法的实施例,该方法包括:
提供包括被附着于金属层的金属箔的金属复合材料衬底,该金属箔比金属层更薄且包括与之不同的材料;
用比金属箔和金属层熔点更低的焊料来涂敷与金属层相对的金属箔表面;
经由焊料而将多个半导体管芯的第一表面扩散焊接至金属箔,包括焊料到高熔点相的等温凝固;以及
在将半导体管芯的第一表面扩散焊接到金属箔之后将半导体管芯装入电绝缘材料中。
在阅读以下详细描述时且在查看附图时,本领域的技术人员将认识到附加特征和优点。
附图说明
附图的元件不一定相对于彼此按比例。相似的参考数字指定对应的类似部分。可将各种所示实施例的特征组合,除非其相互排斥。在图中描述了实施例并在随后的描述中进行详述。
图1图示出半导体模块的实施例的截面图。
图2包括图2A至2K,图示出制造图1的半导体模块的方法的实施例。
图3图示出将半导体管芯扩散焊接到金属复合材料衬底的方法的实施例。
图4包括图4A至4G,图示出基于图3的扩散焊接方法的制造半导体模块的方法的实施例。
图5包括图5A至5I,图示出基于图3的扩散焊接方法的制造半导体模块的方法的另一实施例。
图6包括图6A至6H,图示出基于图3的扩散焊接方法的制造半导体模块的方法的另一实施例。
图7图示出基于图3的扩散焊接方法制造的半导体模块的实施例。
图8图示出基于图3的扩散焊接方法制造的半导体模块的另一实施例。
具体实施方式
根据本文所述的某些实施例,提供了用于使用批量管芯附着过程将半导体管芯结合到金属复合材料衬底的薄金属箔的相对厚的金属复合材料衬底。可以使用金属层来将金属箔结构化。还可以在可选焊料涂敷、结合和层压之前将金属箔结构化。根据本文所述的其它实施例,在金属箔而不是管芯上沉积管芯附着焊料,消除了用厚的背面金属化件来将管芯单体化(分离)的需要。可以使用沉积在金属箔上的管芯附着焊料作为硬掩模以将未结构化金属箔图案化,并且如果期望的话可以在管芯附着过程之后用简单的选择性蚀刻过程来去除焊料。可将这些实施例组合至少达到此类组合并非相互排斥的程度。
图1图示出半导体模块100的实施例的截面图。半导体模块100包括金属复合材料衬底102,其包括金属层104,例如被附着于诸如铜箔之类的结构化金属箔106的第一表面105的铝层。结构化金属箔106具有与第一表面105相对的第二表面107且比金属层104更薄。例如,金属层104可以具有在30 µm和400 µm之间的厚度(T1)且结构化金属箔106可以具有在3 µm和100 µm之间的厚度(T2)。金属层104具有从结构化金属箔106的第一表面105向外延伸的锥形侧壁108。
半导体模块100还包括至少一个半导体管芯110,其具有被附着于结构化金属箔106的第二表面107的第一表面111。在图1中将管芯110与结构化金属箔106之间的此连接/附着区标记为‘DAR’,其是‘管芯附着区’的简写。可以在模块100中包括任何类型的半导体管芯110,诸如类似于功率MOSFET(金属氧化物半导体场效应晶体管)或IGBT(绝缘栅双极晶体管)的功率半导体管芯、例如通过绝缘粘合剂(没有背面连接)被结合到金属箔106的逻辑管芯(例如驱动器、控制器)等。
半导体模块100还包括被附着于结构化金属箔106的第二表面107的电介质层112(诸如层压件、树脂层等)和背对金属复合材料衬底102的电介质层112的表面113上的结构化金属层114。电介质层112包住半导体管芯110。
结构化金属箔106具有从电介质层112向外延伸的侧壁116。结构化金属箔106的侧壁116未被电介质层112覆盖并与金属复合材料衬底102的金属层104的侧壁108对准。电介质层112具有边缘区118,其中,电介质层112的边缘120在电介质层112的相对第一和第二主表面113、115之间延伸。电介质层112的边缘120未被金属覆盖。
一个或多个第一微过孔连接122通过电介质层112从与第一表面111相对的管芯110的第二表面177延伸至背对金属复合材料衬底102的电介质层的表面113上的结构化金属层114。第一微过孔连接122在管芯110的第二表面117处提供用于端子124的外部电接触的点。
一个或多个第二微过孔连接126通过电介质层112从结构化金属箔106延伸到背对金属复合材料衬底102的电介质层112的表面113上的结构化金属层114。第二微过孔连接126在管芯110的第一表面111处提供用于端子的外部电接触的点。如果管芯110中的一个或多个在管芯110的第一表面111处不具有端子(例如,在横向晶体管管芯的情况下),则可以省略第二微过孔连接126。在管芯110的第一表面111处是否提供端子取决于管芯的类型,并且因此为了便于举例说明而未在图1中示出此类端子。可以如图1中所示将金属复合材料衬底102的金属层104结构化且其在管芯110的操作期间充当热沉,通过结构化金属箔106消散来自管芯110的第一表面111的热量。
包括图2A至2K的图2图示出制造图1中所示种类的半导体模块的方法的实施例。图2A是在金属层204上包括金属箔条202的金属复合材料衬底嵌板200的自上而下平面图。一般地,金属箔可以覆盖整个金属层204且也可以被结构化。金属箔条202比金属层204更薄且包括与之不同的材料。在一个实施例中,金属层204是具有在50 µm和200 µm之间的厚度的铝层,并且金属箔条202是每个具有在3 µm和100 µm之间的厚度的铜箔条。可以将铜箔镀覆、涂敷、溅射等到铝层上。在一个示例中,衬底200是Cu/Al复合材料衬底,包括具有约9 µm的厚度的Cu箔条202和具有约100 µm的厚度的Al层204。
图2A中所示的金属箔条布置允许较高的封装密度,因为可以将整个生产嵌板200用于组装。并且,该金属箔条布置允许用于测试管芯被附着在其中的模块可用区的更高最大电流。可以通过优化材料厚度来调整由金属箔条202和金属层204形成的金属复合材料衬底嵌板200的机械性质。嵌板200的金属复合材料结构提供了更稳定的嵌板,并且子过程也更加可行和可靠。图2B至2K是在制造方法的不同阶段沿着图2A中的标记为A—A'的线得到的相应的截面图。
在图2B中,在金属箔202的结构化之前将多个半导体管芯206的第一表面205附着于所示金属箔202。管芯的第一表面205可以如先前在本文中所述地具有一个或多个端子或者没有端子,并且因此在图2中为了便于图示而未在管芯206的第一表面205处示出端子。与第一表面相对的管芯206的第二表面207具有一个或多个端子208。
通过将管芯206附着于诸如铜箔之类的单片金属箔202,后续层压在层压过程期间导致相对线性的收缩,其可以被更容易地模拟以计算补偿因数。最后例如通过蚀刻但是在首先将管芯206附着于箔202之后将金属箔202结构化。在一个实施例中,管芯206的第一表面205是管芯206的背面。可以使用任何标准管芯附着材料210和过程(诸如焊接、扩散焊接、烧结、粘结等)将管芯206附着于金属箔202。在稍后在本文中结合图3至8更详细地描述的扩散焊接的情况下,金属箔202可以是铜箔。可以使用其它材料,诸如用于金属箔202的类似于NiAu或NiCu的镍合金,或者与扩散焊接相容的任何其它金属材料。
在每种情况下,可以在小于300℃(例如约250℃)的温度下作为批量过程将管芯206并行地扩散焊接到金属箔202。通常在约350℃的较高温度下连续地(即一次一个管芯)执行扩散焊接以便减少总管芯附着时间。在300℃或更低的较低温度下的扩散焊接导致较慢的相形成(即,形成高熔点相需要更多时间),但产生更少翘曲,因为管芯附着过程温度明显较低。与常规串行管芯附着过程相比,作为批量过程的一部分将管芯206并行地扩散焊接到金属箔202大大地减少了整体管芯附着过程时间,即使管芯附着温度在批量过程中较低。可以例如使用诸如UV激光之类的激光过程在管芯附着之前在金属箔202中制造对准标记和夹具孔(jig hole)。为了便于图示,在图2中未示出对准标记和夹具孔。
通过使用金属复合材料衬底200(其中如图2B中所示使用批量管芯附着过程将半导体管芯206附着于金属箔202),可以在前表面的层压和图案化过程之后例如用选择性蚀刻过程由金属复合材料衬底202的金属层204制造热沉结构。所得到的结构的某些有利特性是热沉与其中附着管芯206的金属箔202进行冶金接触,并且可以在完成前表面的层压和图案化之后用蚀刻过程来制造热沉。并且,将管芯206附着于相对薄的金属箔202(例如,厚度在3µm与100µm之间)允许管芯206使金属箔202变形,并且因此提供应力释放机制,这对于在管芯附着期间不变形的常规厚Cu箔而言是不可能的。
在图2C和2D中,将附着于金属箔202的半导体管芯206装入电绝缘材料212中。根据图2C和2D中所示的实施例,电绝缘材料212是层压件。在层压的情况下,可以使用激光结构化预浸料(prepreg)214将嵌板200例如放置在夹具台(jig table)中,并且Cu或Cu/Al顶箔216可以用钻孔、布线(route)、冲孔等来结构化,或者可以使用不需要结构化的材料,诸如聚合物/树脂膜(或者甚至印刷、涂敷等)。预浸料包括预先浸渍复合材料纤维,其中已存在诸如环氧树脂之类的基质材料。可以在标准PCB(印刷电路板)真空压制系统中执行层压过程。在该压制循环期间,预浸料树脂214熔化并在树脂214完全交联(crosslink)之前填充部件206的周围。可以使用其它电绝缘材料212来包住半导体管芯206,诸如成型化合物、环氧树脂等。层压结构可以在背对金属复合材料衬底200的层压件212的表面213上包括金属层216。在一个实施例中,此金属层216包括铜。
在图2E和2F中,在电绝缘材料212中形成第一微过孔开口218,其从背对金属复合材料衬底200的电绝缘材料212的表面213延伸到管芯206的第二表面207、即背对金属复合材料结构200的管芯206的表面207。在电绝缘材料212是层压件的情况下,可以在两步过程中或者用直接激光钻孔过程来形成第一微过孔开口218。两步过程包括首先向背对金属复合材料衬底200的层压件212的表面213上的金属层216中蚀刻开口220以形成掩模。然后例如使用CO2激光器在被金属层216中的开口220暴露的地方去除层压件树脂,以在电绝缘材料212中形成第一微过孔开口218。
在图2G中,例如使用直接金属化过程或无电和电化学镀覆过程来填充第一微过孔开口218,或者其保持未填充但被镀覆或涂敷导电材料。在每种情况下,所得到的第一微过孔连接222通过电绝缘材料212从管芯206的第二表面207处的端子208延伸到背对金属复合材料衬底200的电绝缘材料212的表面213上的金属层216。可以类似地形成第二微过孔连接,其通过电绝缘材料212从金属箔202延伸到背对金属复合材料衬底200的电绝缘材料212的表面213上的金属层216,例如,如图1中所示。第二微过孔连接可以将管芯206的第一表面205处的一个或多个端子连接到背对金属复合材料衬底200的电绝缘材料212的表面213上的金属层216。例如在其中在管芯206的第二表面207处提供管芯206的所有端子208的横向晶体管管芯的情况下,可以不需要此类第二微过孔连接。
在图2H中,将金属复合材料衬底200的金属层204结构化(图案化)以形成热沉结构224。在一个实施例中,在形成微过孔连接222之后在金属层204上层压/涂敷光致抗蚀剂226。对光致抗蚀剂226进行曝光、显影和蚀刻以使金属层204的区域暴露。然后例如在铝金属层的情况下使用高度选择性蚀刻过程来去除金属层204的暴露区以形成具有锥形侧壁225的期望热沉结构224。
在图2I中,在设置于背对金属复合材料衬底200的电绝缘材料212的表面213上的金属层216上层压/涂敷光致抗蚀剂228。然后对光致抗蚀剂228进行曝光和显影以形成具有限定结构的掩模。
在图2J中,通过使用显影光致抗蚀剂228作为掩模来蚀刻金属层216而将背对金属复合材料衬底200的电绝缘材料212的表面213上的金属层216结构化。还使用金属复合材料衬底200的先前结构化金属层204作为掩模来蚀刻在结构的相对侧的金属箔202。也就是说,先前由金属复合材料衬底200的金属层204形成的热沉结构224使被去除的金属箔202的区域暴露。如果背对金属复合材料衬底200的电绝缘材料212的表面213上的金属箔202和金属层216包括诸如铜之类的相同材料的话,可以使用相同的蚀刻剂将两者结构化。
此时在该制造方法中,金属复合材料衬底200的金属层204和金属箔202两者都已在用电绝缘材料212包住半导体管芯206之后被结构化,使得电绝缘材料212的表面区230没有复合材料衬底200的金属箔202和金属层204且没有背对金属复合材料衬底200的电绝缘材料212的表面213上的金属层216。
在图2K中,沿着没有金属结构202、204、216的表面区230划分电绝缘材料212以形成单个模块。这可以包括将嵌板200切割成条状尺寸,在正面用阻焊剂来涂敷所得到的条的表面并使用层压件切割过程来将每个条的单个模块分离。
结合图2所述的过程流程的顺序可以不同。并且,可以将附加堆积(build-up)层层压到电绝缘材料212的顶面213。可以例如用结构化层压件和将衬底200、结构化层压件和金属层216结合在一起的树脂膜(例如结合膜)来替换预浸料214。可以例如用诸如在批量管芯附着过程期间放置在背面上的薄层压层(未示出)来保护金属复合材料衬底200的金属层204的暴露(底部)表面。Cu/Al复合材料衬底仅仅是一个选项。还可以使用其它金属箔和/或复合材料箔。还可使用替换焊接过程或材料来将管芯206附着于金属箔202。例如,可以如先前参考管芯附着过程所述地采用扩散焊接过程,在图2B中图示出其结果。
扩散焊接是扩散结合和焊接的混合。扩散焊接的原理是将诸如In、Sn或InSn之类的微量的低熔点焊料中间层敷设到被压制在一起并被加热以形成液体填料的部件之间的接头中,该液体填料通过经由与衬底的等温反应到高熔点相的转换而凝固。液体填料形成,因为超过了中间层焊料的熔点或者由于低和高熔点部件之间的共晶反应。液体填料的等温凝固在相对低的温度下形成强结合,其然后在高得多的温度下仍是固体的。在本文中参考在扩散焊接过程中使用的中间层管芯附着焊料所使用的术语‘低熔点’意指该焊料具有低于被接合的部件的熔点。通过相互扩散或反应扩散而产生的接头不会重新熔化,除非被加热至在其处高熔点相熔化的温度。用于半导体部件的常规扩散焊接过程涉及到在管芯单体化(分离)之前向晶片背面施加管芯附着焊料,其通过要求将切穿厚的晶片背面金属化作为单体化过程的一部分而不利地影响晶片单体化过程。
图3图示出使用其中向金属复合材料衬底而不是管芯施加管芯附着焊料的扩散焊接过程将半导体管芯附着于例如先前在本文中参考图1和2所述种类的金属复合材料衬底的方法的实施例。该方法包括提供一种包括被附着于金属层的金属箔的金属复合材料衬底,该金属箔比金属层更薄且包括与之不同的材料(方框300)。金属箔可以包含Cu、Ni、Ag等。然后用熔点低于金属箔和金属层的管芯附着焊料来涂敷与金属层相对的金属箔的表面(方框302)。通过用管芯附着焊料来覆盖金属箔的整体或大部分而避免焊料‘挤出’的问题。
管芯附着焊料可以被结构化(方框306)或在管芯附着之前保持未结构化(方框308)。在将管芯附着焊料结构化的情况下,可以使用结构化焊料作为掩模以使底层金属箔图案化(方框310),并且然后将管芯放置在结构化管芯附着材料上(方框312)。在管芯附着焊料在管芯附着之前保持未结构化的情况下,将管芯放置在未结构化管芯附着材料上(方框314)。
在任一种情况下(结构化或未结构化管芯附着焊料),然后用扩散焊接将管芯附着于金属箔,由此,将管芯和金属复合材料衬底压在一起并加热以由管芯附着焊料形成液体填料,该液体填料通过经由与管芯和金属复合材料衬底的等温反应到高熔点相的转换而固化(方框316)。可以例如通过选择性蚀刻而从金属箔去除多余焊料,诸如焊料的未反应部分,即并未与管芯结合的焊料部分(方框318)。模块组装过程然后例如通过将半导体管芯装入电绝缘材料中、形成微过孔连接和模块单体化来继续(方框320),如先前在本文中所述。
图4和5图示出用于结构化和未结构化管芯附着焊料的图3中所示的扩散焊接方法的不同阶段。包括图4A至4G的图4图示出其中管芯附着焊料在管芯附着之前保持未结构化的扩散焊接方法的实施例。包括图5A至5I的图5图示出其中在管芯附着之前将管芯附着焊料结构化的扩散焊接方法的实施例。
在管芯附着焊料在管芯附着过程之前保持未结构化的情况下,提供包括被附着于金属层404的金属箔402的金属复合材料衬底400,并且用熔点低于金属箔402和金属层404的管芯附着焊料406来涂敷与金属层404相对的金属箔402的表面401,如图4A中所示。金属箔402比金属层404更薄且包括与之不同的材料。例如,金属层404可以是具有在50 µm和200µm之间的厚度的铝层,并且金属箔402可以是具有在3 µm和100 µm之间的厚度的铜箔。可以使用其它材料,诸如镍合金,比如用于金属箔402的NiAu或NiCu,或者任何其它与扩散焊接相容金属材料。可以使用适合于扩散焊接的任何管芯附着焊料406,诸如Sn、In、Zn或焊料合金,例如AuSn、SnAg、InAg、InSn或SAC焊料、J合金或另一充分低熔点金属或焊料合金。
在管芯附着过程之前将管芯附着焊料结构化的情况下,提供包括被附着于金属层506的金属箔502的金属复合材料衬底500,并且用熔点低于金属箔502和金属层504的管芯附着焊料506来涂敷与金属层504相对的金属箔502的表面501,如图5A中所示。如上文结合图4A所述,金属箔502比金属层504更薄且包括与之不同的材料。例如,金属层504可以是具有在50 µm和200 µm之间的厚度的铝层,并且金属箔502可以是具有在3 µm和100 µm之间的厚度的铜箔。可以使用其它材料,诸如镍合金,比如用于金属箔502的NiAu或NiCu,或者任何其它与扩散焊接相容金属材料。可以使用适合于扩散焊接的任何管芯附着焊料506,诸如Sn、In、Zn或焊料合金,例如AuSn、SnAg、InAg、InSn或SAC焊料、J合金或另一充分低熔点的金属或焊料合金。在管芯附着之前,例如使用光刻过程和如图5B中所示的蚀刻来将管芯附着焊料506结构化。然后使用结构化焊料506作为硬掩模以用于例如通过蚀刻将在焊料506下面的金属箔502结构化,如图5C中所示。
在图4或5的任一实施例中,可以在将半导体管芯扩散焊接到金属箔402/502之前向与金属层404/504相对的金属箔402/502的表面401/501施加烧结层、焊膏和胶粘剂中的一个或多个。在图4和5中为了便于图示而未示出此类附加层。
在图4B和5D中,通过扩散焊接而在管芯408/508的第一表面407/507处将半导体管芯408/508附着于金属箔402/502,由此,将管芯408/508和金属复合材料衬底400/500压在一起并加热以由管芯附着焊料406/506形成液体填料,该液体填料通过经由与管芯408/508和金属复合材料衬底400/500的等温反应到高熔点相的转换而凝固。在一个实施例中,在将管芯408/508的第一表面407/507扩散焊接到金属箔402/502之前向半导体管芯408/508的第一表面407/507施加金属化410/510。例如,可以向管芯408/508的第一表面407/507施加诸如Ti/Cu/Ag、Al/Ti/Cu/Ag或Al/Ti/NiV/Ag之类的背面金属化410/510并用扩散焊接将其结合到管芯附着焊料406/506。管芯408/508的相对(第二)表面409/509背对金属箔402/502并包括诸如结合焊盘之类的一个或多个端子412/512。
在图4C和5E中,例如使用蚀刻过程从管芯408/508被扩散焊接到的金属箔402/502的表面401/501去除多余焊料406/506。未被管芯408/508覆盖的管芯附着焊料406/506的多余部分并不作为扩散焊接过程的一部分与管芯408/508反应(即结合)。因此,可以在将管芯408/508扩散焊接到金属箔402/502之后和将管芯408/508装入电绝缘材料中之前从金属箔402/502中去除焊料406/506的这些未反应部分。
在图4D和5F中,在将半导体管芯408/508扩散焊接到金属箔402/502之后将其装入电绝缘材料414/514中。在一个实施例中,用层压过程来实现电绝缘材料414/514,例如,如先前在本文中结合图2C和2D所述。可以例如用将部件结合在一起的结构化层压件和树脂膜(例如结合膜)来替换在标准层压过程中使用的预浸料。可以使用其它电绝缘材料414/514来包住半导体管芯408/508,诸如成型化合物、环氧树脂等。在每种情况下,可以在背对金属复合材料衬底400/500的电绝缘材料414/514的表面413/513上提供诸如铜层之类的金属层416/516。
在图4E和5G中,形成第一微过孔连接418/518,其通过电绝缘材料414/514从管芯408/508的第二表面409/509处的端子412/512延伸到背对金属复合材料衬底400/500的电绝缘材料414/514的表面413/513上的金属层416/516。可选的第二微过孔连接420/520通过电绝缘材料414/514从金属箔402/502延伸到背对金属复合材料衬底400/500的电绝缘材料414/514的表面413/513上的金属层416/516。可以使用标准光刻法、蚀刻和激光钻孔过程来制造微过孔连接418/518、420/520,例如,如先前在本文中结合图2E、2F和2G所述。
在图4F和5H中,使用标准光刻法和选择性蚀刻过程将金属复合材料衬底400/500的金属层404/504图案化。可以在最终模块产品中使用结构化金属层404/504作为热沉,或者在金属箔402/502的结构化之后将其去除。
在图4G和5I中,例如使用标准光刻法和选择性蚀刻过程将背对金属复合材料衬底400/500的电绝缘材料414/514的表面413/513上的金属层416/516结构化。在金属箔402/502先前未被结构化的情况下,还可以现在使用金属复合材料衬底400/500的结构化金属层404/504作为掩模将金属箔402/502结构化。可以在金属箔402/502的结构化之后将金属复合材料衬底400/500的结构化金属层404/504去除,或者可以将其保留作热沉结构422/522。可以沿着没有金属箔402/502和金属层404/504、416、516的表面区来划分电绝缘材料414/514以形成单个模块,例如,如先前在本文中结合图2J和2K所述。
包括图6A至6H的图6图示出图3中所示的扩散焊接方法的又一实施例的不同阶段。
在图6A中,提供诸如Cu/Al衬底之类的金属复合材料衬底600,其包括被附着于金属层604的金属箔602。在根据本实施例的制造过程期间使用在金属箔602下面的金属层604作为临时载体。金属箔602比金属层604更薄且包括与之不同的材料。例如,金属层604可以是具有在50µm和200µm之间的厚度的铝层,并且金属箔602可以是具有在3µm和100µm之间的厚度的铜箔。可以使用其它材料,诸如镍合金,比如用于金属箔602的NiAu或NiCu,或者任何其它与扩散焊接相容金属材料。
在图6B中,向金属箔602的暴露表面601施加管芯附着焊料606。焊接材料606可以是例如Sn、In、Zn或焊料合金,例如AuSn、SnAg、InAg、InSn或SAC焊料、J合金或另一充分低熔点的金属或焊料合金。除用焊接材料606覆盖金属箔602的暴露表面601之后,还可以向金属箔602的表面601施加一个或多个附加材料(为了便于图示而未示出),诸如胶粘剂、纳米膏、烧结材料等。
在图6C中,例如使用标准光刻法和蚀刻过程将管芯附着焊料606结构化。可以使用结构化管芯附着焊料606作为硬掩模以用于将在焊料606下面的金属箔602结构化。替换地,可以在将焊料606施加于金属复合材料衬底600之前将金属箔602结构化。
在图6D中,经由扩散焊接将具有诸如Ti/Cu/Ag、Al/Ti/Cu/Ag或Al/Ti/NiV/Ag之类的背面金属化610的半导体管芯608(为了便于图示而仅示出一个)结合到管芯附着焊料606,如本文先前描述的。一般地,背面金属化610可以包括用于焊接的任何适当材料系统,包括用于提供与半导体材料(例如Si、SiN、GaAs、GaN等)电接触的接触层、阻挡层(例如,Ti、TiW、W等)和一个或多个功能层(Cu、Ni、Ag等)和一个或几个层(例如,Cu/Ag等),以提供与管芯附着材料606的电接点形成。管芯608具有设置在与第一表面607相对的管芯608的第二表面609处的端子612。管芯的第一表面607被扩散焊接到金属箔602。可以如图6D中所示预先将金属箔602结构化,或者此时其在该过程中保持未结构化。
在图6E中,可选地例如使用蚀刻过程从金属箔602的顶面601去除多余焊料606,如先前在本文中结合图4C和5E所述。
在图6F中,可以使用标准敷层(layup)及层压过程和材料来完成与层压件614和最上层金属化616的铺叠和层压,例如,如先前在本文中结合图4D和5F所述。
在图6G中,例如用选择性蚀刻过程来去除金属复合材料衬底600的金属层604。还例如使用标准光刻法、蚀刻、激光钻孔和镀覆过程来形成微过孔连接618、620,如先前在本文中例如结合图4E和5G所述。
在图6H中,例如使用标准光刻法和选择性蚀刻过程将电绝缘材料层压件614上的最上层金属层616结构化。在金属箔602未被预先结构化的情况下,可以通过施加光致抗蚀剂作为掩模来在同一过程步骤期间将金属箔602结构化。
图7图示出根据图3的方法制造的半导体模块700的实施例的截面图。半导体模块700包括金属复合材料衬底702,其包括金属层704,诸如被附着于诸如铝箔之类的结构化金属箔706的第一表面705的铝层。结构化金属箔706具有与第一表面705相对的第二表面707且比金属层704更薄。例如,金属层704可以具有在50 µm和200 µm之间的厚度,并且金属箔706可以具有在3 µm和100 µm之间的厚度。金属层704具有从结构化金属箔706的第二表面707向外延伸的锥形侧壁708。
半导体模块700此外包括至少一个半导体管芯710,其被根据图3的方法扩散焊接到结构化金属箔706的第二表面707。也就是说,向每个管芯710将被附着到的金属箔706的表面707施加管芯附着焊料712。然后在压力和温度下抵靠着金属箔706压挤(多个)管芯710,使得每个管芯710经由管芯附着焊料712的等温凝固所形成的高熔点相而被扩散结合到金属箔706,如先前在本文中所述。被扩散焊接到金属箔706的每个管芯710的表面可以具有金属化711,如先前在本文中所述。
图7包括模块700的拐角区域714中的金属箔706与一个管芯710之间的界面的分解图。根据本实施例,在将管芯710扩散焊接到金属箔706之前并未从金属箔706中去除管芯附着焊料712的未反应部分716。可以将任何类型的半导体管芯710扩散焊接到金属箔702,诸如类似于功率MOSFET或IGBT的功率半导体管芯、一个或多个逻辑管芯(例如驱动器、控制器)等。诸如FR4之类的层压件718被附着于结构化金属箔706的第二表面707。在层压件718上提供结构化金属层720 。层压件718包住半导体管芯710。
结构化金属箔706具有从层压件718向外延伸的侧壁722。结构化金属箔706的侧壁722未被层压件718覆盖并与金属复合材料衬底702的金属层704的侧壁708对准。层压件718具有在层压件718的相对主表面719、721之间延伸的边缘724。层压件718的边缘724未被金属覆盖。
一个或多个第一微过孔连接726可以通过层压件718从与结构化金属箔706相对的管芯710的表面处的管芯端子728延伸到背对金属复合材料衬底702的层压件718的表面719上的结构化金属层720。第一微过孔连接726在与金属复合材料衬底702相对的管芯710的表面处提供用于管芯端子728的外部电接触的点。
一个或多个第二微过孔连接730通过层压件718从结构化金属箔706延伸到背对金属复合材料衬底702的层压件718的表面719上的结构化金属层720。第二微过孔连接730在被扩散焊接到金属箔706的管芯710的表面处提供用于端子(如果提供的话)的外部电接触的点。如果管芯710中的一个或多个在此表面处不具有端子(例如在横向晶体管管芯的情况下)的话,则可以省略第二微过孔连接730。金属复合材料衬底702的金属层704在管芯710的操作期间充当热沉,通过结构化金属箔706从管芯710消散热量。
图8图示出根据图3的方法制造的半导体模块800的另一实施例的截面图。图8中所示的实施例类似于图7中所示的实施例,然而,管芯附着焊料712的未反应部分716在管芯710到金属箔706的扩散焊接之前被从金属箔706去除,如在图8的分解图中更详细地示出的。
为了便于描述而使用诸如“之下”、“下面”、“下”、“之上”、“上”等空间相对术语来解释一个元件相对于第二元件的定位。除了与在图中所描述的那些不同的取向之外,这些术语意图还涵盖器件的不同取向。此外,还使用诸如“第一”、“第二”等术语来描述各种元件、区域、部分等,并且也并不意图是限制性的。遍及本描述相似的术语指的是相似的元件。
如本文所使用的,术语“具有”、“包含”、“包括”、“含有”等是开放式术语,其指示所述元件或特征的存在,但不排除附加元件或特征。冠词“一”、“一个”和“该”意图包括复数以及单数,除非上下文清楚地另外指明。
着眼于上述变化和应用的范围,应理解的是本发明不受前述描述的限制,也不受附图的限制。更确切地说,仅仅由以下权利要求及其法律等价物来限制本发明。
Claims (23)
1.一种制造半导体模块的方法,该方法包括:
提供包括被附着于金属层的金属箔的金属复合材料衬底,该金属箔比金属层更薄且包括与之不同的材料;
在将金属箔结构化之前将多个半导体管芯的第一表面附着于金属箔;
将被附着于金属箔的半导体管芯装入电绝缘材料中;
在用电绝缘材料包住半导体管芯之后将金属层和金属箔结构化,使得电绝缘材料的表面区没有金属箔和金属层;以及
沿着没有金属箔和金属层的表面区划分电绝缘材料以形成单个模块。
2.权利要求1的方法,其中,所述金属层是具有在50 µm和200 µm之间的厚度的Al层,并且金属箔是具有在3 µm和100 µm厚之间的厚度的Cu箔。
3.权利要求1的方法,其中,在将金属箔结构化之前将管芯的第一表面附着于金属箔包括将管芯的第一表面扩散焊接到金属箔。
4.权利要求1的方法,其中,在将金属箔结构化之前将管芯的第一表面附着于金属箔包括将管芯的第一表面焊接、烧结或粘合到金属箔。
5.权利要求1的方法,其中,在将金属箔结构化之前将管芯的第一表面附着于金属箔包括:
用比金属箔和金属层熔点更低的焊料来涂敷与金属层相对的金属箔表面;以及
经由焊料将半导体管芯的第一表面扩散焊接到金属箔,包括焊料到高熔点相的等温凝固。
6.权利要求5的方法,还包括:
在将半导体管芯的第一表面扩散焊接到金属箔之后且在将半导体管芯装入电绝缘材料中之前从金属箔中去除焊料的未反应部分。
7.权利要求1的方法,其中,所述电绝缘材料是层压件。
8.权利要求1的方法,其中,在用电绝缘材料包住半导体管芯之后将金属层和金属箔结构化,使得电绝缘材料的表面区没有金属箔和金属层包括:
掩蔽金属层,使得金属层的区域被暴露;
去除金属层的暴露区,使得金属箔的区域被暴露;以及
使用剩余金属层作为掩模来去除金属箔的暴露区。
9.权利要求1的方法,还包括:
形成一个或多个第一连接,其通过电绝缘材料从与第一表面相对的管芯的第二表面延伸到背对金属复合材料衬底的电绝缘材料的表面上的结构化金属层;以及
形成一个或多个第二连接,其通过电绝缘材料从金属箔延伸到背对金属复合材料衬底的电绝缘材料的表面上的结构化金属层。
10.一种半导体模块,包括:
金属复合材料衬底,包括被附着于结构化金属箔的第一表面的金属层,该结构化金属箔具有与第一表面相对的第二表面且比金属层更薄,该金属层具有从结构化金属箔的第一表面向外延伸的锥形侧壁;
至少一个半导体管芯,具有被附着于结构化金属箔的第二表面的第一表面;
电介质层,其被附着于结构化金属箔的第二表面并包住所述至少一个半导体管芯;以及
结构化金属层,其在背对金属复合材料衬底的电介质层的表面上,
其中,所述结构化金属箔具有从电介质层向外延伸的侧壁,结构化金属箔的侧壁未被电介质层覆盖且与金属复合材料衬底的金属层的侧壁对准,
其中,所述电介质层具有在电介质层的相对第一和第二主表面之间延伸的边缘,电介质层的边缘未被金属覆盖。
11.权利要求10的半导体模块,还包括:
一个或多个第一连接,其通过电介质层从与第一表面相对的所述至少一个半导体管芯的第二表面延伸到背对金属复合材料衬底的电介质层的表面上的结构化金属层。
12.权利要求11的半导体模块,还包括:
一个或多个第二连接,其通过电介质层从结构化金属箔延伸到背对金属复合材料衬底的电介质层的表面上的结构化金属层。
13.一种将半导体管芯附着到金属复合材料衬底的方法,所述方法包括:
提供包括被附着于金属层的金属箔的金属复合材料衬底,该金属箔比金属层更薄且包括与之不同的材料;
用比金属箔和金属层熔点更低的焊料来涂敷与金属层相对的金属箔表面;
经由焊料而将多个半导体管芯的第一表面焊接至金属箔,包括焊料到高熔点相的等温凝固;以及
在将半导体管芯的第一表面扩散焊接到金属箔之后将半导体管芯装入电绝缘材料中。
14.权利要求13的方法,还包括:
在将半导体管芯的第一表面扩散焊接到金属箔之前向与金属层相对的金属箔的表面施加焊膏层、烧结层、焊膏和胶粘剂中的一个或多个。
15.权利要求13的方法,还包括:
在将半导体管芯的第一表面扩散焊接到金属箔之后且在将半导体管芯装入电绝缘材料中之前从金属箔去除焊料的未反应部分。
16.权利要求13的方法,还包括:
在将半导体管芯的第一表面扩散焊接到金属箔之前向半导体管芯的第一表面施加金属化。
17.权利要求13的方法,还包括:
将金属层和金属箔结构化,使得电绝缘材料的表面区没有金属箔和金属层;以及
沿着没有金属箔和金属层的表面区划分电绝缘材料以形成单个模块。
18.权利要求17的方法,其中,将金属层和金属箔结构化,使得电绝缘材料的表面区没有金属箔和金属层包括:
在将半导体管芯装入电绝缘材料中之后掩蔽金属层,使得金属层的区域被暴露;
去除金属层的暴露区,使得金属箔的区域被暴露;以及
使用剩余金属层作为掩模来去除金属箔的暴露区。
19.权利要求13的方法,还包括:
在将半导体管芯的第一表面扩散焊接到金属箔之前将焊料结构化。
20.权利要求19的方法,还包括:
在将半导体管芯的第一表面扩散焊接到金属箔之前使用结构化焊料作为掩模将金属箔结构化。
21.权利要求20的方法,还包括:
在将半导体管芯的第一表面扩散焊接到金属箔之后且在将半导体管芯装入电绝缘材料中之前从金属箔去除结构化焊料的未反应部分。
22.权利要求13的方法,还包括:
在将管芯的第一表面扩散焊接到金属箔并用电绝缘材料包住半导体管芯之后从金属箔去除金属层。
23.权利要求13的方法,其中,所述金属层是具有在50 µm和200 µm之间的厚度的Al层,并且其中,金属箔是具有在3 µm和100 µm之间的厚度的Cu箔。
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US10679965B2 (en) * | 2015-02-04 | 2020-06-09 | Zowie Technology Corporation | Semiconductor package structure with preferred heat dissipating efficacy without formation of short circuit |
US10083888B2 (en) * | 2015-11-19 | 2018-09-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
EP3300105B1 (de) * | 2016-09-26 | 2022-07-13 | Infineon Technologies AG | Leistungshalbleitermodul und verfahren zur herstellung eines leistungshalbleitermoduls |
FR3061989B1 (fr) | 2017-01-18 | 2020-02-14 | Safran | Procede de fabrication d'un module electronique de puissance par fabrication additive, substrat et module associes |
US20180153951A1 (en) * | 2016-12-05 | 2018-06-07 | Mead Johnson Nutrition Company | Methods for Inducing Adipocyte Browning, Improving Metabolic Flexibility, and Reducing Detrimental White Adipocyte Tissue Deposition and Dysfunction |
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US11798924B2 (en) | 2020-06-16 | 2023-10-24 | Infineon Technologies Ag | Batch soldering of different elements in power module |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1190797A (zh) * | 1996-12-13 | 1998-08-19 | 国际商业机器公司 | 用于引线键合芯片返工及替换的散热片及封装结构 |
CN101980870A (zh) * | 2008-03-26 | 2011-02-23 | 泰克诺玛公司 | 制造层叠的电路板的方法 |
CN102244057A (zh) * | 2011-03-15 | 2011-11-16 | 日月光半导体制造股份有限公司 | 半导体封装及其制造方法 |
CN103563110A (zh) * | 2011-06-06 | 2014-02-05 | 奥斯兰姆奥普托半导体有限责任公司 | 用于制造光电子半导体器件的方法和这样的半导体器件 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070084719A1 (en) * | 2005-09-28 | 2007-04-19 | Wickersham Charles E Jr | Inertial bonding method of forming a sputtering target assembly and assembly made therefrom |
US7312519B2 (en) * | 2006-01-12 | 2007-12-25 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
US7759777B2 (en) | 2007-04-16 | 2010-07-20 | Infineon Technologies Ag | Semiconductor module |
DE102007017831B8 (de) | 2007-04-16 | 2016-02-18 | Infineon Technologies Ag | Halbleitermodul und ein Verfahren zur Herstellung eines Halbleitermoduls |
US8375577B2 (en) * | 2008-06-04 | 2013-02-19 | National Semiconductor Corporation | Method of making foil based semiconductor package |
US7836586B2 (en) * | 2008-08-21 | 2010-11-23 | National Semiconductor Corporation | Thin foil semiconductor package |
US7767495B2 (en) * | 2008-08-25 | 2010-08-03 | Infineon Technologies Ag | Method for the fabrication of semiconductor devices including attaching chips to each other with a dielectric material |
US9490193B2 (en) | 2011-12-01 | 2016-11-08 | Infineon Technologies Ag | Electronic device with multi-layer contact |
US9245868B2 (en) * | 2012-06-27 | 2016-01-26 | Infineon Technologies Ag | Method for manufacturing a chip package |
US8890301B2 (en) * | 2012-08-01 | 2014-11-18 | Analog Devices, Inc. | Packaging and methods for packaging |
-
2014
- 2014-02-10 US US14/176,621 patent/US10192849B2/en active Active
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2015
- 2015-02-10 DE DE102015101843.8A patent/DE102015101843B4/de active Active
- 2015-02-10 CN CN201510071017.0A patent/CN104835746B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1190797A (zh) * | 1996-12-13 | 1998-08-19 | 国际商业机器公司 | 用于引线键合芯片返工及替换的散热片及封装结构 |
CN101980870A (zh) * | 2008-03-26 | 2011-02-23 | 泰克诺玛公司 | 制造层叠的电路板的方法 |
CN102244057A (zh) * | 2011-03-15 | 2011-11-16 | 日月光半导体制造股份有限公司 | 半导体封装及其制造方法 |
CN103563110A (zh) * | 2011-06-06 | 2014-02-05 | 奥斯兰姆奥普托半导体有限责任公司 | 用于制造光电子半导体器件的方法和这样的半导体器件 |
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