CN104900623B - 露出管芯的功率半导体装置 - Google Patents

露出管芯的功率半导体装置 Download PDF

Info

Publication number
CN104900623B
CN104900623B CN201410167761.6A CN201410167761A CN104900623B CN 104900623 B CN104900623 B CN 104900623B CN 201410167761 A CN201410167761 A CN 201410167761A CN 104900623 B CN104900623 B CN 104900623B
Authority
CN
China
Prior art keywords
tube core
paddle board
power die
semiconductor package
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410167761.6A
Other languages
English (en)
Other versions
CN104900623A (zh
Inventor
徐艳博
王志杰
宗飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Priority to CN201410167761.6A priority Critical patent/CN104900623B/zh
Priority to US14/552,442 priority patent/US9613941B2/en
Publication of CN104900623A publication Critical patent/CN104900623A/zh
Application granted granted Critical
Publication of CN104900623B publication Critical patent/CN104900623B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32058—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15157—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

本发明涉及露出管芯的功率半导体装置。一种半导体封装件具有引线框和功率管芯。所述引线框具有第一管芯桨板，其具有一个空腔完全贯穿形成于其中。所述具有下表面的功率管芯且安装在所述第一管芯桨板上，使得所述下表面的第一部分使用无焊料管芯附接粘接剂附接到所述第一管芯桨板，以及所述下表面的第二部分未附接到所述第一管芯桨板，并邻接形成在所述第一管芯桨板中的所述空腔，使得所述第二部分暴露。

Description

露出管芯的功率半导体装置
技术领域
本发明一般地涉及使用表面安装技术(SMT)的半导体封装，且更具体地，涉及露出焊垫的封装的功率半导体装置。
背景技术
封装的功率半导体装置通常用于实现功率电子装置中的开关与整流器。为了组装典型的功率半导体封装件，使用焊料膏将功率管芯(die)安装在引线框管芯桨板(paddle)(也称为旗板(flag))上。然后，以相对高的温度(例如，＞350℃)将焊料膏回流以在功率管芯与管芯桨板之间形成机械接合。由于焊料相对好的导热性，在半导体装置运行期间，焊料充当热沉，发散从功率管芯发出的热。
在焊料回流以后，使用管芯附接环氧树脂将控制管芯安装到引线框的另一个管芯桨板，环氧树脂随后在烤箱中以较低的温度(例如，175。C)固化。然后，将功率管芯和控制管芯互相电连接，并使用接合线将其连接到引线框的金属引脚(lead)。
线附接之后，将组件(包括功率管芯、控制管芯、金属引脚以及接合线)大部分包封在模制料中，使引脚的远端暴露出来，然后固化模制料。包封后，将功率半导体封装件单颗化(将相邻的同时组装的装置分离的工艺)，得到准备用于安装在电路板上的功率半导体封装件。单颗化还包括切割和/或移除用于保持金属引脚在位的支撑结构。
需要执行两个分离管芯的附接工艺，一个用于使用焊料附接功率管芯，一个用于使用粘合剂附接控制管芯，这增加了组装工艺的时间和成本。因此，就使用单个管芯附接步骤组装功率半导体装置将是有利的。
概述
根据本公开的一个实施例，提供了一种半导体封装件，包括：引线框，包括第一管芯桨板，所述第一管芯桨板具有至少一个完全贯穿其形成的空腔；以及第一功率管芯，其包括下表面，其中所述功率管芯安装在所述第一管芯桨板上，使得：所述下表面的第一部分使用无焊料管芯附接粘接剂附接到所述第一管芯桨板；以及所述下表面的第二部分未附接到所述第一管芯桨板，邻接形成在所述第一管芯桨板中的所述空腔，使得所述第二部分暴露于所述空腔内的周围环境。
根据本公开的另一实施例，提供了一种组装半导体封装件的方法，所述方法包括：(a)提供包括第一管芯桨板的引线框，所述第一管芯桨板具有至少一个完全贯穿其形成的空腔；(b)提供包括下表面的第一功率管芯；(c)使用无焊料管芯附接粘接剂将所述功率管芯安装在所述第一管芯桨扳上，使得：所述下表面的第一部分被使用无焊料管芯附接粘接剂附接到所述第一管芯桨板；以及所述下表面的第二部分未附接到所述第一管芯桨板，邻接形成在所述第一管芯桨板中的所述空腔，使得所述第二部分暴露于所述空腔内的周围环境。
附图说明
通过例子说明本发明的实施例，并且其不受附图的限制，在附图中，相同的附图标记指示相似的元素。图中的元素用出于简单和清楚的目的而示出，并且并不必然按比例绘制。例如，为了清楚起见，层和区域的厚度可以被夸大。
图1A示出了根据本发明一个实施例的四方扁平无引脚(QFN)引线框的顶视图；
图1B示出了根据图1A的QFN引线框沿线A-A的截面侧视图；
图2示出了根据本发明一个实施例的用于组装功率半导体封装件的工艺的简化的流程图；
图3A示出了根据本发明一个实施例的功率四方扁平无引脚(PQFN)半导体封装件的顶视图；
图3B示出了图3A的PQFN半导体封装件的沿线B-B的截面侧视图；以及
图4示出了根据本发明一个实施例的安装在印刷电路板的一部分上的图3A和图3B的功率半导体封装件的简化的截面侧视图。
具体实施方式
这里公开了本发明的详细的说明性实施例。但是，这里公开的具体结构和功能细节仅仅是代表性的，用于描述本发明的示例实施例。本发明的实施例可以以多种替代形式实施，并且不应被解释成限制到仅仅这里提出的实施例。此外，这里使用的术语仅用于描述特定实施例的目的，而并非是对本发明示例实施例的限制。
如此处所用的，单数形式“一”和“所述”(″a″，″an″和″the″)意图也包括复数形式，除非上下文另外明确表明。还将进一步理解，词语“包含”、“具有”和/或“包括”指明所陈述的特征、步骤或组件的存在，但并不排除一个或多个其他特征、步骤或组件的存在或增加。还应该指出的是，在一些替代实现方式中，提到的功能-动作可以不按照图中的顺序发生。例如，连续示出的两幅图实际上可能基本同时地执行或者有时可以以相反的顺序执行，这取决于涉及到的功能/动作。
如在传统的功率半导体封装件的组装过程中的使用焊料膏将功率管芯安装在管芯桨板上具有几个缺点。首先，由于焊料回流的高温，必须在焊料回流以后安装控制管芯，并且固化相应的环氧树脂。因此，焊料回流产生额外步骤。
第二，高温回流可能引起焊料膏中的锡的扩散，从而污染功率管芯桨板周围的环境，包括控制管芯桨板、金属引脚以及其它接合表面。所述污染会引起模制料与引线框之间的分层，使得模制料与引线框分离。另外，所述分层可能还会导致接合线从其各自的接合表面脱离。发明人发现，该接合脱离尤其是对于引线框上的接合表面，诸如，(i)功率管芯桨板，(ii)下接合突部(down bond tab，其是功率管芯桨板的一部分)，以及(iii)与控制管芯关联的金属引脚，是一个问题。
因而，需要(i)简化功率半导体封装件组装工艺，以及(ii)消除与焊料膏高温回流相关的污染的可能性。但是，这些问题的解决也必须允许在半导体封装件的正常使用期间从功率管芯发出的热能够充分地散逸。
在以下的说明中，将理解，本发明的某些实施例涉及半导体封装件，其包括不使用焊料膏将管芯附接到引线框的管芯，以及不使用焊料膏组装半导体封装件的方法。在本发明的至少一些实施例中，所使用的某些特定管芯要求使用热沉以避免管芯的结温变得太高时造成的对管芯的损伤。一般地，无法保持管芯的结温低于最大结温会导致管芯损伤甚至失效。要求热沉的管芯包括(但不限于)如上文所描述的用在功率半导体装置中的所谓的“功率管芯”。在本发明的至少一些实施例中，所使用的某些特定管芯具有大于约1安培的驱动电流。
在本发明一个实施例中，一种半导体封装件包括引线框和第一管芯。所述引线框包括第一管芯桨板，其具有至少一个完全贯穿其形成的空腔。所述第一管芯包括下表面并且要求使用热沉以避免操作期间对管芯的损伤，所述第一管芯被安装到所述第一管芯桨板上，从而使得(i)所述下表面的第一部分使用无焊料管芯附接粘接剂附接到所述第一管芯桨板，以及(ii)所述下表面的第二部分未附接到所述第一管芯桨板，邻接形成在所述第一管芯桨板中的所述空腔，使得所述第二部分暴露于所述空腔内的周围环境。
本发明的另一个实施例是一种用于细装前述半导体封装件的方法。
图1A和1B分别示出了根据本发明一个实施例的四方扁平无引脚(QFN)引线框100的顶视图和A-A截面侧视图。QFN引线框100可以用于组装功率四方扁平无引脚(PQFN)半导体封装件，其中功率管芯不使用焊料膏安装。所述QFN引线框100由适当的导电金属或合金(例如但不限于，铜)的单个片制成。尽管未示出，但是引线框100与其他引线框一起制造在片上，并且使用锯切单颗化、刻蚀或者冲压将引线框100从其分离。
引线框100的周界通过金属边界102界定。在金属边界102内，，例如通过刻蚀和/或冲压金属片来形成金属图案。所述金属图案包括功率管芯桨板108、四个功率输入/输出(IO)引脚106、控制管芯桨板118、以及27个控制IO引脚114。这些组件被保持在一起并且使用连接条104连接到金属边界102。
功率管芯桨板108具有从其完全刻蚀贯穿的矩形空腔110，以及沿着所述空腔110的周界的凸缘112，其通过减小邻近空腔110的桨板的厚度形成。减小厚度例如可以通过刻蚀穿过所述功率管芯桨板108的路程的一部分以形成所述凸缘112。如将在下面进一步详细讨论的，当功率管芯(未示出)被附接到所述功率管芯桨板108时，从功率管芯发出的热能够散发到所述空腔110内的周围环境。
图2示出了根据本发明一个实施例的用于组装功率半导体封装件的工艺200的简化流程图。工艺200可以与图1A和1B的引线框100或者本发明的替代引线框一起使用，这从以下描述中将更加清楚。对于这里的讨论，结合其与引线框100的使用来描述工艺200。要进一步理解工艺200，请参考图3A和3B。
图3A和3B分别示出了根据本发明一个实施例的PQFN半导体封装件300的顶视图和B-B截面侧视图。图3A中，为了说明，PQFN半导体封装件300被示出而没有模制料318。
在步骤202，对引线框100执行引线框带载。在步骤204，将功率管芯304附接到引线框100的功率管芯桨板108。如图3B所示，功率管芯304的下表面316的小部分(即，外周界)支撑在功率管芯桨板108的凸缘112上。功率管芯304使用无焊料管芯附接粘接剂314附接到功率管芯桨板108，无焊料管芯附接粘接剂314施加于功率管芯304的周界周围。无焊料管芯附接粘接剂314可以是，但不限制于，管芯附接带、环氧树脂或其他基于非环氧树脂的粘结剂。
功率管芯304的下表面316的大部分(即，中心部)暴露与功率管芯桨板108的空腔110内的周围环境。下表面316的暴露允许从功率管芯304发出的热散发到空腔110内的周围环境中。此外，由于无焊料管芯附接粘接剂314没有施加到下表面316的中心，因此无焊料管芯附接粘接剂314不会作为妨碍从下表面316中心的散热的热障。
在步骤206，使用无焊料管芯附接粘接剂(未示出)将控制管芯310安装到控制管芯桨板118上。然后在步骤208，将用于功率管芯304的无焊料管芯附接粘接剂与用于控制管芯310的无焊料管芯附接粘接剂同时在烤箱中固化。因而，不需要对功率管芯304和控制管芯310分开的固化步骤。
在步骤210，使用楔接合(wedge bonding)工艺，通过四个接合线302将功率管芯304引线接合到四个金属引脚106。在步骤212，控制管芯310(i)通过27个接合线312引线接合到27个金属引脚114，(ii)通过13个接合线308引线接合到功率管芯304，以及(iii)使用球接合工艺通过接合线306引线接合到功率管芯桨板108的至少一个下接合突部116。
在步骤214，应用模制料318以包封引线框100的顶部、管芯304和310以及接合线302、306、308和312。注意，在步骤202中施加的引线框带(未示出)阻止了模制料包封功率管芯304的下表面316。在步骤216，从引线框100移除引线框带，以及在步骤218，执行模制后固化。最后，在步骤220，执行锯切单颗化，以将功率半导体封装件300与互连的引线框100的同一阵列上制造的其他功率半导体封装件(未示出)分离。
由于工艺200使用(i)无焊料管芯附接粘接剂314来附接功率管芯304，以及(ii)同时固化用于功率管芯304和控制管芯310的管芯附接粘合剂，因此可以以比可比的使用焊料膏和焊料回流安装功率管芯的现有技术的功率半导体封装件组装工艺少的步骤执行工艺200。
另外，因为工艺200不使用焊料膏和焊料回流来安装功率管芯304，因此消除了与焊料膏和焊料回流相关的污染问题。这些污染问题的消除也降低了模制料与引线框之间的分层的可能性。
图4示出了根据本发明一个实施例的安装在印刷电路板(PCB)400的一部分上的图3A和图3B的功率半导体封装件300的简化截面侧视图。如图所示，在功率半导体封装件300组装后，可以使用焊料膏402将功率半导体封装件300安装到PCB400上，焊料膏402填充空腔110。焊料膏402在功率半导体封装件300外面，并且与功率管芯304的下表面316接触，从而作为功率管芯304的热沉。由于在模制料施加(即，步骤214)后施加焊料膏402，因此焊料膏402不会污染功率半导体封装件300内的接合表面，例如下接合突部116、金属引脚106和114、或者控制管芯焊垫118。
注意，焊料膏402可以具有比上面描述的现有技术的管芯接合方法中使用的焊料膏的铅含量(例如，92.5％)低的铅含量(例如63％)。另外，用于焊料膏402的峰值回流温度(例如，260℃)可以比上述现有技术的管芯接合方法中用于回流焊料的峰值回流温度(350℃)低。
在替代实施例中，金属块(slug)(未示出)可以替代焊料膏402沉积到到PCB400上，并且功率半导体封装件300可以安装到PCB400上使得金属块支撑在空腔110内。
在功率半导体封装件300的空腔110被使用焊料膏402填充或者安装在金属块上后，功率半导体封装件300可以呈现出与那些现有技术的使用焊料膏安装功率管芯的功率半导体封装件的类似的传导散热特性。
一般地，图3A和3B所示的特定功率半导体封装件结构(包括引线框100结构)仅仅是示例性的，用于说明不使用焊料膏将功率管芯附接到功率管芯桨板。本发明的实施例不限于图3A和3B所示的特定封装结构。
因而，尽管本发明一个实施例被描述为使用QFN引线框实现，但是本发明的实施例不限于此。根据替代实施例，本发明可以使用其它类型的封装实现，包括但不限于：四方扁平封装(QFP)，以及小外形集成电路(SOIC)封装。
进一步地，根据本发明的替代实施例，功率管芯桨板可以具有不止一个形成于其中的空腔以用于散热。例如，在图1A中，可以以部分刻蚀的向下穿过空腔110的中心的条将空腔110分成两个空腔(即，右空腔和左空腔)。另外，功率管芯桨板可以具有一个或多个不同于图1A所示形状的空腔。例如，空腔可以是方形、圆形或任何其他适合的形状。
此外，尽管图3A和3B示出了一个实施例，其中功率管芯桨板108具有凸缘112以及功率管芯304支撑在凸缘112上，但是本发明的实施例不限于此。根据本发明的替代实施例，可以省略用于部分蚀刻来形成凸缘112的步骤，并且功率管芯304可以支撑在功率管芯桨板108的上表面的一部分上，该部分在其他方式中本来通过用于形成凸缘112的部分刻蚀而被移除。
将进一步理解，上面已经描述和示出了各部分的布置、细节和材料，以解释本发明的特质，本领域技术人员可以对细节、材料以及部件排列作出各种改变，而不脱离所附权利要求所表示的本发明的范围。例如，可以使用与上述讨论的不同的引线接合工艺(例如，接合线302可以使用球接合工艺形成，而非楔接合工艺)。再例如，形成在引线框上的金属图案可以不同于图1A中所示的(例如，引线框可以具有不同的金属引脚数量)。
这里对“一个实施例”(“one embodiment”)或实施例(“an embodiment”)的引述意味着，结合该实施例描述的特定特征、结构或特性可以被包括在本发明的至少一个实施例中。说明书不同地方出现的短语“在一个实施例中”并不必然都涉及同一实施例，并且也不表示单独的或替代的实施例就必然与其他实施例彼此互斥。这也一样适用于术语“实现方式”。
方位术语(例如，“下”、“上”、“水平”、“垂直”、“之上”、“之下”、“向上”、“向下”、“顶”、“下底”、“右”、“左”以及他们的派生词(例如，“水平地”、“垂直地”等))应当被解释为涉及所讨论的附图中示出的方位。这些方位术语是出于便于描述的目的，而不是要求装置以特定方位构造或操作。
除非有明确的相反说明，否则数值和范围被认为是近以的，就好像在数值或范围的值之前置有词语“约”或“近似”一样。
权利要求中的附图标号或附图参考标记用于标识所要求保护的主题的一个或多个可能的实施例，以便理解权利要求。这样的使用不应被认为是将这些权利要求的范围必然限定于对应附图所示的实施例。
应理解，这里提出的示例性方法的步骤并不必然要求以所描述的顺序执行，并且这些方法的步骤顺序应当理解为仅作为示范。同样地，在这些方法中可以包括附加的步骤，并且在符合本发明的各种不同实施例的方法中，某些步骤可以省略或组合。
尽管所附方法权利要求中的元素(如果有的话)被利用对应标记以特定顺序叙述，但是这些元素并不必然限于以该特定顺序实现，除非这种权利要求叙述以另外的方式暗示了用以实现这些元素中的一些或全部元素的特定顺序。
此外，对于本说明书的目的，术语“耦接”、“连接”意指本领域已知的或后来将开发的、允许能量在两个或多个要素之间传递的任何方式，并且尽管并不要求，但是也构思了插入一个或多个附加要素。相反，术语“直接耦合”、“直接连接”等意味着不存在这些附加要素。
本申请中权利要求涵盖的实施例限于这样的实施例：(1)通过本申请文件能够实现的，以及(2)对应于法定主题(statutoty subject matter)的。不能实现的实施例和对应于非法定主题的实施例如果落入权利要求的范围，则其被明确放弃。

Claims (12)

1.一种半导体封装件，包括：
引线框，包括第一管芯桨板，所述第一管芯桨板具有至少一个完全贯穿其形成的空腔；
第一功率管芯，其包括下表面，其中所述功率管芯安装在所述第一管芯桨板上，使得：
所述下表面的第一部分使用无焊料管芯附接粘接剂附接到所述第一管芯桨板；以及
所述下表面的第二部分未附接到所述第一管芯桨板，邻接形成在所述第一管芯桨板中的所述空腔，使得所述第二部分暴露于所述空腔内的周围环境；
多个接合线，其将所述功率管芯电连接到所述半导体封装件的所述引线框以及至少一个其他部件；以及
模制料，包封所述引线框的上表面、接合线以及所述功率管芯的上部；
其中在应用模制料后所述半导体封装件被使用焊料膏安装在印刷电路板上，其中所述焊料膏填充引线框空腔的至少一部分并且接触所述功率管芯的所述下表面的所述第二部分。
2.如权利要求1所述的半导体封装件，其中：
所述第一管芯桨板包括邻近所述空腔形成的凸缘，其中所述凸缘的厚度小于所述第一管芯桨板的厚度；以及
通过使用无焊料管芯附接粘接剂将所述下表面的所述第一部分附接到所述凸缘而将所述功率管芯安装在所述凸缘上。
3.如权利要求1所述的半导体封装件，其中所述无焊料管芯附接粘接剂是环氧树脂或管芯附接带。
4.如权利要求1所述的半导体封装件，其中：
所述引线框进一步包括第二管芯桨板；以及
所述半导体封装件进一步包括第二控制管芯，其被使用无焊料管芯附接粘接剂安装在所述第二管芯桨板上，其中所述第一管芯和所述第二管芯的所述无焊料管芯附接粘接剂同时固化。
5.如权利要求1所述的半导体封装件，其中所述功率管芯具有大于1安培的驱动电流。
6.如权利要求1所述的半导体封装件，进一步包括热沉，其附接到所述功率管芯的所述下表面的所述第二部分，其中所述热沉的外表面暴露。
7.一种组装半导体封装件的方法，所述方法包括：
(a)提供包括第一管芯桨板的引线框，所述第一管芯桨板具有至少一个完全贯穿其形成的空腔；
(b)提供包括下表面的第一功率管芯；
(c)使用无焊料管芯附接粘接剂将所述功率管芯安装在所述第一管芯桨板上，使得：
所述下表面的第一部分被使用无焊料管芯附接粘接剂附接到所述第一管芯桨板；以及
所述下表面的第二部分未附接到所述第一管芯桨板，邻接形成在所述第一管芯桨板中的所述空腔，使得所述第二部分暴露于所述空腔内的周围环境；
使用接合线将所述功率管芯电连接到所述半导体封装件的所述引线框以及至少一个其他部件；以及
应用模制料到所述半导体封装件以包封所述引线框的上表面的至少一部分、所述接合线以及所述功率管芯的上表面；
其中在应用模制料后，使用焊料膏将所述半导体封装件安装到印刷电路板，使得所述焊料膏填充引线框空腔的至少一部分并且接触所述功率管芯的所述下表面的所述第二部分。
8.如权利要求7所述的方法，其中：
移除所述第一管芯桨板的邻近所述空腔的材料以形成凸缘，其中所述凸缘的厚度小于所述第一管芯桨板的厚度；并且
安装所述功率管芯包括通过使用无焊料管芯附接粘接剂将所述下表面的所述第一部分附接到所述凸缘而将所述功率管芯安装在所述凸缘上。
9.如权利要求7所述的方法，其中所述无焊料管芯附接粘接剂是环氧树脂或管芯附接带。
10.如权利要求7所述的方法，其中：
步骤(b)进一步包括，提供第二控制管芯；以及
步骤(c)进一步包括，使用无焊料菅芯附接粘接剂将所述控制管芯安装到所述引线框的第二管芯桨板；并且
所述方法进一步包括，同时固化用于所述功率管芯和所述控制管芯的无焊料管芯附接粘接剂。
11.如权利要求7所述的方法，其中所述功率管芯具有大于1安培的驱动电流。
12.如权利要求7所述的方法，进一步包括：将热沉附接到所述功率管芯的所述下表面的所述第二部分，其中所述热沉填充所述空腔并且所述热沉的外表面暴露。
CN201410167761.6A 2014-03-06 2014-03-06 露出管芯的功率半导体装置 Active CN104900623B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201410167761.6A CN104900623B (zh) 2014-03-06 2014-03-06 露出管芯的功率半导体装置
US14/552,442 US9613941B2 (en) 2014-03-06 2014-11-24 Exposed die power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410167761.6A CN104900623B (zh) 2014-03-06 2014-03-06 露出管芯的功率半导体装置

Publications (2)

Publication Number Publication Date
CN104900623A CN104900623A (zh) 2015-09-09
CN104900623B true CN104900623B (zh) 2018-11-30

Family

ID=54018135

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410167761.6A Active CN104900623B (zh) 2014-03-06 2014-03-06 露出管芯的功率半导体装置

Country Status (2)

Country Link
US (1) US9613941B2 (zh)
CN (1) CN104900623B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015223775A1 (de) * 2015-11-30 2017-06-01 Continental Teves Ag & Co. Ohg Verfahren zum Herstellen eines Verbindungselements, Verbindungselement und Sensoranordnung
EP3432354B1 (en) * 2017-07-19 2022-01-19 Ampleon Netherlands B.V. Electrical component, device and package
CN112151513A (zh) 2019-06-27 2020-12-29 恩智浦美国有限公司 功率管芯封装
US11133241B2 (en) 2019-06-28 2021-09-28 Stmicroelectronics, Inc. Semiconductor package with a cavity in a die pad for reducing voids in the solder

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202288A (en) * 1990-06-01 1993-04-13 Robert Bosch Gmbh Method of manufacturing an electronic circuit component incorporating a heat sink
US7977773B1 (en) * 2006-07-17 2011-07-12 Marvell International Ltd. Leadframe including die paddle apertures for reducing delamination

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60239043A (ja) 1984-05-14 1985-11-27 Oki Electric Ind Co Ltd 半導体装置用パツケ−ジの製造方法
US5696666A (en) 1995-10-11 1997-12-09 Motorola, Inc. Low profile exposed die chip carrier package
US5905299A (en) 1996-01-05 1999-05-18 Texas Instruments, Inc. Thermally enhanced thin quad flatpack package
US6202288B1 (en) * 1997-12-26 2001-03-20 Tdk Corporation Method for manufacturing magnetic head suspension assembly with head IC chip
US6440779B1 (en) 2001-05-16 2002-08-27 Siliconware Precision Industries Co., Ltd. Semiconductor package based on window pad type of leadframe and method of fabricating the same
US6809408B2 (en) * 2002-01-31 2004-10-26 Siliconware Precision Industries Co., Ltd. Semiconductor package with die pad having recessed portion
TWI257693B (en) * 2003-08-25 2006-07-01 Advanced Semiconductor Eng Leadless package
MY139795A (en) 2004-11-09 2009-10-30 Freescale Semiconductor Inc Leadframe for a semiconductor device
US20070111399A1 (en) 2005-11-14 2007-05-17 Goida Thomas M Method of fabricating an exposed die package
US7772036B2 (en) 2006-04-06 2010-08-10 Freescale Semiconductor, Inc. Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing
FR2940521B1 (fr) * 2008-12-19 2011-11-11 3D Plus Procede de fabrication collective de modules electroniques pour montage en surface
US8222718B2 (en) 2009-02-05 2012-07-17 Fairchild Semiconductor Corporation Semiconductor die package and method for making the same
KR101977994B1 (ko) * 2013-06-28 2019-08-29 매그나칩 반도체 유한회사 반도체 패키지

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202288A (en) * 1990-06-01 1993-04-13 Robert Bosch Gmbh Method of manufacturing an electronic circuit component incorporating a heat sink
US7977773B1 (en) * 2006-07-17 2011-07-12 Marvell International Ltd. Leadframe including die paddle apertures for reducing delamination

Also Published As

Publication number Publication date
US20150255443A1 (en) 2015-09-10
CN104900623A (zh) 2015-09-09
US9613941B2 (en) 2017-04-04

Similar Documents

Publication Publication Date Title
US9029194B2 (en) Making an integrated circuit module with dual leadframes
US20010006259A1 (en) Semiconductor device and method of producing the same
CN104835746B (zh) 具有被结合到金属箔的半导体管芯的半导体模块
JP2005191240A (ja) 半導体装置及びその製造方法
US9029991B2 (en) Semiconductor packages with reduced solder voiding
KR20080073735A (ko) 상단 및 하단 노출 패키지 반도체 조립 장치 및 방법
CN104900623B (zh) 露出管芯的功率半导体装置
CN104854695A (zh) 具有印刷形成的端子焊盘的引线载体
JP2008135688A (ja) 半導体装置および半導体装置の製造方法
CN107636828A (zh) 集成的夹具和引线以及制作电路的方法
US11393699B2 (en) Packaging process for plating with selective molding
CN104576565A (zh) 具有散热体的半导体器件及其组装方法
JP2015144216A (ja) 半導体装置及びその製造方法
US8697496B1 (en) Method of manufacture integrated circuit package
US20230068748A1 (en) Leaded semiconductor device package
JP2002026044A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP4547252B2 (ja) 集積回路パッケージにおける半田接合信頼性を改善するシステム及び方法
JPH0473297B2 (zh)
TWI393227B (zh) 已封裝之積體電路及形成堆疊式積體電路封裝之方法
US10840172B2 (en) Leadframe, semiconductor package including a leadframe and method for forming a semiconductor package
US6312976B1 (en) Method for manufacturing leadless semiconductor chip package
JP2008060160A (ja) 樹脂封止型半導体装置の製造方法
JPH03286558A (ja) 半導体装置およびその製造方法並びにそれに使用されるリードフレーム
JPH09312372A (ja) 半導体装置の製造方法
JP6923299B2 (ja) 半導体装置及び半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: Texas in the United States

Applicant after: NXP America Co Ltd

Address before: Texas in the United States

Applicant before: Fisical Semiconductor Inc.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant