CN112151513A - 功率管芯封装 - Google Patents
功率管芯封装 Download PDFInfo
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- CN112151513A CN112151513A CN201910566612.XA CN201910566612A CN112151513A CN 112151513 A CN112151513 A CN 112151513A CN 201910566612 A CN201910566612 A CN 201910566612A CN 112151513 A CN112151513 A CN 112151513A
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- die
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- power die
- electrodes
- leads
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- 239000004593 Epoxy Substances 0.000 claims abstract description 17
- 150000001875 compounds Chemical class 0.000 claims abstract description 11
- 238000000465 moulding Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 16
- 239000002390 adhesive tape Substances 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000004891 communication Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 125000003700 epoxy group Chemical group 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract
一种功率管芯封装,包括引线框架,该引线框架具有功率引线在其一个侧面上以及信号引线在其一个或多个其他侧面上的旗座。功率管芯贴附于旗座的底表面并且以导电环氧树脂与功率引线电连接。控制管芯贴附于旗座的顶表面并且以接合线与信号引线电连接。成型化合物被提供用于密封管芯、接合线以及引线的近端部,而引线的远端部是暴露的,从而形成PQFN封装。
Description
技术领域
本发明涉及集成电路(IC)封装,并且更特别地涉及功率管芯封装。
背景技术
图1是常规的功率管芯封装10的横截面侧视图,该功率管芯封装10使用具有旗座(flag)12和围绕旗座12的引线14的引线框架来组装。功率管芯16用无铅管芯贴附粘合剂18贴附于旗座12的顶表面,并且控制管芯20用粘合剂膜22贴附于功率管芯18的顶表面。功率管芯16用粗的铝接合线24(例如,15密耳的直径)与第一组引线14电连接,而控制管芯20用细的铜接合线26(例如,1.5密耳的直径)与第二组引线14电连接。整个组件以密封剂28覆盖。密封剂28被设置用于保护管芯16和20以及线接合部免受破坏。
功率管芯16产生必须要消散掉的热量,所以旗座12由相对厚的铜片形成,并且管芯贴附粘合剂必须具有良好的热性能,这些因素增加了封装10的总成本。降低此类功率管芯封装的组装成本将是有利的。
附图说明
根据以下的详细描述、所附权利要求及附图,本发明的各个方面、特征和优点将变得完全清楚,在附图中相同的附图标记表示相似的或相同的元件。附图所示的某些元件可以被扩大,并因此不是按比例绘制,以便更清晰地呈现本发明
图1是常规的功率管芯封装的放大的横截面侧视图;
图2是根据本发明的一个实施例的功率管芯封装的放大的横截面侧视图;
图3是图2的功率管芯封装的组装过程的流程图;
图4A是图2的功率管芯封装的引线框架的俯视平面图,而图4B是沿着图4A的线A-A的侧视图;
图5A和5B是示出图3的组装过程中的功率管芯贴附步骤的俯视平面图和侧视图;
图6A和6B是示出图3的组装过程中的控制管芯贴附步骤的俯视平面图和侧视图;
图7A和7B是示出图3的组装过程中的线接合步骤的俯视平面图和横截面侧视图;
图8是示出图3的组装过程中的成型步骤的放大的横截面侧视图;
以及
图9A和9B是图2的功率管芯封装的俯视和仰视平面图。
具体实施方式
本文公开了本发明的详细说明性实施例。但是,本文所公开的具体结构和功能细节只是代表性的,是出于描述本发明的示例实施例的目的。本发明的实施例可以用许多可替换的形式来实现,而不应被理解为仅限定于本文所阐明的实施例。此外,本文所使用的术语只是为了描述特定的实施例,而并非意指对本发明的示例实施例的限定。
如本文所使用的,单数形式“一(a)”、“一个(an)”和“该(the)”意指同样包括复数形式,除非上下文另有明确说明。还应当理解,词语“包括”、“包括”、“具有”、“拥有”、“含有”和/或“含有”指明存在所述的特征、步骤或构件,但并不排除存在或添加一个或多个其它的特征、步骤或构件。还应当注意,在一些可替换的实现中,所指出的功能/行为可以不按照附图中指出的顺序出现。
在一个实施例中,本发明提供一种功率管芯封装,该功率管芯封装包括引线框架、控制管芯和功率管芯。引线框架包括具有用于容纳控制管芯的顶表面或上表面以及用于容纳功率管芯的底表面或下表面的旗座。引线框架还具有与旗座的第一侧面相邻且间隔开的多个功率引线以及与旗座的至少一个其他侧面相邻且间隔开的多个信号引线。功率引线具有靠近旗座的近端部以及与旗座间隔更远的远端部。控制管芯具有贴附于旗座的上表面的背面以及与背面相对的有源面,该有源面包括多个控制管芯电极。第一组控制管芯电极以第一接合线与所述多个信号引线电连接。功率管芯具有贴附于旗座的下表面的第一面。功率管芯具有多个功率管芯电极,所述多个功率管芯电极包括与多个功率引线电连接的第一组功率管芯电极。在其他实施例中,第二组控制管芯电极以第二接合线连接至第二组功率管芯电极,并且整个组件以成型化合物覆盖。
本发明还提供了用于组装功率管芯封装的方法,该方法包括提供具有旗座的引线框架,该旗座具有用于容纳控制管芯的顶表面或上表面以及用于容纳功率管芯的底表面或下表面。引线框架还具有与旗座的第一侧面相邻且间隔开的多个功率引线以及与旗座的至少一个其他侧面相邻且间隔开的多个信号引线。功率引线具有靠近旗座的近端部以及与旗座间隔更远的远端部。功率管芯的有源面贴附于旗座的下表面。功率管芯具有比旗座更大的占用面积(footprint),使得功率管芯的一部分悬于旗座之上,并且功率管芯的悬于旗座之上的部分具有多个功率管芯电极,所述多个功率管芯电极包括与功率引线的近端部接触且电通信的第一组功率管芯电极。控制管芯的背面贴附于旗座的上表面。与旗座的背面相对的控制管芯的有源面包括多个控制管芯电极。第一组控制管芯电极以第一接合线与所述多个信号引线电连接,并且然后旗座、功率引线的近端部、信号引线、控制管芯、功率管芯、功率引线与第一组功率管芯电极之间的电连接以及第一接合线用成型化合物来包裹,其中功率管芯的底表面暴露出来。
本发明提供了成本比目前可用的封装更低的功率管芯封装,因为引线框架更便宜并且不需要粗的铝接合线。另外,由于功率管芯的整个底表面没有贴附于旗座,因此要么可以使用成本更低的管芯贴附材料,要么需要较少的更昂贵的管芯贴附材料,所以将功率管芯贴附于旗座的成本较少。本发明的封装还可以具有比常规的功率管芯封装更好的热性能,因为功率管芯的底面是暴露的。
现在参照图2,示出了根据本发明的一个实施例的功率管芯封装100的横截面侧视图。功率管芯封装100包括具有旗座102的引线框架,该旗座102具有用于容纳控制管芯的顶表面或上表面104以及用于容纳功率管芯的底表面或下表面106。引线框架还具有与旗座102的第一侧面相邻且间隔开的多个功率引线108以及与旗座102的至少一个其他侧面相邻且间隔开的多个信号引线110。功率引线108具有靠近旗座102的近端部112以及与旗座102间隔更远的远端部114。
控制管芯116具有贴附于旗座102的上表面104的背面以及与其背面相对的有源面,该有源面包括多个控制管芯电极。第一组控制管芯电极与所述多个信号引线110电连接。在目前优选的实施例中,第一多个控制管芯电极以第一接合线118连接至信号引线110。第一接合线118可以包括铜的、金的或其他导电金属的线,如在本技术领域已知的并且使用市场上可购得的线接合设备连接至管芯电极和引线框架引线110。
功率管芯120具有贴附于旗座102的下表面106的第一面或有源面。功率管芯120具有在其有源面上的多个功率管芯电极,所述多个功率管芯电极包括与多个功率引线108电连接的第一组功率管芯电极。更特别地,根据本发明的目前优选的实施例,功率引线108的近端部112与第一组功率管芯电极直接接触。
控制管芯116以管芯贴附材料122贴附于管芯旗座102的上表面104,管芯贴附材料122诸如管芯贴附环氧树脂或管芯贴附粘合剂胶带,这两种都是本技术领域已知的且在市场上可购得的。功率管芯120以导电环氧树脂124贴附于管芯旗座102的下表面106。功率引线108的近端部112也以导电环氧树脂126连接至第一组功率管芯电极。导电环氧树脂124和126优选地包括相同的材料。管芯贴附材料122能够是导电的或者不导电的,而环氧树脂124和126是导电的环氧树脂。合适的导电的和非导电的环氧树脂是本领域技术人员所了解的且容易在市场上购得。
从图2中能够看出,信号引线110和功率管芯引线108的远端部114位于第一平面A-A中,而功率管芯引线108的近端部112和旗座102位于第二平面B-B中。第二平面B-B平行于第一平面A-A且与其间隔开,使得功率管芯引线108的近端部112安置于第一组功率管芯电极的顶部上且与其电接触。
在图2中还可以看出,功率管芯120具有比旗座102更大的占用面积,使得功率管芯120的包括第一组功率管芯电极的一部分悬于旗座102之上。然后,功率引线108的近端部112能够接触第一组功率管芯电极,但仍然与旗座102间隔开。在旗座102与功率引线108的近端部112之间的间隔内,功率管芯120的表面是暴露的,并且还有位于该暴露间隔内的第二组功率管芯电极。
贴附于旗座102的顶表面104的控制管芯116优选具有比旗座102更小的占用面积,如图2所示。尽管图2并不一定按比例绘制,但是它表明,在该优选实施例中,控制管芯116比功率管芯120和旗座104小。控制管芯116还具有以第二接合线128与第二组功率管芯电极电连接的第二组电极。
成型化合物130包裹旗座102、功率引线108的近端部112、信号引线110、控制管芯116、功率管芯120,以及第一和第二接合线118和128。成型化合物130保护管芯116和120、接合线118和128以及线接合部免受破坏。成型化合物130还界定了封装体。功率引线108的远端部114、信号引线110的侧表面和底表面以及功率管芯120的底面是暴露的。引线108和110的暴露部分允许到器件100的外部电连接。
在一个实施例中,金属涂层132(诸如焊料层)形成于功率管芯120的暴露的底表面之上。金属涂层132的目的是为了在表面安装之前的器件级的电测试和处理过程中防止功率管芯的底部受到机械损坏。
引线框架可以由本技术领域所已知的铜或其他导电金属形成,并且可以按照条带或陈列的形式来提供。引线框架或者只是引线框架的选定部分(如引线的外部引线区)可以用另一种金属或合金来涂覆或电镀,以抑制引线框架暴露于外部环境时的腐蚀。引线框架可以通过切割、冲压(stamp)和/或蚀刻铜片或铜箔来形成。在一个实施例中,管芯容纳区102包括管芯衬垫,也就是,管芯116和120安装于其上的固态铜件。在一些实施例中,可以将管芯衬垫制造得相对厚,使得它能够充当热沉,吸收由管芯116和120产生的热量。
控制管芯116可以包括数字电路,其用于接收来自其他集成电路芯片的信号以及给其他集成电路芯片提供信号,而功率管芯120可以包括模拟电路,诸如功率MOSFET。在一个实施例中,器件100可以包括能够用来例如控制汽车前照灯的集成电路,诸如,可从荷兰的NXP有限公司(NXP B.V.)购得的NXP eSwitch(eXtreme Switch),其包括以下特征,诸如,具有菊花链(daisy chain)能力的16位SPI、具有外部或内部时钟的PWM模块、智能过流关闭、过温保护、自动重试大部分保护措施、故障安全模式、灯泡或LED的开路负载保护、电池短路检测以及模拟电流和温度反馈。
图3是用于组装图2所示的封装10的方法的流程图150,并且图4-8示出了组装过程的不同阶段中的封装10。
在预备步骤152中,执行晶圆切割,以提供多个功率管芯和多个控制管芯。在目前优选的实施例中,功率管芯和控制管芯在单独的晶圆上制造,但是切割步骤可以在同一组装现场对两个晶圆进行。另外,在步骤152,示出了如同图4A和4B中所示的以170表示的引线框架那样的引线框架。更特别地,图4A和4B示出了根据本发明的一个实施例的引线框架170的一部分。引线框架170是引线框架阵列的一部分,使得多个封装可以同步组装。引线框架170包括旗座172、多个功率引线174和多个信号引线176。旗座172具有用于容纳控制管芯的上表面178和用于容纳功率管芯的下表面180。功率引线174位于旗座172的第一侧面182的邻近处且与其间隔开,而信号引线176与旗座172的至少一个其他侧面邻近且与其间隔开。在所示的实施例中,信号引线176被布置于旗座172的其余三个侧面周围。功率引线174具有靠近于旗座172的近端部184以及与旗座172间隔更远的远端部186。从图4B中可以看出,旗座172和功率引线174的近端部184位于第一平面中,并且信号引线176和功率引线174的远端部186位于第二平面中,第二平面与第一平面间隔开且与其平行。引线框架170可以形成于组装现场或者由引线框架供应商在a处形成,并且如同前面所讨论的,引线框架可以镀上一种或多种金属或者合金,以防止被腐蚀。
在步骤154,将功率管芯贴附于引线框架。在目前优选的实施例中,引线框架170被翻转过来,使得底面180朝上,如图4A和4B所示,并且导电环氧树脂188被布置于旗座172的底面180和功率引线174的近端部184上。导电环氧树脂188可以按照X图形或者作为滴或涂片(blob or smear)(非特别的形状)分配到旗座172和功率引线174上。
图5A和5B示出了贴附于旗座172的下表面或底表面的功率管芯190的有源面。功率管芯190具有比旗座172更大的占用面积,使得功率管芯190的一部分悬于旗座172之上,并且功率管芯190的悬于旗座172之上的部分具有包括第一组功率管芯电极的多个功率管芯电极,第一组功率管芯电极与功率引线174的近端部184接触且电通信。因而,功率管芯190跨过旗座172与功率引线174之间的间隔,并且安置于旗座172和功率引线174两者上。参照图5B,尽管该图的右手侧示出旗座172的侧面和功率管芯190的侧面没有对准,但是并不要求旗座172与功率管芯不对准。例如,如果旗座172不太宽,使得它的侧面与功率管芯190的侧面对齐,则引线框架将会使用更少的金属。
在步骤156(图3),在贴附了功率管芯190之后,胶带192被放置于功率引线174的远端部186、功率管芯190和信号引线176之上,如图6B所示。组件然后被翻转,并且在步骤158,执行控制管芯194的贴附。如图6A和6B所示,控制管芯194以管芯贴附膜或管芯贴附环氧树脂196贴附于旗座172的上表面178。控制管芯194在其有源面朝上的情况下贴附,使得多个第一电极198和多个第二电极200是可接近的。功率管芯190还具有位于功率管芯190上的且在旗座172与功率引线174之间的间隙内可见的多个第二电极202。
在步骤160,在第一组控制管芯电极198与信号引线176之间制作第一电连接,并且在第二组控制管芯电极200与功率管芯190之间制作第二电连接。更特别地,如图7A和7B所示,第一组控制管芯电极198以第一接合线204与多个信号引线176电连接,并且第二组控制管芯电极200以第二接合线206与第二组功率管芯电极202电连接。第一和第二接合线204和206可以包括相同的线类型,例如,1.5密耳的铜线。
在线接合之后,在步骤162(图3),成型化合物208形成于管芯190和194、第一和第二接合线204和206以及功率引线174和信号引线176的部分之上,如所示图8。成型化合物208可以使用本技术领域所已知的“成型阵列封装(molded array packaging)”或MAP工艺形成于组件之上。在成型之后,功率管芯190的底表面是暴露的,如同信号引线176的部分以及功率引线174的远端部186那样。此外,在成型之后,胶带192被去除。
图9A和9B是根据上述方法组装的功率器件212的俯视和仰视平面图。在俯视图(图9A)中,成型化合物208、功率引线174、和信号引线176的部分是可见的,而在仰视图(图9B)中,可见功率引线174和信号引线176的更多。功率管芯190的底表面也是暴露的,如同以上参照图8所指出的。但是,在一些实施例中,功率管芯190的暴露的底表面以导电材料(诸如金或焊料)涂覆。在图9B中,功率管芯190的底表面以金210涂覆。在需要时,可以执行裁剪和成形操作,以完成方形扁平无引线(QFN)封装(Quad Flag No-leads(QFN)package)的形成。
现在应当清楚,本发明包括用于PQFN型封装的引线框架。PQFN具有用于给出功率器件的较低的零件和组装成本,因为引线框架可以使用冲压工艺来形成,其成本低于需要蚀刻的工艺。而且,旗座和引线可以具有相同的厚度,因而成本不会因为具有更复杂的引线框架结构而增加。功率管芯直接连接至功率引线,所以不需要单独的线接合工艺,该线接合工艺使用昂贵的粗铝线。两个管芯同样适合于引线框架旗座的相对面。
本文对“一个实施例”或“实施例”的引用意指结合实施例所描述的特定的特征、结构或特性能够包括于本发明的至少一个实施例中。出现于本说明书的不同地方的短语“在一个实施例中”并不一定全都参考同一实施例,单独的或可替换的实施例也不一定与其他实施例相互排斥。这同样适用于词语“实现”。
出于本描述的目的,词语“耦合”、“耦接”、“耦接的”、“连接”、“正连接”或“连接的”指的是本技术领域所已知的或以后将开发出的任何形式,其中允许能量在两个或更多个元件之间传输,并且一个或多个附加的元件的介入是可预期的,尽管不是必要的。词语“直接耦接”、“间接耦接”等意指,已连接的元件要么是接触的,要么经由用于传输能量的导体来连接。
Claims (12)
1.一种功率管芯封装,包括:
引线框架,所述引线框架具有包括用于容纳控制管芯的上表面和用于容纳功率管芯的下表面的旗座,与所述旗座的第一侧面相邻且间隔开的多个功率引线以及与所述旗座的至少一个其他侧面相邻且间隔开的多个信号引线,其中所述功率引线具有靠近于所述旗座的近端部以及与所述旗座间隔更远的远端部;
控制管芯,具有贴附于所述旗座的所述上表面的背面以及与所述背面相对的包括多个控制管芯电极的有源面,其中第一组控制管芯电极与所述多个信号引线电连接;以及
功率管芯,具有贴附于所述旗座的所述下表面的第一面,其中所述功率管芯具有多个功率管芯电极,所述多个功率管芯电极包括与所述多个功率引线电连接的第一组功率管芯电极。
2.根据权利要求1所述的功率管芯封装,其中:
所述第一组控制管芯电极以第一接合线与所述多个信号引线电连接,并且
所述第一组功率管芯电极与所述多个功率管芯引线直接接触并且以导电环氧树脂贴附于所述多个功率管芯引线。
3.根据权利要求2所述的功率管芯封装,还包括与所述第一组控制管芯电极不同的第二组控制管芯电极,所述第二组控制管芯电极以第二接合线与不同于所述第一组功率管芯电极的第二组功率管芯电极电连接。
4.根据权利要求1所述的功率管芯封装,其中所述信号引线以及所述功率管芯引线的所述远端部位于第一平面中,并且所述功率管芯引线的近端部和所述旗座位于第二平面中,其中所述第二平面平行于所述第一平面且与所述第一平面间隔开,使得所述功率管芯引线的所述近端部安置于所述第一组功率管芯电极的顶部上并且与其电接触。
5.根据权利要求1所述的功率管芯封装,其中:
所述功率管芯的有源表面以导电环氧树脂贴附于所述旗座的所述下表面,并且所述功率管芯引线的所述近端部也以导电环氧树脂贴附于所述第一组功率管芯电极,并且
所述控制管芯以管芯贴附粘合剂胶带贴附于所述旗座。
6.根据权利要求1所述的功率管芯封装,其中所述旗座是矩形的,并且所述功率引线与所述旗座的所述第一侧面相邻,并且所述信号引线间隔于所述旗座的其余的三个其他的面周围。
7.根据权利要求1所述的功率管芯封装,还包括成型化合物,所述成型化合物包裹着所述旗座、所述功率引线的所述近端部、所述信号引线、所述控制管芯、所述功率管芯,以及在所述功率引线与所述功率管芯电极之间的和在所述信号引线与所述第一组控制管芯电极之间的电连接,其中所述功率管芯的底表面是暴露的。
8.根据权利要求7所述的功率管芯封装,还包括形成于所述功率管芯的暴露的底表面之上的焊料层,并且其中所述封装包括方形扁平无引线(QFN)封装。
9.根据权利要求8所述的功率管芯封装,其中:
所述第一组控制管芯电极以第一接合线与所述多个信号引线电连接;
与所述第一组控制管芯电极不同的第二组控制管芯电极以第二接合线与不同于所述第一组功率管芯电极的第二组功率管芯电极电连接;
所述功率管芯具有比所述旗座更大的占用面积,使得所述功率管芯的包括所述第一组功率管芯电极的部分悬于所述旗座之上;
所述第一组功率管芯电极与所述多个功率管芯引线直接接触;
所述信号引线以及所述功率管芯引线的所述远端部位于第一平面中,并且所述功率管芯引线的近端部和所述旗座位于第二平面中,其中所述第二平面平行于所述第一平面且与所述第一平面间隔开,使得所述功率管芯引线的所述近端部安置于所述第一组功率管芯电极的顶部上并且与其电接触;
所述功率管芯的有源表面以导电环氧树脂贴附于所述旗座的所述下表面,并且所述功率管芯引线的所述近端部也以导电环氧树脂贴附于所述第一组功率管芯电极;
所述控制管芯具有比所述旗座更小的占用面积,使得所述控制管芯被布置于所述旗座的所述占用面积内;并且
所述控制管芯以管芯贴附粘合剂胶带贴附于所述旗座。
10.一种用于组装功率管芯封装的方法,包括:
提供引线框架,所述引线框架包括具有用于容纳控制管芯的上表面和用于容纳功率管芯的下表面的旗座,与所述旗座的第一侧面相邻且间隔开的多个功率引线以及与所述旗座的至少一个其他的侧面相邻且间隔开的多个信号引线,其中所述功率引线具有靠近于所述旗座的近端部以及与所述旗座间隔更远的远端部;
将功率管芯的有源面贴附于所述旗座的所述下表面,其中所述功率管芯具有比所述旗座更大的占用面积,使得所述功率管芯的一部分悬于所述旗座之上,并且其中所述功率管芯的悬于所述旗座之上的部分具有多个功率管芯电极,所述多个功率管芯电极包括与所述功率引线的所述近端部接触且与其电通信的第一组功率管芯电极;
将控制管芯的背面贴附于所述旗座的所述上表面,其中所述控制管芯的与所述旗座的所述背面相对的有源面包括多个控制管芯电极;
以第一接合线将第一组控制管芯电极与所述多个信号引线电连接;
以成型化合物包裹着所述旗座、所述功率引线的所述近端部、所述信号引线、所述控制管芯、所述功率管芯、在所述功率引线与所述第一组功率管芯电极之间的电连接以及所述第一接合线,其中所述功率管芯的底表面是暴露的。
11.根据权利要求10所述的方法,还包括:
在所述功率管芯的暴露的底表面之上形成焊料层;并且
以第二接合线将第二组控制管芯电极与第二组功率管芯电极电连接。
12.根据权利要求10所述的方法,其中:
所述信号引线以及所述功率管芯引线的所述远端部位于第一平面中,并且所述功率管芯引线的近端部和所述旗座位于第二平面中;
所述第二平面平行于所述第一平面且与所述第一平面间隔开,使得所述功率管芯引线的所述近端部安置于所述第一组功率管芯电极的顶部上并且与其电接触;并且
所述功率管芯以导电环氧树脂贴附于所述旗座,并且所述控制管芯以非导电管芯贴附粘合剂贴附于所述旗座。
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