CN111128943A - 受防护半导体装置和其引线框架 - Google Patents

受防护半导体装置和其引线框架 Download PDF

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CN111128943A
CN111128943A CN201911050278.9A CN201911050278A CN111128943A CN 111128943 A CN111128943 A CN 111128943A CN 201911050278 A CN201911050278 A CN 201911050278A CN 111128943 A CN111128943 A CN 111128943A
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die
receiving area
leads
die receiving
lead
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阮丽霏
傅梓淞
迈克尔·B·文森特
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Abstract

使用引线框架组装一种受防护半导体装置，该引线框架具有管芯收容区域、围绕该管芯收容区域安置的引线和形成于该管芯收容区域中的可弯曲带材。每一引线具有内引线末端和外引线末端，该内引线末端与该管芯收容区域的侧部中的一个侧部间隔开但靠近该侧部，该外引线末端远离该管芯收容区域的该侧部。IC管芯附接到该管芯收容区域并且电连接到该等引线的该等内引线末端。包封物形成于该管芯和电连接件上方并且形成主体。该带材被弯曲成竖直延伸到该主体的顶侧。封盖形成于该主体的该顶侧上并且接触该竖直带材的远端。

Description

受防护半导体装置和其引线框架
技术领域
本发明大体上涉及半导体装置和半导体装置封装，且更具体地说，涉及具有电磁干扰防护的半导体装置封装。
背景技术
在多个高密度电子装置应用中使用半导体装置封装或集成电路芯片载体。通过用环氧树脂材料进行包封或围绕集成电路或半导体装置转移模制热塑树脂，保护该等装置不受外部环境的影响。然而，随着电路变得越来越小，越来越密集，并且在更高频率下和更恶劣环境中操作，日益需要防护电路免受辐射，例如射频干扰(radio frequencyinterference，RFI)和电磁干扰(electromagnetic interference，EMI)。举例来说，需要保护蜂窝电话和其它移动装置免受这类辐射。还需要防护例如安装在靠近火花塞处的微控制器等汽车电路，且塑料包封物不提供EMI或RFI防护。
常规防护系统使用导电金属罩壳环绕需防护的电路。该罩壳保护内部电路免受EMI和RFI并且防止该电路产生的RFI或EMI信号流失。另一解决方案是在模制封装之前或之后将金属盖放在半导体装置上方。这种解决方案适用于具有大半导体管芯(即，至少一平方英寸)的球栅阵列(ball grid array，BGA)。又一解决方案是在包封的装置上方提供金属涂层。然而，所有这些解决方案都具有一些缺陷。举例来说，使用导电金属罩壳增加封装的整体大小并且需要额外焊接步骤来将金属护罩附接到该装置，且该额外焊接过程产生的热量可能危害该装置。
因此，需要可在具有任何半导体管芯大小的多种封装中使用的具成本效益的组件层级防护。
发明内容
根据本发明的第一方面，提供一种制品，包括：
管芯收容区域、多个引线和带材，所述引线安置于所述管芯收容区域的至少一侧上并且大体垂直于所述管芯收容区域的所述至少一侧，其中所述多个引线中的每一引线具有内引线末端和外引线末端，所述内引线末端与所述管芯收容区域的所述至少一侧间隔开但靠近所述管芯收容区域的所述至少一侧，所述外引线末端远离所述管芯收容区域的所述至少一侧，所述带材形成于所述管芯收容区域中并且可弯曲到大致竖直位置以用于连接到封装封盖。
在一个或多个实施例中，所述带材沿着所述管芯收容区域的一侧形成。
在一个或多个实施例中，所述带材具有0.05mm到0.20mm的宽度，以及0.50mm到2.0mm的长度。
在一个或多个实施例中，所述制品包括引线框架，且所述引线框架包括镀覆有非腐蚀性金属或金属合金的铜。
在一个或多个实施例中，所述管芯收容区域为矩形。
在一个或多个实施例中，所述多个引线包括安置于所述管芯收容区域的侧部中的每一侧部上的引线。
在一个或多个实施例中，所述制品进一步包括：
第一集成电路管芯，其附接到所述管芯收容区域并且电连接到所述多个引线的所述内引线末端；和
包封物，其形成于所述第一管芯上方，电连接件于所述第一管芯与所述多个内引线末端之间，其中所述包封物形成主体，且其中所述带材竖直弯曲并且延伸到所述主体的上边缘。
在一个或多个实施例中，所述制品进一步包括形成于所述主体的所述上边缘上并且接触所述带材的封盖。
在一个或多个实施例中，所述封盖包括涂于所述主体的顶边缘上的金属溅射。
在一个或多个实施例中，所述第一管芯通过接合线电连接到所述内引线末端。
在一个或多个实施例中，所述制品进一步包括第二集成电路管芯，所述第二集成电路管芯附接到所述第一管芯的顶表面并且电连接到所述第一管芯和所述多个引线中的至少一个。
在一个或多个实施例中，所述第一管芯包括微控制器单元，且所述第二管芯包括压力传感器，在所述第二管芯上方的所述包封物中存在空隙，且在所述封盖中存在与所述空隙连通的孔，使得所述第二管芯借助于所述孔和所述空隙暴露于所述主体外部的周围环境。
在一个或多个实施例中，所述封盖通过导电粘附剂附接到所述主体的所述上边缘，且竖直带材接触所述导电粘附剂。
根据本发明的第二方面，提供一种受防护半导体装置，包括：
引线框架，其包括管芯收容区域、多个引线和带材，所述引线安置于所述管芯收容区域的至少一侧上并且大体垂直于所述管芯收容区域的所述至少一侧，其中所述多个引线中的每一引线具有内引线末端和外引线末端，所述内引线末端与所述管芯收容区域的所述至少一侧间隔开但靠近所述管芯收容区域的所述至少一侧，所述外引线末端远离所述管芯收容区域的所述至少一侧，所述带材形成于所述管芯收容区域中并且弯曲到大致竖直位置以用于连接到封装封盖；
第一集成电路管芯，其附接到所述管芯收容区域并且电连接到所述多个引线的所述内引线末端；
包封物，其形成于所述第一管芯和所述第一管芯与所述多个内引线末端之间的电连接件上方，其中所述包封物形成主体，且其中所述带材竖直延伸到所述主体的上边缘；和
封盖，其形成于所述主体的所述上边缘上并且接触竖直带材的远端。
在一个或多个实施例中，所述受防护半导体装置进一步包括第二集成电路管芯，所述第二集成电路管芯附接到所述第一管芯的顶表面并且电连接到所述多个引线和所述第一管芯中的至少一个，并且覆盖有所述包封物。
根据本发明的第三方面，提供一种组装受防护半导体装置的方法，包括：
提供引线框架，所述引线框架包括管芯收容区域、多个引线和带材，所述引线安置于所述管芯收容区域的至少一侧上并且大体垂直于所述管芯收容区域的所述至少一侧，其中所述多个引线中的每一引线具有内引线末端和外引线末端，所述内引线末端与所述管芯收容区域的所述至少一侧间隔开但靠近所述管芯收容区域的所述至少一侧，所述外引线末端远离所述管芯收容区域的所述至少一侧，所述带材形成于所述管芯收容区域中并且弯曲到大致竖直位置以用于连接到封装封盖；
将第一集成电路(IC)管芯附接到所述引线框架的管芯垫；
将所述第一IC管芯电连接到所述多个引线的所述内引线末端；
用模制化合物包封所述第一IC管芯、电连接件和所述引线框架，其中所述模制化合物形成主体，且其中所述多个引线的远端沿着所述主体的至少一个侧向侧暴露且竖直带材的远端在所述主体的顶表面暴露；和
在所述主体的所述顶表面上形成金属封盖，其中所述竖直带材的暴露的远端接触所述封盖。
在一个或多个实施例中，所述方法进一步包括：
将第二IC管芯附接到所述第一IC管芯的上表面并且将所述第二IC管芯电连接到所述第一IC管芯和所述多个引线的所述内引线末端中的至少一个，其中所述第二IC管芯覆盖有所述模制化合物。
在一个或多个实施例中，空隙形成于所述第二IC管芯上方且所述封盖包括与所述空隙连通的孔，使得所述第二IC管芯借助于所述孔和所述空隙暴露于周围环境。
在一个或多个实施例中，所述第一IC管芯是微控制器单元且所述第二IC管芯是压力传感器。
在一个或多个实施例中，所述封盖通过溅镀形成。
本发明的这些和其它方面将根据下文中所描述的实施例显而易见，且参考这些实施例予以阐明。
附图说明
从以下详细描述、所附权利要求书和附图将更全面地了解本发明的实施例。图式不一定按比例缩放，这是因为一些元件相较于其它元件可相对更小或更大，通过这类差异来突出本发明的特征。在图式中，相似元件符号识别类似或相同元件。
图1是根据本发明的实施例的半导体装置的放大横截面侧视图；
图2是用于形成图1的半导体装置的引线框架的俯视平面图；
图3是示出组装图1的半导体装置的方法的一系列横截面侧视图；和
图4是根据本发明的实施例的压力传感器半导体装置的放大横截面侧视图。
具体实施方式
本文公开本发明的详细说明性实施例。然而，出于描述本发明的例子实施例的目的，本文公开的具体结构和功能细节仅为代表性的。本发明可以许多替代形式体现并且不应被理解为仅限于本文所阐述的实施例。本文中所使用的术语仅仅是为了描述特定实施例，且并不希望限制本发明的例子实施例。
如本文中所使用，除非上下文另外明确指示，否则单数形式“一”和“该”意在也包括复数形式。另外应理解，术语“包括(comprises、comprising、includes和/或including)”指定所陈述特征、步骤或组件的存在，但是不排除一个或多个其它特征、步骤或组件的存在或添加。还应该注意，在一些替代的实施方案中，提到的功能/动作可不按图中所提到的次序出现。举例来说，取决于所涉及的功能性/动作，连续展示的两个图可实际上基本同时执行或有时可以相反次序执行。
本发明提供具有封盖的半导体装置，该封盖提供EMI和RFI防护。该装置形成有引线框架，该引线框架包括形成于引线框架的管芯垫中的竖直条带。竖直条带接触封盖并且与封盖电连通。在一个实施例中，本发明是一种制品，该制品包括管芯收容区域、安置于管芯收容区域的至少一侧且大体垂直于管芯收容区域的至少一侧的多个引线，以及形成于管芯收容区域中的带材，该带材可弯曲到大致竖直位置以用于连接到封装封盖。引线中的每一个引线具有内引线末端和外引线末端，该内引线末端与管芯收容区域的至少一侧间隔开但靠近该至少一侧，该外引线末端远离管芯收容区域的至少一侧。
在另一实施例中，本发明是包括引线框架、集成电路(integrated circuit，IC)管芯、包封物和封盖的受防护半导体装置。引线框架具有管芯收容区域、多个引线和带材，该等引线安置于管芯收容区域的至少一侧上并且大体垂直于管芯收容区域的至少一侧，该带材形成于管芯收容区域中并且弯曲到大致竖直位置以用于连接到封装封盖。引线中的每一个引线具有内引线末端和外引线末端，该内引线末端与管芯收容区域的至少一侧间隔开但靠近该至少一侧，该外引线末端远离管芯收容区域的至少一侧。IC管芯附接到管芯收容区域并且电连接到多个引线的内引线末端。包封物形成于第一管芯以及第一管芯与多个内引线末端之间的电连接件上方并且形成主体。带材竖直延伸到主体的上边缘。封盖形成于主体的上边缘上并且接触竖直带材的远端。
在又一实施例中，本发明提供组装受防护半导体装置的方法。该方法包括提供引线框架，该引线框架包括管芯收容区域、多个引线和带材，该等引线安置于管芯收容区域的至少一侧上并且大体垂直于管芯收容区域的至少一侧，该带材形成于管芯收容区域中并且弯曲到大致竖直位置以用于连接到封装封盖。引线中的每一个引线具有内引线末端和外引线末端，该内引线末端与管芯收容区域的至少一侧间隔开但靠近该至少一侧，该外引线末端远离管芯收容区域的至少一侧。该方法还包括将IC管芯附接到引线框架的管芯垫，将IC管芯电连接到多个引线的内引线末端，并且用模制化合物包封IC管芯、电连接件和引线框架。模制化合物形成主体，且在主体的一个或多个侧部暴露引线的远端并在主体的顶侧暴露竖直带材的远端。该方法还包括在主体的顶侧形成金属封盖。竖直带材的暴露远端接触封盖。
现在参考图1，示出根据本发明的实施例的封装半导体装置10的横截面侧视图。半导体装置10具有用塑料模制化合物形成的主体12和从壳体12向外延伸的多个引线14。半导体装置10可容纳例如电力装置、专用IC(application specific IC，ASIC)等各种集成电路16，且引线14，虽然示出为笔直延伸出装置10的两个相对侧，但可从装置10的一个、两个、三个或甚至所有四个侧部延伸。此外，引线14可弯曲成不同形状，例如J型引线或鸥翼形引线，或甚至与壳体齐平，进而形成方形扁平无引脚(Quad Flat No-Lead，QFN)装置。
装置10是基于引线框架的装置，其中引线框架包括引线14和管芯收容区域16。引线14通常远离管芯收容区域16的侧部垂直延伸。每一引线14因此具有内引线末端18和外引线末端20，该内引线末端18与管芯收容区域16的侧部间隔开但靠近该侧部，该外引线末端20远离管芯收容区域16的该侧部，且如上文所论述，引线14的远端20可从装置10的侧向侧向外延伸。
管芯收容区域16的大小和形状设定成支撑一个或多个半导体集成电路(IC)管芯。在示出的实施例中，第一IC管芯22附接到管芯收容区域16的顶表面且第二IC管芯24堆叠在第一IC管芯22的顶部上。第二IC管芯24是任选的且可位于邻近第一IC管芯22处。此外，可存在一个或多个堆叠式管芯和一个或多个相邻管芯。第一IC管芯22通过接合线26电连接到引线14，该等接合线26在一端连接到第一IC管芯22的主动表面上的接合垫并在另一端连接到引线14的内引线末端18。使用常规方法使第二IC管芯24附接到第一IC管芯22的顶表面，并且还使用接合线26使第二IC管芯24电连接到以下中的一者或两者：第一IC管芯22；和引线14中的一个或多个。
本发明的关键特征是可弯曲带材28，该可弯曲带材28弯曲成从管芯收容区域16竖直延伸到主体12的顶表面。装置10还包括形成于主体12的顶表面上方的封盖30。竖直可弯曲带材28接着延伸到封盖30并且与封盖30连接。在一个实施例中，封盖30包括溅涂到主体12的顶表面上的金属，例如铜。必要时，主体12可经历研磨以暴露带材28，使得当封盖30形成于主体12的顶表面上时，带材28将接触封盖30。虽然在本发明的优选实施例中，将封盖30溅涂到主体12的顶表面上，但可使用粘附剂将预成型封盖附接到主体12的顶表面。此外，封盖30可至少部分地在主体12的侧部上方延伸。
图2示出根据本发明的实施例的引线框架32的俯视平面图。引线框架32优选地由铜片如本领域中已知通过冲压、压模、切割或蚀刻形成，且可用例如Ni、Pd和Au等一或多种其它金属或合金镀覆下伏金属(例如，Cu)。引线框架32包括引线14、管芯收容区域16和可弯曲带材28。
在本发明的优选实施例中，带材28沿着管芯收容区域16的一侧形成并且包括结合部34，带材28从该结合部34可弯曲到竖直位置。结合部34可通过蚀刻和渐进机械成型或锻粗工具形成。带材28的长度被设定成主体12的高度。在一个实施例中，带材28具有约0.050mm到约0.200mm的宽度，和约0.50mm到约2.0mm的长度。然而，本领域的技术人员将理解，带材28可形成于引线框架的其它位置中，且带材的尺寸将受封装的大小、管芯收容区域的大小和附接到管芯收容区域的管芯的大小影响。
如本领域中已知，管芯收容区域16可为矩形，且引线14安置于管芯收容区域的侧部中的每一个侧部上并远离管芯收容区域16的相应侧部垂直延伸。引线14的内引线末端18与管芯收容区域16的相应侧部间隔开，但靠近该等相应侧部。
图2还示出主体12的轮廓，或确切地说，在一个实施例中，示出主体12的位置。然而，本领域的技术人员将理解，主体的大小可取决于被主体覆盖的组件的大小和期望外引线末端20从主体12向外延伸的程度而略微更大或更小。
图3是示出图1中示出的半导体装置10的组装的一系列图式。开始于左上侧，示出包括多个引线框架32的引线框架片材36的一部分。引线框架32中的每一个引线框架32都包括引线14、管芯收容区域16和可弯曲带材28，已通过在结合部34弯曲带材28来将该可弯曲带材28弯曲到竖直位置。
在左侧中间图中，第一管芯22已附接到管芯收容区域16且第二管芯24已附接到第一管芯22的上部表面。还通过接合线26将第一管芯22和第二管芯24中的每一个管芯电连接到引线14。可使用包括焊料、胶粘剂或胶带等已知管芯附接方法将第一管芯22附接到管芯收容区域16，且还可使用已知方法将第二管芯24附接到第一管芯22的表面。在示出的实施例中，使用接合线26将第一管芯22的主动表面上的接合垫(未示出)电连接到内引线末端18，并且将第二管芯24的接合垫连接到以下中的一者或两者：第一管芯22的接合垫中的选定接合垫；和内引线末端14。可替换的是，如果第一管芯是倒装芯片管芯，那么第一管芯可通过直接连接到内引线末端的管芯接合垫，例如通过导电凸块或球，搁置在引线顶部。此外，已执行模制过程以用模制化合物覆盖管芯22和24以及接合线26，从而形成主体12。
在左侧下部图中，封装体的顶表面(即，模制化合物)经历研磨以暴露带材28。接着，如右下侧图中所示，封盖30形成于主体12的顶表面上，其中封盖30接触带材28的暴露部分。如前文所述，优选地通过在主体12的顶表面上溅镀铜层形成封盖30。最后，在右上侧，通过单分同时形成的装置来形成各个装置10。
如本领域的技术人员将理解，还执行修整和成型过程，其中切除引线框架32的外部部分，且引线14的外引线末端20延伸到超出主体12的外边缘，进而提供封装半导体装置10。外引线末端20取决于设计要求可延伸到超出或可不延伸到超出主体12的外边缘并且可弯曲成期望形状，例如鸥翼形和J型引线。
现在参考图4，示出了根据本发明的另一实施例的封装半导体装置40的横截面侧视图。半导体装置10具有用塑料模制化合物形成的主体42和在壳体42的侧部和底部暴露的多个引线44，使得装置40是QFN类型的封装。存在管芯收容区域46和附接到管芯收容区域46的表面的微控制器管芯48。管芯收容区域46包括引线框架标记。压力传感器管芯50附接到微控制器管芯48的顶表面。微控制器管芯48通过第一接合线54电连接到引线44，且压力传感器管芯50通过第二接合线56与微控制器管芯48电连接。
可弯曲带材56从管芯收容区域46竖直延伸一种主体42的顶部。封盖58通过导电胶粘剂60紧固到主体42的顶表面。封盖58包括孔62，且主体42包括空隙64。空隙64在模制期间形成于压力传感器管芯50上方。封盖58中的孔62与空隙64流体连通，使得压力传感器管芯50的顶表面暴露于周围环境。在一个实施例中，凝胶(未示出)至少部分地填充空隙并且覆盖压力传感器管芯50。
现将显而易见，本发明提供一种具有可弯曲带材的封装半导体装置，该可弯曲带材从管芯收容区域竖直延伸到形成于封装的顶表面上的封盖。带材连接到封盖将提供EMI和RFI防护。可弯曲带材是引线框架的部分。引线框架因此包括用于将带材弯曲到竖直位置的可弯曲结合部。引线框架可由引线框架供应商制造且引线框架供应商可供应具有处于平坦位置或已经弯曲并且处于竖直位置的带材的引线框架。
除非另有明确陈述，否则每个数值和范围应解释为近似值，如同词语“约”或“大致”在该值或范围之前一样。此外，虽然已使用例如顶部和底部等标识，但应理解，这类标识是相对术语，因此这类表面或定向并非绝对的。此外，虽然示出和描述了堆叠管芯装置，但本发明不限于堆叠管芯装置，因为可组装包括延伸到封装封盖并且与封装封盖连接的竖直带材的单个管芯装置、具有并排管芯的装置或具有堆叠式管芯与并排管芯的组合的装置。
另外应理解，在不脱离如在所附权利要求中涵盖的本发明的实施例的情况下，本领域的技术人员可对已描述并且示出以解释本发明的实施例的各部分的细节、材料和布置进行各种改变。
在包括任何权利要求的此说明书中，术语“每一(each)”可用于指代多个先前叙述元件或步骤的一个或多个指定的特性。当与开放式术语“包括”一起使用时，术语“每一”的叙述不排除附加的未列出的元件或步骤。因此，应理解，设备可具有附加的未列出的元件，并且方法可具有附加的未列出的步骤，其中附加的未列出的元件或步骤不具有一个或多个指定的特性。
本文中提及“一个实施例”或“实施例”意指结合该实施例描述的特定特征、结构或特性可包括在本发明的至少一个实施例中。本说明书中各个位置中的短语“在一个实施例中”的出现不必完全是指相同实施例，也不是与其它实施例相互排斥的单独或替代实施例。同样的情况适用于术语“实施方案”。

Claims (10)

1.一种制品，其特征在于，包括：
管芯收容区域、多个引线和带材，所述引线安置于所述管芯收容区域的至少一侧上并且大体垂直于所述管芯收容区域的所述至少一侧，其中所述多个引线中的每一引线具有内引线末端和外引线末端，所述内引线末端与所述管芯收容区域的所述至少一侧间隔开但靠近所述管芯收容区域的所述至少一侧，所述外引线末端远离所述管芯收容区域的所述至少一侧，所述带材形成于所述管芯收容区域中并且可弯曲到大致竖直位置以用于连接到封装封盖。
2.根据权利要求1所述的制品，其特征在于，所述带材沿着所述管芯收容区域的一侧形成。
3.根据权利要求1所述的制品，其特征在于，所述带材具有0.05mm到0.20mm的宽度，以及0.50mm到2.0mm的长度。
4.根据权利要求1所述的制品，其特征在于，所述制品包括引线框架，且所述引线框架包括镀覆有非腐蚀性金属或金属合金的铜。
5.根据权利要求1所述的制品，其特征在于，所述管芯收容区域为矩形。
6.根据权利要求5所述的制品，其特征在于，所述多个引线包括安置于所述管芯收容区域的侧部中的每一侧部上的引线。
7.一种受防护半导体装置，其特征在于，包括：
引线框架，其包括管芯收容区域、多个引线和带材，所述引线安置于所述管芯收容区域的至少一侧上并且大体垂直于所述管芯收容区域的所述至少一侧，其中所述多个引线中的每一引线具有内引线末端和外引线末端，所述内引线末端与所述管芯收容区域的所述至少一侧间隔开但靠近所述管芯收容区域的所述至少一侧，所述外引线末端远离所述管芯收容区域的所述至少一侧，所述带材形成于所述管芯收容区域中并且弯曲到大致竖直位置以用于连接到封装封盖；
第一集成电路管芯，其附接到所述管芯收容区域并且电连接到所述多个引线的所述内引线末端；
包封物，其形成于所述第一管芯和所述第一管芯与所述多个内引线末端之间的电连接件上方，其中所述包封物形成主体，且其中所述带材竖直延伸到所述主体的上边缘；和
封盖，其形成于所述主体的所述上边缘上并且接触竖直带材的远端。
8.根据权利要求7所述的受防护半导体装置，其特征在于，进一步包括第二集成电路管芯，所述第二集成电路管芯附接到所述第一管芯的顶表面并且电连接到所述多个引线和所述第一管芯中的至少一个，并且覆盖有所述包封物。
9.一种组装受防护半导体装置的方法，其特征在于，包括：
提供引线框架，所述引线框架包括管芯收容区域、多个引线和带材，所述引线安置于所述管芯收容区域的至少一侧上并且大体垂直于所述管芯收容区域的所述至少一侧，其中所述多个引线中的每一引线具有内引线末端和外引线末端，所述内引线末端与所述管芯收容区域的所述至少一侧间隔开但靠近所述管芯收容区域的所述至少一侧，所述外引线末端远离所述管芯收容区域的所述至少一侧，所述带材形成于所述管芯收容区域中并且弯曲到大致竖直位置以用于连接到封装封盖；
将第一集成电路(IC)管芯附接到所述引线框架的管芯垫；
将所述第一IC管芯电连接到所述多个引线的所述内引线末端；
用模制化合物包封所述第一IC管芯、电连接件和所述引线框架，其中所述模制化合物形成主体，且其中所述多个引线的远端沿着所述主体的至少一个侧向侧暴露且竖直带材的远端在所述主体的顶表面暴露；和
在所述主体的所述顶表面上形成金属封盖，其中所述竖直带材的暴露的远端接触所述封盖。
10.根据权利要求9所述的方法，其特征在于，进一步包括：
将第二IC管芯附接到所述第一IC管芯的上表面并且将所述第二IC管芯电连接到所述第一IC管芯和所述多个引线的所述内引线末端中的至少一个，其中所述第二IC管芯覆盖有所述模制化合物。
CN201911050278.9A 2018-10-30 2019-10-30 受防护半导体装置和其引线框架 Pending CN111128943A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11584638B2 (en) 2020-07-30 2023-02-21 Invensense, Inc. Reducing delamination in sensor package

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY196394A (en) * 2019-01-04 2023-03-28 Carsem M Sdn Bhd Molded Integrated Circuit Packages
US10892229B2 (en) * 2019-04-05 2021-01-12 Nxp Usa, Inc. Media shield with EMI capability for pressure sensor
US20220221353A1 (en) * 2021-01-12 2022-07-14 Texas Instruments Incorporated Semiconductor force sensors

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557142A (en) 1991-02-04 1996-09-17 Motorola, Inc. Shielded semiconductor device package
US5166772A (en) 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
KR0184076B1 (ko) 1995-11-28 1999-03-20 김광호 상하 접속 수단이 패키지 내부에 형성되어 있는 3차원 적층형 패키지
US6740959B2 (en) 2001-08-01 2004-05-25 International Business Machines Corporation EMI shielding for semiconductor chip carriers
WO2005059995A2 (en) 2003-12-18 2005-06-30 Rf Module And Optical Design Limited Semiconductor package with integrated heatsink and electromagnetic shield
CN1755929B (zh) 2004-09-28 2010-08-18 飞思卡尔半导体（中国）有限公司 形成半导体封装及其结构的方法
US20070071268A1 (en) 2005-08-16 2007-03-29 Analog Devices, Inc. Packaged microphone with electrically coupled lid
US7582951B2 (en) 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US7449775B1 (en) * 2006-05-22 2008-11-11 Sun Microsystems, Inc. Integrated thermal solution for electronic packages with materials having mismatched coefficient of thermal expansion
US20080014678A1 (en) 2006-07-14 2008-01-17 Texas Instruments Incorporated System and method of attenuating electromagnetic interference with a grounded top film
US7557417B2 (en) 2007-02-21 2009-07-07 Infineon Technologies Ag Module comprising a semiconductor chip comprising a movable element
US8072047B2 (en) 2008-05-21 2011-12-06 Stats Chippac Ltd. Integrated circuit package system with shield and tie bar
US20090302483A1 (en) * 2008-06-04 2009-12-10 Himax Technologies Limited Stacked die package
US8362598B2 (en) 2009-08-26 2013-01-29 Amkor Technology Inc Semiconductor device with electromagnetic interference shielding
US8216885B2 (en) * 2009-10-19 2012-07-10 Texas Instruments Incorporated Methods and devices for manufacturing cantilever leads in a semiconductor package
US20120126378A1 (en) 2010-11-24 2012-05-24 Unisem (Mauritius ) Holdings Limited Semiconductor device package with electromagnetic shielding
US9362209B1 (en) 2012-01-23 2016-06-07 Amkor Technology, Inc. Shielding technique for semiconductor package including metal lid
US9153543B1 (en) 2012-01-23 2015-10-06 Amkor Technology, Inc. Shielding technique for semiconductor package including metal lid and metalized contact area
US8809973B2 (en) * 2013-01-23 2014-08-19 Infineon Technologies Ag Chip package comprising a microphone structure and a method of manufacturing the same
US9986354B2 (en) 2013-06-26 2018-05-29 Infineon Technologies Ag Pre-mold for a microphone assembly and method of producing the same
US9656857B2 (en) * 2014-11-07 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectromechanical systems (MEMS) devices at different pressures
US9673150B2 (en) 2014-12-16 2017-06-06 Nxp Usa, Inc. EMI/RFI shielding for semiconductor device packages
US9653414B2 (en) 2015-07-22 2017-05-16 Nxp B. V. Shielded QFN package and method of making
US10269682B2 (en) * 2015-10-09 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US20170278825A1 (en) * 2016-03-24 2017-09-28 Freescale Semiconductor, Inc. Apparatus and Methods for Multi-Die Packaging
US11011483B2 (en) * 2018-02-21 2021-05-18 Texas Instruments Incorporated Nickel alloy for semiconductor packaging

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11584638B2 (en) 2020-07-30 2023-02-21 Invensense, Inc. Reducing delamination in sensor package
TWI795761B (zh) * 2020-07-30 2023-03-11 美商伊凡聖斯股份有限公司 減少感測器封裝中的脫層及其方法

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