CN107636828A - 集成的夹具和引线以及制作电路的方法 - Google Patents

集成的夹具和引线以及制作电路的方法 Download PDF

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CN107636828A
CN107636828A CN201680033968.1A CN201680033968A CN107636828A CN 107636828 A CN107636828 A CN 107636828A CN 201680033968 A CN201680033968 A CN 201680033968A CN 107636828 A CN107636828 A CN 107636828A
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lead frame
fixture
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circuit according
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CN107636828B (zh
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M·涩谷
M·吉野
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Texas Instruments Inc
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Abstract

一种电路包括耦合到电路中的至少一个组件的导电夹具(502)。至少一个引线部分(552)位于夹具的一端上。该电路进一步包括第一引线框架，该第一引线框架具有设定尺寸(444)以接收至少一个引线部分(552)的至少一个开口。至少一个引线部分(552)被接收在至少一个开口(444)中，并且至少一个引线部分(552)是电路的外部导体。

Description

集成的夹具和引线以及制作电路的方法
背景技术
一些集成电路具有无引脚封装，诸如将集成电路物理地和电气地耦合到印刷电路板的方形扁平无引脚(QFN)器件和双排扁平无引脚(DFN)器件。扁平无引脚器件(也被称为微引线框架(MLF)器件和小外形无引脚(SON)器件)基于表面安装技术，该技术将集成电路连接到印刷电路板的表面，而无需印刷电路板中的通孔。在一些示例中，扁平无引脚封装是接近芯片尺寸的塑料包封封装件，通常用平面铜引线框架衬底制造。封装件上的周边焊盘(land)提供与印刷电路板的电耦合。焊盘用作触点并且可以被称为集成电路内部的引线，但是这些引线不会延伸超出集成电路封装件的边界。
一些集成电路和其它电子器件具有耦合到电路和器件内的电子组件的导电夹具。这些夹具可以在第一平面上，并且电路和器件的引线或触点可以在第二平面上。夹具被焊接或以其它方式电气地和/或机械地结合到引线，这在器件和集成电路的外部触点之间产生额外的电阻。该结合也在电路和器件中提供了弱点(weak spot)。例如，这些结合很容易发生破裂和其它故障，这可能使电路和器件不能工作。
发明内容
一种电路包括耦合到电路中的至少一个组件的导电夹具。至少一个引线部分位于夹具的一端上。该电路进一步包括具有设定尺寸以接收至少一个引线部分的至少一个开口的第一引线框架。至少一个引线部分被接收在至少一个开口中，并且至少一个引线部分是电路的外部导体。
附图说明
图1是器件的一部分的侧视截面图，示出了夹具与引线之间的结合。
图2是图1的整个器件的顶视等距视图，示出了夹具与引线之间的结合。
图3是图1和图2的夹具与引线之间的结合的放大剖视图，示出了结合中的裂缝的位置。
图4是第一引线框架的示例的顶视平面图。
图5是第二引线框架的示例的顶视平面图。
图6是示出图4的引线框架上的凸片的示例的剖视正视图。
图7是图4和图5的引线框架在被放在一起之后的顶视平面图。
图8是在模锻工艺之后附接到引线的图5的夹具的侧面正视图。
图9是包含第一FET器件和第二FET器件的结构的侧面剖视图。
图10是制造图9的结构的示例方法的流程图。
具体实施方式
图1是电子器件100的一部分的侧视截面图，示出了夹具102与引线104之间的结合。器件100的示例包括方形扁平无引脚(QFN)封装或者双排扁平无引脚(DFN)封装中的集成电路。夹具102是诸如铜的导电材料，其耦合到电路或集成电路内的至少一个电子组件(图1中未示出)。在一些实施例中，夹具102电耦合到至少一个场效应晶体管(FET)的源极或漏极。引线104也是导电材料并且用作器件100的引线以将器件100耦合到其它电子器件。例如，引线104可以将器件100电子地和机械地耦合到印刷电路板上的导体。
器件100被嵌入到通过常规模制技术施加的模具106中。引线104具有未被模具106包围的表面107，并且用作器件100的导电焊盘。在将器件100组装到印刷电路板(未示出)期间，表面107被设置在结合材料(诸如印刷电路板的表面上的焊料)上。在固化结合材料之后，器件100被电气地和机械地耦合到印刷电路板，而无需使用印刷电路板中的通孔。
夹具102和引线104位于不同的平面上，使得夹具102具有成角度的部分108，该成角度的部分使夹具102的端部110到达引线104的平面。夹具102的端部110位于引线104的表面114附近，并且通过结合化合物116在结合区域115处机械地和电气地耦合到表面114。在一些实施例中，结合化合物116是通常将夹具和引线结合在一起的焊料或导电环氧树脂。
图2是图1的器件100的示例的顶视等距视图。夹具102电耦合到电子组件，这些电子组件在图2的实施例中是晶体管Q1和Q2。晶体管Q1也电气地和机械地耦合到夹具200。例如，夹具102可以耦合到晶体管Q1的源极，并且夹具200可以耦合到晶体管Q1的漏极。夹具200可以电耦合到图2中未示出的引线，该引线将晶体管Q1的漏极耦合到外部电路或器件。晶体管Q1的栅极耦合到夹具202，该夹具202通过结合材料208结合到引线204。夹具102电气地和机械地结合到晶体管Q2的源极。
夹具102与引线104(以及夹具202与引线204)之间的结合存在一些电气和机械问题。参考夹具102与引线104之间的结合，该结合在夹具102与引线104之间产生相对高的电阻。例如，电阻在以下位置处：夹具102；夹具102与结合材料116之间的触点；结合材料116；结合材料116与引线104之间的触点；以及引线104。这些电阻是串联的，并且可能大于夹具102与引线104的材料(其可以是低电阻铜)的电阻。因此，夹具102到引线104的结合可能在耦合到夹具102和引线104的电子组件之间提供相对高的电阻，这可能负面地影响这些组件的功能。
在机械方面，夹具102与引线104之间的结合是器件100中的弱点，并且容易发生破裂或其它故障。图3是图1和图2的夹具102与引线104之间的结合区域115的放大剖视图，其示出了结合材料116中的裂缝300的位置。裂缝300可能由应力引起，诸如由于温度变化或对结合材料116、夹具102和/或引线104施加应力的其它因素导致的膨胀和收缩引起的应力施加。裂缝300位于结合材料116中，因此它可能增加结合材料116中的电阻并且由于夹具102与引线104之间的高电阻而使上述问题恶化。在一些情况下，裂缝300可能导致夹具102和引线104之间完全断开，这可能导致器件100的故障。
本文所描述的器件通过将夹具和引线形成或制造成单个器件而不是结合在一起的两个器件来克服与夹具和引线之间的结合相关联的上述问题。图4是第一引线框架400的顶视平面图。图5是第二引线框架500的顶视平面图。引线框架400和500是双FET器件的一些部分，在其中FET串联电耦合并且在物理上并排布置。如本文所描述，双FET器件的用法是可将夹具制造成引线的许多应用的示例。
第一引线框架400具有多个部分402。每个部分402构成具有双FET的单个器件，所述双FET在本文中被称为第一FET和第二FET。在图4的示例中，第一引线框架400具有四个部分402，但是可以存在任意数量的部分402。这些部分402由支撑在部分402内的组件并将部分402彼此连接的框架406限定。
在图4的示例中，第一引线框架400具有第一夹具或导体410，第一FET的节点被制造在第一夹具或导体410上。在本文描述的示例中，第一FET的漏极被制造在第一导体410的表面412上。多个固位器(retainer)414将第一导体410连接到框架402，并用于在制造期间将第一导体410相对于框架402保持在固定位置。稍后的制造工艺切割固位器414，因此它们用作将第一FET耦合到其它电路和/或电子组件的导体。
第二夹具或导体420具有表面422，第二FET的源极被制造在表面422上。多个固位器424将第二导体420连接到框架402，并用于在制造期间将第二导体420相对于框架402保持在固定位置。如同第一导体410一样，固位器424在稍后的制造工艺期间被切割并用作将第二FET耦合到其它电路和/或电子组件的导体。第三夹具或导体430耦合到第二FET的栅极。固位器434将第三导体430连接到框架402并起到与固位器414和424相同的功能。
如下面更详细描述的，多个固位器440从框架402延伸并用于接收第二引线框架500的一些部分。固位器440包括由空间444分开的多个凸片(tab)442，其中如下面更详细描述的，第二引线框架500的一些部分被接收到空间444中。
图6是示出图4的固位器440的示例的剖视正视图。在图6的示例中，第二引线框架500的一些部分填充凸片442之间的空间444。凸片442具有延伸超过第二引线框架500的高度的延伸部分600。在图6的示例中，延伸部分600是尖的或大致三角形的。延伸部分600在模锻工艺期间提供金属以填充凸片442与第二引线框架500之间的空间。
再次参考图5，第二引线框架500具有带有表面504的第一夹具或导体502。表面504是包含FET的器件的顶表面；并且在一些实施例中，表面504是器件的外表面。第一导体502具有与表面504相对的表面(图5中未示出)，第一FET的源极和第二FET的漏极制造在该相对的表面上。第二引线框架500具有将第一导体502连接到框架512的多个固位器510。框架512与图4的框架402起到相同的作用。第二夹具或导体520耦合到第一FET的栅极。第二导体520相对于框架512被固位器522保持在固定位置。
第一导体502具有从主体部分延伸的多个引线550，并且第二导体520具有从主体部分延伸的引线552。引线550和552有时被称为引线部分。引线550通过过渡部554连接到第一导体502，并且引线552通过过渡部556连接到第二导体520。过渡部554和556将引线550和552降低到一个或多个平面，该平面低于第一导体502和第二导体520的主体部分所位于其上的平面。引线550和552与第一导体502中的其它组件一体形成。
在制造期间，用于FET的源极、栅极和漏极的材料被制造在引线框架400和500的导体上。例如，FET的组件可以被制造到导体410、420和430上或者被电耦合到导体410、420和430。下面进一步描述FET中的多个层的示例。然后可以将第二引线框架500放置到第一引线框架400上，并且可以固化焊料结合件或其它结合件以形成FET。
图7是图4和图5的引线框架400和500在它们放在一起之后的顶视平面图。图7是第二引线框架500已经被放置在第一引线框架400的顶部上的顶视图。如图7所示，第一导体502的引线550和第二导体520的引线552被接收到固位器440的空间444中。引线550和552在固位器440内的布置由图6的正视图示出。在引线550和552被接收到空间444中之后，FET中的焊料和/或其它结合材料被固化。
在此制造阶段，在FET内的结合材料被固化，并且引线框架400和500需要在单片化之前用模塑化合物包封。引线550和552在模制之前被固定到固位器440，这在模制和单片化工艺期间将引线550和552固定在安全的位置。图8示出在模锻工艺之后附接到引线550和552的固位器440。另外参考图6，模锻工艺已将固位器440的顶部600冲压或变形为引线550和552，这将引线550和552固定在固定位置。因此，引线550和552位于比导体502和520(图5)更低的平面上，并且当将与模制相关联的压力施加到引线框架400和500时，引线550和552将不会移动。可以应用其它技术以将引线550和552固定到第一固位器440，诸如铆接和其它结合技术。
图9是包含第一FET器件902和第二FET器件904的结构900的侧面剖视图。结构900的视图没有示出模制化合物，但是模制化合物将在FET器件902和904的顶表面908和底表面910之间延伸。FET器件902和904中的每一个具有两个FET，它们是前面提到的第一FET 914和第二FET 916。沿着穿过固位器440的划片线920来单片化器件。因此，该单片化(singulation)断开第一引线框架400和第二引线框架500之间的任何电接触，使得引线550和552(图9中未示出)不电接触第二引线第一引线框架400。在单片化之后，引线550和552被暴露并用作其相应的器件902和904的电导体。
图10是如上所述加工带有两个引线框架的器件的示例方法的流程图1000。步骤1002包括在第一引线框架的一部分与第二引线框架的一部分之间制造至少一个电子组件。第一引线框架具有引线部分。步骤1004包括将第一引线框架的引线部分附接到第二引线框架。步骤1006包括将至少一个组件单片化。引线部分是单片化之后的电子组件的引线。
为了说明的目的，上面描述的器件是用双晶体管制造的。在其它实施例中，器件是用其它组件(诸如单晶体管)制造的。一体形成的引线(如上所述)减小了从引线到组件的电阻并增加了热导率。例如，一体形成的引线能够有效地传递热量，而无需通过结合材料传导热量。
虽然已经在此详细描述了集成电路的一些示例，但是在所描述的实施例中可以进行修改，并且在权利要求的范围内的其它实施例是可能的。

Claims (20)

1.一种电路，其包括：
导电夹具，其耦合到所述电路中的至少一个组件；
至少一个引线部分，其位于所述夹具的一端上；以及
第一引线框架，其具有设定尺寸以接收所述至少一个引线部分的至少一个开口；
其中所述至少一个引线部分被接收在所述至少一个开口中；以及
其中所述至少一个引线部分是所述电路的外部导体。
2.根据权利要求1所述的电路，其中所述导电夹具是第二引线框架的至少一部分。
3.根据权利要求2所述的电路，其中所述第一引线框架至少部分地在第一平面上，并且其中所述第二引线框架至少部分地在第二平面上。
4.根据权利要求1所述的电路，其中所述至少一个引线部分通过模锻工艺固定在所述至少一个开口内。
5.根据权利要求1所述的电路，其中所述至少一个引线部分通过结合化合物固定在所述至少一个开口内。
6.根据权利要求1所述的电路，进一步包括限定所述至少一个开口的所述边界的多个凸片。
7.根据权利要求6所述的电路，其中所述凸片在制造期间具有延伸部分，并且其中所述延伸部分在制造期间被挤压，并且其中所述挤压将所述至少一个引线部分固定在所述至少一个开口中。
8.根据权利要求6所述的电路，其中所述凸片被模锻以将所述至少一个引线部分固定在所述至少一个开口中。
9.根据权利要求6所述的电路，其中所述凸片与结合材料结合以将所述至少一个引线部分固定在所述至少一个开口中。
10.根据权利要求1所述的电路，其中所述导电夹具耦合到至少一个晶体管的第一节点。
11.根据权利要求10所述的电路，其中所述第一引线框架耦合到所述至少一个晶体管的第二节点。
12.根据权利要求1所述的电路，其中第一晶体管的源极和第二晶体管的漏极被制造在所述导电夹具上。
13.根据权利要求12所述的电路，其中所述第二晶体管的所述漏极和所述第二晶体管的所述源极被制造在所述第一引线框架上。
14.根据权利要求12所述的电路，其中所述第一晶体管的所述栅极耦合到所述导电夹具。
15.一种制造电路的方法，所述方法包括：
在第一引线框架的一部分和第二引线框架的一部分之间制造至少一个电子组件，所述第一引线框架具有引线部分；
将所述第一引线框架的所述引线部分附接到所述第二引线框架；以及
从所述第一引线框架和所述第二引线框架单片化个体组件，其中所述引线部分是单片化之后的所述电子组件的引线。
16.根据权利要求15所述的方法，其中所述单片化切割所述至少一个导电夹具与所述第一引线框架之间的附接。
17.根据权利要求15所述的方法，进一步包括在单片化之前将至少所述引线部分包封在模塑化合物中。
18.根据权利要求17所述的方法，其中所述引线部分的所述至少一部分在单片化之后从所述模制化合物延伸。
19.根据权利要求15所述的方法，其中附接包括将所述第一引线框架的所述引线部分模锻到所述第二引线框架。
20.一种电路，包括：
导电夹具，其耦合到晶体管的至少第一节点；
至少一个引线部分，其位于所述夹具的一端上并与所述夹具一体形成；以及
引线框架，其具有设定尺寸以接收所述至少一个引线部分的至少一个开口，其中所述晶体管的第二节点耦合到所述引线框架；
其中所述至少一个引线部分被接收在所述至少一个开口中；以及
其中所述至少一个引线部分是所述电路的外部导体。
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