CN102194788A - 多层引线框封装及其制备方法 - Google Patents
多层引线框封装及其制备方法 Download PDFInfo
- Publication number
- CN102194788A CN102194788A CN2011100728941A CN201110072894A CN102194788A CN 102194788 A CN102194788 A CN 102194788A CN 2011100728941 A CN2011100728941 A CN 2011100728941A CN 201110072894 A CN201110072894 A CN 201110072894A CN 102194788 A CN102194788 A CN 102194788A
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- China
- Prior art keywords
- semiconductor wafer
- lead frame
- encapsulation
- leadframe package
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 claims abstract description 213
- 235000012431 wafers Nutrition 0.000 claims description 202
- 238000005538 encapsulation Methods 0.000 claims description 92
- 239000000206 moulding compound Substances 0.000 claims description 57
- 230000005611 electricity Effects 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 16
- 230000005669 field effect Effects 0.000 claims description 11
- 239000012530 fluid Substances 0.000 claims description 11
- 238000000926 separation method Methods 0.000 claims description 5
- 238000000465 moulding Methods 0.000 abstract description 9
- 150000001875 compounds Chemical class 0.000 abstract 2
- 239000011230 binding agent Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 238000002360 preparation method Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000010923 batch production Methods 0.000 description 3
- 239000007767 bonding agent Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
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Abstract
本发明提供了一种多层引线框封装及其制备方法,本发明提出了一种引线框封装,具有第一、第二、第三和第四导电结构,一对半导体晶片设置在它们之间,限定了一个堆栈式结构。第一和第二结构与第一结构分离开来,并重叠。半导体就设置在第一和第二结构之间。半导体晶片具有电连接到第一和第二结构的接头。一部分第三结构与一部分第二结构位于同一平面内。第三结构耦合到半导体晶片上。一个额外的半导体晶片连接到第一和第二结构的其中之一上。第四结构与额外的半导体晶片电接触。设置成型混料,将一部分所述的封装与设置在体积中的成型混料的子部分密封起来。
Description
技术领域
本发明主要涉及半导体封装,更确切地说是涉及多层引线框封装及其制备方法。
背景技术
现有的引线框组装技术采用一块金属合金带有多个单元结构,每个单元结构都通过晶片连接工艺,接收一个或指定数量的芯片。
最常见的情况是,通常由金(Au)铝(Al)或铜(Cu)制备的金属线,连接到一个或多个半导体晶片的顶部衬垫以及引线框的引线垫上方,以便将来自引线框封装外部的信号和/或功率,传递到内部晶片,反之亦然。
近年来,已经引入连接晶片和引线框的金属平板和/或夹片,用于功率半导体封装,以省略引线接合工艺并降低导通电阻。然而,现有的夹片/平板组装工艺所使用的夹片连接过程,是以一个接一个的顺序拾取并放下每个晶片的夹片。但这会减少产量输出。因此,有必要提供具有所需工作性能的功率半导体封装。
发明内容
本发明提出了一种引线框封装,其特点是具有第一结构,该第一结构是导电的;一个分离出来第二结构,与第一结构重叠,该第二结构是导电的;一个设置在第一和第二结构之间的半导体晶片,第二结构的一部分与半导体晶片分离,半导体晶片限定了一个体积,并具有一个直通路径,在第二结构的对边之间延伸,该直通路径与体积成流体连通,半导体晶片具有与第一和第二结构电接触的接头;以及设置的成型混料,用于将一部分封装和设置在体积中的成型混料的子部分密封在一起。在另一个实施例中,提出了第三结构,即与一部分第二结构共处一个公共平面的部分。该第三结构是导电的,并与半导体晶片电连通。然而,在另一个实施例中,一个额外的半导体晶片与第一和第二结构的其中之一重叠,并连接在一起。一个第四结构与额外的半导体晶片重叠,该第四结构是导电的,并与额外的半导体晶片电连通。本发明的这些及其他方面还将在下文中详细论述。
一个引线框封装,其特点是,该封装包含:
一个第一引线框,该第一引线框是导电的;
一个第二引线框,与该第一引线框重叠,该第二引线框的一部分与该第一引线框分离开来,该第二引线框是导电的;
一个设置在该第一和第二引线框之间的第一半导体晶片,该第一半导体晶片具有电连接到该第一和第二引线框上的接头;
一个第二半导体晶片,接合并电连接到该第二引线框;
一个第三引线框,与该第一和第二引线框重叠,是导电的,并与该第二半导体晶片电接触;以及,
所设置的成型混料,用于密封一部分该封装。
一个引线框封装,其特点是,该封装包含:
一个第一结构,该第一结构是导电的;
一个第二结构,与该第一结构重叠,该第二结构的一部分与该第一结构分离开来,该第二结构是导电的;
一个设置在该第一和第二结构之间的半导体晶片,该半导体晶片具有电连接到该第一和第二结构上的接头;并且
所设置的成型混料,用于密封一部分封装,其中每个该第一结构和第二结构都还含有在相互垂直方向上延伸的拉杆。
一种用于制备引线框封装的方法,其特点是,该方法包含:
制备一个第一引线框;
将第一半导体晶片固定在第一引线框上;
将第二引线框固定在所述的第一半导体晶片上,该第一半导体晶片设置在所述的第一和第二引线框之间;
将第二半导体晶片固定在所述的第二引线框上,该第二引线框设置在该第一和第二半导体晶片之间,并将该第一半导体晶片上的接头电连接到该第二半导体晶片上的接头上;
将第三引线框固定在该第二半导体晶片上,该第二半导体晶片设置在该第二和第三引线框之间;
将该半导体晶片密封在非导电的成型混料中;并且
分离该封装。
一种半导体封装,其特点是,该封装包含:
一个第一结构,该第一结构是导电的;
一个第二结构,与该第一结构分离开来,并重叠,该第二结构是导电的;
一个第一半导体晶片,设置在该第一和第二结构之间,该第一半导体晶片具有电连接到该第一和第二结构的接头;
一个第二半导体晶片,连接到该第二结构上,使第二结构位于第一和第二半导体晶片之间,并且电连接到第一和第二半导体晶片上;以及
一个第三结构,与该第二结构分离开来,并重叠,该第三结构是导电的,并与该第二半导体晶片电接触。
附图说明
图1表示依据本发明的第一实施例,一种半导体晶片封装的俯视图;
图1A表示图1所示的半导体晶片封装的第一引线框的俯视图;
图1B表示图1所示的半导体晶片封装的半导体晶片的俯视图;
图1C表示安装在图1所示的半导体晶片封装的第一引线框上方的半导体晶片的俯视图;
图1D表示图1所示的半导体晶片封装的第二引线框的俯视图;
图2表示图1所示的封装沿线2-2的剖面图;
图3表示图1所示的封装沿线3-3的剖面图;
图4表示图1-3所示的接触窝点和直通路径的详细视图;
图5A表示图1所示封装的侧视图;
图5B表示图5A所示的封装旋转90度的侧视图;
图6A和6B分别表示图5所示封装的仰视图和俯视图;
图7表示依据本发明的第二实施例,一种半导体晶片封装的俯视图;
图8表示图7所示的封装沿线8-8的剖面图;
图9表示带有成型材料的类似于图1所示封装的俯视图;
图10表示带有成型材料的类似于图1所示封装的仰视图;
图11表示依据本发明的第三实施例,一种半导体晶片封装的俯视图;
图12表示图11所示的封装沿线12-12的剖面图;
图13表示图11所示的封装沿线13-13的剖面图;
图14表示图11所示的封装沿线14-14的剖面图;
图15表示图11-14所示的接触窝点和直通路径的详细视图;
图16表示带有成型材料的类似于图11所示封装的俯视图;
图17表示依据本发明的一个可选实施例,带有成型材料的类似于图11所示封装的俯视图;
图18表示依据本发明的一个可选实施例,带有成型材料的类似于图7所示封装的俯视图;
图19表示依据本发明的另一个可选实施例,带有成型材料的类似于图7所示封装的俯视图;
图20表示依据本发明的第四实施例,一种半导体晶片封装的俯视图;
图21表示带有成型材料的类似于图20所示封装的俯视图;
图22表示与图20所示的半导体晶片有关的电路图的示意图;
图23表示依据本发明的第五实施例,一种半导体晶片封装的俯视图;
图24表示图23所示的封装沿线24-24的剖面图;
图25表示与图23所示的半导体晶片有关的电路图的示意图;
图26表示依据本发明的另一个实施例,一种半导体晶片封装的俯视图;
图26A表示图26所示封装的底部引线框的俯视图;
图26B表示安装在图26所示封装的底部引线框上的第一半导体晶片的俯视图;
图26C表示图26所示封装的中间引线框的俯视图;
图26D表示安装在图26所示封装的第一半导体晶片和底部引线框上的中间引线框的俯视图;
图26E表示安装在图26所示封装的中间引线框上的第二半导体晶片的俯视图;
图26F表示图26所示封装的顶部引线框的俯视图;
图27表示图26所示的封装沿线27-27的剖面图;
图28表示图26所示的封装沿线28-28的剖面图;
图29表示图26所示的封装沿线29-29的剖面图;
图30表示用于组装图1所示封装的批量处理技术的透视图;
图31表示组装的一批图30所示封装的透视图;
图32表示图31所示的校准孔和校准突起的侧面剖面图;
图33表示用于类似于图31所示的引线框结构的第二半导体晶片的俯视图;
图34表示用于类似于图31所示的引线框结构的顶部引线框的俯视图;
图35表示用于类似于图26-34所示的引线框结构的校准孔和校准突起的侧面剖面图;
图36表示制备类似于图26所示封装的工艺流程图。
具体实施方式
参见图1至6B,一种多层引线框封装10包含第一和第二导电引线框12和14。第一引线框12含有三个分隔开的结构15、16和17。第二引线框14含有两个分隔开的结构18和19。结构18与结构15和16的一部分重叠,结构19与结构15和17的一部分重叠。半导体晶片20包含在封装10中。半导体晶片20在电学领域中已为人们所熟知。在本例中,半导体晶片20可以是一个晶体管,例如功率场效应管(FET)或功率金属氧化物半导体FET(MOSFET),具有位于其顶端的一个源极电极20a和一个栅极电极20b,以及位于其底端的一个漏极电极(图中没有表示出),结构15构成漏极接头,结构18构成源极接头,并且结构19构成栅极接头。在一个可选实施例中,可以用一个接合引线代替结构19。可以用任何适合传导半导体晶片20中电流的导电材料,制备引线框12和14。例如可以用铝、铜、金等诸如此类的处理,制备引线框12和14。
参见图2和3,结构18和19对着半导体晶片20的第一边22(例如源极和栅极边),结构15对着半导体晶片20的第二边23(例如漏极边),第二边23设置在第一边22的对面。利用导电环氧脂、焊锡等合适的粘合剂/结合剂24,将第二边23连接到结构15上。为了便于将半导体晶片20连接到结构15上,半导体晶片20的一个或多个边,如图26和28所示,可以设置在隆起处或凹陷处,如图结构15上的30和32所示。隆起处/凹陷处30和32中的其中之一,必须包围着半导体晶片20,以便将半导体晶片20固定在合适的位置。因此,在制备封装10时,可以精确地控制半导体晶片20的位置。更确切地说由凹陷处30形成的侧壁34,不仅可以用于阻止半导体晶片20移动到上方,而且还可以将结合剂24保留在结构15所需的区域内。与之类似,凹陷处32形成的侧壁36,不仅可以用于阻止半导体晶片20移动到上方,而且还可以将结合剂24保留在结构15所需的区域内。
参见图1和2,除了接触窝点38之外,结构18与半导体晶片20分离开来。按照这种方式,体积40限定在结构18和半导体晶片20之间。结构16与半导体晶片20并排且分离开来形成其间的空隙42,空隙42与体积40成流体连通。利用上述合适的导电粘合剂/结合剂46,将结构18的一部分44固定连接到结构16上。结构16和18的一部分,延伸出结合剂46,并相互分离开来,限定了它们之间的缝隙48。
参见图2和3,结构17与半导体晶片20并排且分离开来形成其间的空隙50。结构19在半导体晶片20和结构17之间延伸,与一部分空隙50重叠。除了接触窝点52之外,结构19与半导体晶片20分离开来,限定了它们之间的体积54。利用上述合适的导电粘合剂/结合剂58,将结构19的一部分56固定连接到结构17上。结构17和19的一部分,延伸出结合剂58,并相互分离开来,限定了它们之间的缝隙60。
参见图2、3和4,结构18和半导体晶片20之间的电连接是利用接触窝点38实现的。每个接触窝点38都是整体与结构18一起形成,并延伸离开,引线框14的顶面64所在的平面62朝向着半导体晶片20,终止在区域66处。例如上述的那些导电结合剂,将接触窝点38固定连接到区域66。区域66通常含有一个接头(例如图1B所示的源极电极20a),同半导体晶片20中的电路(图中没有表示出)电连接。结构19也以一种类似的方式,利用接触窝点52,与半导体晶片20的区域68电连接。接触窝点52整体与结构19一起形成。通过上述的那些导电粘合剂/结合剂,将接触窝52固定连接到区域68。区域68通常含有一个接头(例如图1B所示的栅极电极20b),同半导体晶片20中的电路(图中没有表示出)电连接。
每个接触窝点38都含有一个通孔70、一个环状肩72、一个环状侧壁74以及一个小孔76。通孔70从区域66开始延伸,在环状肩72中终止。环状侧壁74从环状肩72开始延伸,在小孔76中终止。与之类似,接触窝点52含有一个通孔78、一个环状肩80、一个环状侧壁82以及一个小孔84。通孔78从区域68开始延伸,在环状肩80中终止。环状侧壁82从环状肩80开始延伸,在小孔84中终止。结构18和19也可以称为孔径结构。
封装10密封在成型混料86中,成型混料86的轮廓如某些图中(即图1、1A、1C、2和3)的虚线所示。在本领域中,众所周知,成型混料86可以是任一种电绝缘材料。成型混料86的特点使其适合用于封装10。在本例中,这种成型混料86材料,在使用时,具有合适的粘性,使引线框12和14的形状符合半导体晶片20,并填充空洞/体积40、54、空隙42和50、缝隙48和60等等,除了拉杆90-107末端之外,密封半导体晶片20以及引线框12和14。为了便于填充空洞40,要在结构18中形成多个直通路径108,与空洞40成流体连通。每个直通路径108都从设置在顶面64上的开口109开始延伸,并在设置在顶面64对面的结构18的表面上的开口110中终止。直通路径108也有助于将成型混料86锁定在结构18上。通常,成型混料86为封装10提供一个矩形棱镜的形状,这在图5A和5B的侧视图中表示得更加清晰。
图5A表示结构18的拉杆105和106的末端、结构19的拉杆96、结构16的拉杆97至99以及穿过封装侧壁上的成型混料裸露出来的结构17的拉杆95。与之类似,图5B表示结构18的拉杆103的末端、结构19的拉杆104以及穿过成型混料86裸露出来的结构15的拉杆94。
如图6A中的仰视图所示,结构15的拉杆90至93、结构16的拉杆97至99以及结构17的拉杆95也可以用作半导体封装10的引线。更确切地说,如果半导体晶片是一个功率MOSFET,那么结构15的拉杆90至93可以用作漏极引线,结构16的拉杆97至99可以用作源极引线,通过结构18连接到源极电极20a上,结构17的拉杆95可以用作栅极引线,通过结构19连接到栅极电极20b上。没有用作引线的拉杆的末端,可以通过封装侧壁上的成型混料裸露出来,如图5A-5B所示。例如,拉杆96、105和106的末端(不作引线)通过封装10侧壁上的成型混料86裸露出来,距离封装的底部有一定距离。
虽然如图所示的该封装是一种双侧扁平无引线(DFN)锯齿封装,但是本领域的技术人员应明确,本发明也可用于其它的封装类型。如图6B的俯视图所示,结构18的顶面,通过成型混料86的顶部裸露出来——这可以改善器件的热传导,可以在裸露的顶面上选择安装一个散热片。在本实施例中,结构19相对于结构18的顶部下凹,因此没有通过成型混料86的顶部裸露出来。当然,如同下文中的可选实施例所述的那样,引线框14的顶部也可以不裸露。
参见图7和8,依据另一个实施例,封装110包含引线框112和114,它们可以与由上述引线框12和14相同的材料制成。引线框112被分成两支,实际上是由分离开的结构115和116构成的。结构115与上述结构15大致相同。半导体晶片120也连接到结构115上,连接方式与上述半导体晶片20连接到结构15的方式相同。结构116邻近结构115,并分隔开,与结构115相邻的一侧拥有共同的边界。因此,结构116包含四个分离的拉杆195-198,从结构116开始延伸,远离结构115。拉杆195-198也作为封装110的引线——它们可以作为半导体晶片120的顶部电极(图中没有表示出)的引线。结构115含有六个拉杆190-194和199。拉杆190-193延伸出结构115,与拉杆195-198延伸的方向相反,它们也可作为封装110的引线——更确切地说,它们可以作为半导体晶片120的底部电极(图中没有表示出)的引线。拉杆194和199以相反的方向延伸出结构115,并与拉杆190-193和拉杆195-198垂直。
引线框114是一个单一结构,该结构含有多个拉杆、201-205和207以及排列在三对分离的137、139和141中的多个接触窝点138。因此,封装110是用于二端半导体晶片120,引线框114作为一个引线接头,结构115作为剩余的引线接头。拉杆202和205沿远离半导体晶片120的相反方向延伸。拉杆201和207相互平行地延伸,并远离拉杆203和204。拉杆203和204相互平行地延伸。拉杆202和205沿垂直于拉杆201、203、204和207的方向延伸。以上述接触窝点38的方式配置接触窝点138。一对143直通路径208设置在接触窝点对137和139之间,一对145直通路径208设置在接触窝点对139和141之间。以上述直通路径108的方式配置直通路径208。更确切地说,除了接触窝点138以外,引线框114的所有部分都与半导体晶片120分离开来。以这种方式,体积140限定在引线框114和半导体晶片120之间,结构116与半导体晶片120并排,并分离开来,半导体晶片120限定了它们之间的空隙142,空隙142与体积140成流体连通。利用上述合适的导电粘合剂/结合剂146,将引线框114的一部分144固定连接到结构116上。引线框114和结构116的一部分,延伸出结合剂146,并相互分离开,限定了它们之间的缝隙148。封装110密封在成型混料186中,成型混料186的轮廓如图中虚线所示,它是用与成型混料86相同类型的材料制成。尽管在另一个实施例中引线框114是顶部裸露的,但是如图8的剖面图所示,引线框114的顶部并没有通过成型混料186裸露出来。
参见图1和9,封装210中除了接触窝点238(例如源极窝点)延伸出半导体晶片20的距离比接触窝点52(例如栅极窝点)延伸出半导体晶片20的距离远;窝点238也没有通孔之外,封装210与封装10大致相同。因此,结构218的顶部与拉杆301、302、307和303一起,通过成型混料286裸露出来。因此,封装210中对应结构19的结构(图中没有表示出)用成型混料286密封起来,其顶部没有像上述结构19那样裸露出来。如图所示,接触窝点238含有一个对着半导体晶片20的最低面237。使用成型混料286之后,最低面237裸露出来,也就是说,成型混料286没有填充接触窝点238。然而应明确,某些或全部接触窝点238都可以含有一个开口(图中没有表示出),通过开口,成型混料286可以传播并填充接触窝点238。参照图11-15可以更加全面地理解该内容。然而,用成型混料286填充直通路径308,这有利于将结构218与成型混料286联锁起来。应明确,如果有必要使用成型混料286制备封装210的话,这时所形成的栅极接触结构将与结构218具有相同的高度,在此之后,封装210对应结构19的结构(例如栅极接触结构,图中没有表示出)可以用与结构218类似的方式裸露出来。如图10的仰视图所示,在封装210的底边使用了成型混料286之后,结构215和栏杆290-293、294、295、297-299和300会裸露出来。拉杆293、292、291、290、295、297、298和299也可以用作半导体封装210的引线。
参见图2、9和11,在另一个实施例中,封装310除了接触窝点338含有与直通路径408成流体连通的通道337之外,封装310与封装210相同。因此,半导体封装20像上述结构15那样,连接到结构315上,结构318和319耦合的半导体晶片20上,结构316和317以与结构18和19相同的方式,耦合到半导体晶片20以及结构16和17上。
参见图11至15,通道337有利于用成型混料386填充接触窝点338。更确切地说,位于相邻的接触窝点338之间的结构318上的直通路径408,具有一个延伸到直通路径408的通道337。通道337连接直通路径408两边的各个接触窝点338与直通路径408流体连通,从结构318的顶面延伸并终止在与结构318顶面的相对面相间隔的地方。以这种方式,成型混料386进入到直通路径408中,相同的混料沿通道337传导到接触窝点338中,与它成流体连通。如图16所示的俯视图中的区域387和389。应明确,如图17中的封装410的结构418的拉杆501、503和507所示,通过将拉杆401、403和407的末端延伸到远离顶面364的地方,朝着半导体晶片20向下延伸,结构318具有更加强大的联锁功能。更确切地说,封装410的拉杆501、503和507的一部分并没有通过成型混料486的顶部裸露出来,这一部分提供了更大的表面区域,以便与成型混料486锁定在一起。
参见图7、15、18和19,类似的通道337可以和引线框114一起使用,从而用成型混料586填充接触窝点138。这可以通过具有区域587和589的引线框514,填充有成型混料586来表示。引线框514的顶面564包围着区域587和589,通过成型混料586裸露出来。如同封装610的拉杆701、702-704和707所示,通过将拉杆601、602、603、604和607的延伸到远离顶面564的地方,引线框514就可以具有更加强大的联锁功能。
参见图11和20,双半导体晶片封装710可表示为两个引线框堆栈711和713,共同封装在一个公共的成型混料786中。每个引线框堆栈711和713都与封装310基本相同。因此,这两个半导体晶片720和721包含在封装710中,引线框堆栈711的结构718以及引线框堆栈713的结构719都通过成型混料786裸露出来。引线框堆栈711和713都相互分离开来,并相互电绝缘。含有半导体晶片720和721的等效电路的一个示例,如图22所示,分别含有MOSFET、723和725。
参见图1、11、23、24和25,表示双半导体晶片封装810的另一个实施例,其中制备了一个半桥式电路899。为了这个目的,封装810要含有两个引线框堆栈811和813。引线框堆栈811包含导电结构815、817、819、823和825,以及半导体晶片821。半导体晶片821包含场效应管847,并通过与上述半导体晶片连接到结构15类似的方式,连接到结构815上。结构819包含多个接触窝点837、直通路径807以及通道839,其配置方式与接触窝点338、通道337和直通路径408类似。更确切地说,直通路径807设置在相邻的接触窝点837和通道839之间,并且在接触窝点837和它附近的直通路径807之间延伸。与上述结构18连接到半导体晶片20上的方式类似,结构819也连接到半导体晶片821上。除了接触窝点837以外,结构819像上述封装10那样,与半导体晶片821分离开来。与上述体积40形成在封装10中的方式相同,通过这种方式,体积(图中没有表示出)限定在结构819和半导体晶片821之间。结构823与半导体晶片821并排分离开来,半导体晶片821限定了它们之间的空隙842,空隙842与该体积(图中没有表示出)成流体连通。结构825与半导体晶片821和结构823并排分离开来。结构817含有一个接触窝点853。与上述结构19连接到半导体晶片20和结构17上的方式相同,结构817耦合到半导体晶片821和结构823上。
引线框堆栈813含有导电结构816、818、820、824和826,以及半导体晶片822。半导体晶片822含有场效应管848。与上述结构817、819、823和825,以及引线框堆栈811的半导体晶片821耦合在一起的方式相同,导电结构818、820、824和826,以及半导体晶片822耦合在一起。为了这个目的,与接触窝点837、直通路径807以及通道840的配置方式类似,结构820含有多个接触窝点838、直通路径808以及通道840。像上述引线框堆栈811那样,除了接触窝点838以外,结构820与半导体晶片822分离开来。与体积40形成在封装10中的方式相同,以这种方式,体积(图中没有表示出)限定在结构820和半导体晶片822之间。但是,结构819与结构820不同,结构819含有一个电接触元件860,该元件从前一个电接触元件开始延伸。一个互补的电接触元件862从结构816开始,朝着接触元件860延伸,通过上述任一种合适的导电粘合剂/结合剂,接触元件耦合在一起。以这种方式,半导体晶片822的场效应管848的漏极区,与半导体晶片821的场效应管847的源极区电接触,以形成半桥式电路899。第一和第二引线框堆栈811和813密封在成型混料886中,形成封装810。半桥式电路可以用于功率转换、尤其是直流-直流降压变换器等多种应用。
参见图11、25以及26至29,在另一个实施例中,可以利用封装910制备半桥式电路899。封装910包含重叠的半导体晶片900和902。为了这个目的,封装910含有三个由上述导电材料制成的引线框903、904和905。每对相邻的引线框903、904和905都具有设置在它们之间的半导体晶片900和902的其中之一。引线框903含有六个结构906、907、908、909、910和911。引线框904含有两个结构912和913,这两个结构与结构318和319相同。结构907、910和911分别与结构314、317和316基本相同。与半导体晶片20连接到结构314上的方式相同,半导体晶片900连接到结构907上。与结构318和319连接到半导体晶片20上的方式相同,结构912和913也与之类似地连接到半导体晶片900上。半导体晶片902的场效应管848的漏极区,利用结构912,连接到半导体晶片900的场效应管847的源极区。为了这个目的,例如通过一个导电粘合剂/结合剂层914,半导体晶片902的一端电连接到结构912上。要注意的是,半导体晶片902与结构913绝缘,结构913相对于结构912下凹。通过这种方式,由于半导体晶片902可以非接触地覆盖结构912,因此半导体晶片902可以具有一个较大的晶片尺寸。
参见图25-29,引线框905含有两个结构920和921。结构920含有两对分离的接触窝点922,并有一个直通路径923设置在它们之间。通道924在每对相邻的接触窝点922之间延伸,接触窝点922与设置在每对相邻的接触窝点922之间的直通路径923成流体连通。与上述图15所示的接触窝点338、直通路径408以及通道337相同,配置接触窝点922、直通路径923以及通道924。除了接触窝点922以外,结构920与半导体晶片902分离开来。以这种方式,体积940限定在结构920和半导体晶片902之间。空洞940邻近空隙943,空隙943限定在结构920以及结构912和907之间。利用一个导电粘合剂/结合剂的层944,结构920与结构906电接触,利用一个导电粘合剂/结合剂的层945,结构921与结构908电接触.与之类似,一个导电粘合剂/结合剂层946,将接触窝点922固定到半导体晶片902上,导电粘合剂/结合剂层947,将结构921的接触窝点925固定到半导体晶片902上。除了拉杆950-976末端、结构920的顶部以及引线框903的拉杆底部以外,由虚线所示的成型混料986,密封了半导体晶片900、902、引线框903、904和905。
引线框903的拉杆通过成型混料986裸露出来,它也作为封装910的引线。更确切地说,依据图25所示的半桥式电路,结构906的拉杆950、951、952和954通过连接到结构920和结构906上,可以作为半导体晶片902的源极引。与之类似,结构907的拉杆955、957、959、961可以作为半导体晶片900的漏极引线。结构908的拉杆962通过连接到结构913和结构910上,可以作为半导体晶片902的栅极引线。结构911的拉杆970、975、974通过连接到结构912和结构911上,可以作为半导体晶片900的源极引线,以及半导体晶片902的漏极引线。没有用作引线的拉杆的末端,通过封装侧壁上的成型混料,单独裸露出来,并远离封装的底部。在一个类似于图25和26所示的半桥式结构中,对于功率应用,半导体晶片900可认为是高端FET,半导体晶片902可认为是低端FET。如图26的俯视图所示,拉杆950-976沿垂直方向延伸,从而在组装过程中,尤其是批量组装过程中,具有较好的稳定性和同轴度。
参见图1和30-32,利用批量处理技术,实现了一个与封装10类似的制备封装示例。通过这种方式,形成了一个类似于引线框12的引线框,作为一个引线框阵列1070,如图中的1071-1074所示。为了便于讨论,图中仅表示出了四个引线框。例如,阵列1070可以由四行四列排布的16个引线框构成。阵列1070含有一个包围着阵列1070的框1075。如图中半导体晶片所示,1076-1079分别连接到上述引线框1071-1074上。类似于引线框14的引线框,也相似地排列在阵列980中,如图中的引线框981-984所示。配置阵列1070和980,使每个引线框1071-1074都与引线框981-984的其中之一有关。因此,可能有16个引线框与阵列980有关,但是为了便于讨论,仅仅表示出了四个。当阵列1070和980配置得当时,框985包围着阵列980,并与框1075校准。确切地说,配置阵列1070和980,使其与引线框981-984的其中之一以及相应的半导体晶片1076-1079重叠,并将每个引线框1071-1074与引线框981-984的其中之一以及相应的半导体晶片1076-1079校准,构成一个阵列堆栈1086。为了这个目的,框1075含有多个校准孔987,框985含有多个校准突起988。配置突起988和孔987,以便在突起988带有孔987的其中之一的上方,在阵列1070和980之间建立合适的校准。通过这种方式,可以同时高效地制备多个封装。垂直方向上,来自于引线框1071-1074和981-984的多个拉杆,在批量处理时,保持引线框校准。此后,利用成型混料,可以将引线框的阵列分成单独的封装。利用引线框的阵列,同时制备封装的顶部和底部,如图5A-5B所示,导致引线框拉杆的末端都通过成型混料裸露出来。没有用作引线的拉杆末端,通过封装侧壁上的成型混料,远离封装的底部。
与之类似,为了制备与图26-29所示的封装910类似的引线框结构,可以从如图31所示的结构类似的图33-35所示的工艺开始继续进行。与图26E所示的类似,可以将第二半导体晶片996-999连接到引线框981-984的顶部。然后,具有框995的顶部引线框991-994的阵列990,可以连接到第二半导体晶片996-999上,形成一个类似于图26所示的封装910的结构。为了这个目的,如图35所示,阵列980的框995的额外的突起989,刚好适合阵列980的框985的突起988的顶部。成型混料可以形成在引线框堆栈附近,例如通过锯割或打孔,将封装分开。利用引线框阵列同时制备,使每个引线框的拉杆末端通过成型混料裸露出来。
用于制备图26所示的封装910的堆栈式引线框结构的工艺流程如图36所示。工艺1100从步骤1110开始,制备一个底部引线框(可以是一个一起连接在一个框上的底部引线框的阵列),随后的晶片步骤1120,将第一半导体晶片连接到底部引线框上。然后,将中间引线框(可以是一个一起连接在一个框上的中间引线框的阵列)连接到第一半导体晶片的顶部,使第一半导体晶片在步骤1130中,位于第一和第二引线框之间。在步骤1140中,第二半导体晶片连接到中间引线框的顶部,在步骤1150中,顶部引线框(可以是一个一起连接在一个框上的顶部引线框的阵列)连接到第二半导体晶片的顶部。在步骤1160中使用成型混料,然后在步骤1170中,例如通过锯割或打孔,将半导体封装分成单独的封装,形成如图26所示的类似于910的封装。
尽管本发明的内容已经通过上述优选实施例作了详细介绍,但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后,对于本发明的多种修改和替代都将是显而易见的。因此,本发明的保护范围应由所附的权利要求来限定。
Claims (27)
1.一个引线框封装,其特征在于,该封装包含:
一个第一引线框,所述的第一引线框是导电的;
一个第二引线框,与所述的第一引线框重叠,所述的第二引线框的一部分与所述的第一引线框分离开来,所述的第二引线框是导电的;
一个设置在所述的第一和第二引线框之间的第一半导体晶片,所述的第一半导体晶片具有电连接到所述的第一和第二引线框上的接头;
一个第二半导体晶片,接合并电连接到所述的第二引线框;
一个第三引线框,与所述的第一和第二引线框重叠,是导电的,并与所述的第二半导体晶片电接触;以及,
所设置的成型混料,用于密封一部分所述的封装。
2.如权利要求1所述的引线框封装,其特征在于,其中每个第一、第二和第三引线框都还包含多个拉杆,其中拉杆的末端通过封装侧壁上的成型混料裸露出来。
3.如权利要求2所述的引线框封装,其特征在于,其中不作为引线的拉杆末端,通过封装侧壁上的成型混料裸露出来。
4.如权利要求2所述的引线框封装,其特征在于,其中所述的第一和第三引线框具有在相互垂直的方向上延伸的拉杆。
5.如权利要求1所述的引线框封装,其特征在于,其中所述的第一和第二半导体晶片为功率场效应管FET。
6.如权利要求5所述的引线框封装,其特征在于,其中所述的第一和第二半导体晶片通过所述的第二引线框,串联在一起,构成一个半桥式电路。
7.如权利要求1所述的引线框封装,其特征在于,其中所述的第二引线框还包含一个额外的导电结构,该导电结构电接触所述的第一半导体晶片,但不接触第二半导体晶片。
8.如权利要求7所述的引线框封装,其特征在于,其中所述的第二半导体晶片与一部分所述的额外的导电结构重叠。
9.如权利要求8所述的引线框封装,其特征在于,其中所述的额外的导电结构的顶部从所述的第二半导体晶片下凹。
10.如权利要求1所述的引线框封装,其特征在于,其中所述的第二和第三引线框具有与所述的第一和第二半导体晶片分离开来的部分,分别限定各自的体积,并且具有各自的直通路径,在所述的第二和第三引线框的相对面之间延伸,所述的各自的直通路径与所述的各自的体积成流体连通。
11.如权利要求10所述的引线框封装,其特征在于,其中每个所述的第二和第三引线框都含有多个分离的窝点,每个窝点由从所述的相对面当中的一个开始,朝向所述的第一或第二半导体晶片延伸的一部分来限定,一对所述的窝点具有一个在它们之间延伸的通道,所述的通道从所述的相对面当中的一面开始延伸,终止在与所述的相对面当中的剩余一面相间隔的地方。
12.一个引线框封装,其特征在于,该封装包含:
一个第一结构,所述的第一结构是导电的;
一个第二结构,与所述的第一结构重叠,所述的第二结构的一部分与所述的第一结构分离开来,所述的第二结构是导电的;
一个设置在所述的第一和第二结构之间的半导体晶片,所述的半导体晶片具有电连接到所述的第一和第二结构上的接头;并且
所设置的成型混料,用于密封一部分封装,其中每个所述的第一结构和第二结构都还含有在相互垂直方向上延伸的拉杆。
13.如权利要求12所述的引线框封装,其特征在于,其中所述的拉杆末端通过所述的成型混料裸露出来。
14.如权利要求12所述的引线框封装,其特征在于,其中半导体晶片是一个功率场效应管FET。
15.如权利要求12所述的引线框封装,其特征在于,该封装还包含:
一个第三结构,所述的第三结构是导电的,一部分所述的第三结构与所述的第一结构在同一平面中;
一个第四结构,与所述的第三结构重叠,所述的第四结构是导电的;以及
一个设置在所述的第三和第四结构之间的第二半导体晶片,所述的第二半导体晶片具有电连接到所述的第三和第四结构上的接头,其中所述的第三和第四结构以及第二半导体晶片位于在水平方向上邻近所述的第一和第二结构的地方。
16.如权利要求15所述的引线框封装,其特征在于,其中所述的第二结构电连接到所述的第三结构上。
17.如权利要求12所述的引线框封装,其特征在于,其中所述的第二结构的一部分与所述的半导体晶片分离开来,限定了一个体积,并具有一个在所述的第二结构的相对面之间延伸的直通路径,所述的直通路径与所述的体积成流体连通。
18.如权利要求17所述的引线框封装,其特征在于,其中所述的第二结构含有多个分离的窝点,每个窝点由从所述的相对面当中的一面开始,朝向所述的半导体晶片延伸的一部分来限定,一对所述的窝点具有一个在它们之间延伸的通道,所述的通道从所述的第二结构的所述的相对面当中的一面开始延伸,终止在与所述的相对面当中的剩余一面相间隔的地方。
19.一种用于制备引线框封装的方法,其特征在于,所述的方法包含:
制备一个第一引线框;
将第一半导体晶片固定在第一引线框上;
将第二引线框固定在所述的第一半导体晶片上,所述的第一半导体晶片设置在所述的第一和第二引线框之间;
将第二半导体晶片固定在所述的第二引线框上,所述的第二引线框设置在所述的第一和第二半导体晶片之间,并将所述的第一半导体晶片上的接头电连接到所述的第二半导体晶片上的接头上;
将第三引线框固定在所述的第二半导体晶片上,所述的第二半导体晶片设置在所述的第二和第三引线框之间;
将所述的半导体晶片密封在非导电的成型混料中;并且
分离所述的封装。
20.如权利要求19所述的方法,其特征在于,其中每个引线框都含有多个拉杆,其中所述的分离使所述的多个拉杆的末端通过所述的非导电成型混料裸露出来。
21.如权利要求20所述的方法,其特征在于,其中某些拉杆的末端不用作封装的引线,这些末端通过封装的侧壁裸露出来。
22.如权利要求20所述的方法,其特征在于,其中第二和第三引线框的一部分还包含沿相互垂直方向延伸的拉杆。
23.如权利要求19所述的方法,其特征在于,其中第一和第二半导体晶片为功率场效应管(FET),其中之所以将第二半导体晶片固定,是为了使一个半导体晶片的源极,通过所述的第二引线框,电连接到另一个半导体晶片的漏极上。
24.如权利要求19所述的方法,其特征在于,其中制备第一引线框还包含制备所述的第一引线框的一个第一阵列,连接到第一框上,
其中所述的固定第二引线框还包含,将连接在第二框上的所述的第二引线框的第二阵列固定到所述的第一半导体晶片上,
其中所述的固定第三引线框还包含,将连接在第三框上的所述的第三引线框的第三阵列固定到所述的第二半导体晶片上,以及
其中所述的分离所述的封装还包含,将引线框所述的阵列分离成单独的封装。
25.如权利要求23所述的方法,其特征在于,其中所述的第二引线框还包含一个额外的导电结构,该导电结构电连接到所述的第一半导体晶片上,但不连接到所述的第二半导体晶片上,所述的额外的导电结构从所述的第二半导体晶片下凹。
26.一种半导体封装,其特征在于,该封装包含:
一个第一结构,所述的第一结构是导电的;
一个第二结构,与所述的第一结构分离开来,并重叠,所述的第二结构是导电的;
一个第一半导体晶片,设置在所述的第一和第二结构之间,所述的第一半导体晶片具有电连接到所述的第一和第二结构的接头;
一个第二半导体晶片,连接到所述的第二结构上,使第二结构位于第一和第二半导体晶片之间,并且电连接到第一和第二半导体晶片上;以及
一个第三结构,与所述的第二结构分离开来,并重叠,所述的第三结构是导电的,并与所述的第二半导体晶片电接触。
27.如权利要求26所述的半导体封装,其特征在于,其中第一和第二半导体晶片为功率场效应管,串联在一起,构成一个半桥式电路。
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US8513784B2 (en) | 2013-08-20 |
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US20110227205A1 (en) | 2011-09-22 |
US8815649B2 (en) | 2014-08-26 |
US20130302946A1 (en) | 2013-11-14 |
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