CN113394187A - 无引线半导体封装件以及制造方法 - Google Patents

无引线半导体封装件以及制造方法 Download PDF

Info

Publication number
CN113394187A
CN113394187A CN202011526201.7A CN202011526201A CN113394187A CN 113394187 A CN113394187 A CN 113394187A CN 202011526201 A CN202011526201 A CN 202011526201A CN 113394187 A CN113394187 A CN 113394187A
Authority
CN
China
Prior art keywords
semiconductor device
terminals
leadframe
packaged semiconductor
leadless packaged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011526201.7A
Other languages
English (en)
Inventor
周安乐
王飞莹
张贵祥
闭香红
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anshi Co ltd
Original Assignee
Anshi Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anshi Co ltd filed Critical Anshi Co ltd
Publication of CN113394187A publication Critical patent/CN113394187A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本公开涉及无引线封装的半导体装置，包括相对的顶部主表面和底部主表面以及在顶部表面与底部表面之间延伸的侧壁，无引线封装的半导体装置还包括：引线框结构，其包括各自具有布置在其上的半导体晶片的两个或更多个引线框子结构的阵列；端子；以及轨道，延伸横过半导体装置的底部表面，其中，轨道提供用于互连半导体晶片和端子的区域，其中，轨道被绝缘材料填充以隔离引线框子结构。

Description

无引线半导体封装件以及制造方法
技术领域
本发明涉及形成无引线封装的半导体装置的方法。本发明还涉及无引线封装的半导体装置。
背景技术
已知无引线封装的半导体装置提供优于引线封装件的优点。这些优点包括：在降低引线电感方面具有更好的电气性能；通过使用暴露的散热垫来改善向印刷电路板(PCB)的热传递的良好的散热；减小的封装厚度；以及减小了PCB上占用的面积的较小的占位面积。无引线封装的半导体装置的示例包括四方扁平无引线(QFN)装置和双扁平无引线(DFN)装置。然而，无引线封装的半导体装置的缺点在于，当安装在PCB上时，检查焊点是困难的。传统的检查技术利用所谓的自动光学检查(AOI)系统，从而相机扫描安装在PCB上的无引线封装的半导体装置，以用于各种缺陷，诸如开路连接、短路连接、焊料连接的薄化以及错误放置的装置。由于半导体装置输入/输出(I/O)端子布置在该装置的底部且因此在将装置安装在PCB上时从视图上被隐藏，因此，通常无法将AOI系统与无引线半导体装置一起使用。自动X射线检查(AXI)系统可能允许检查焊点，然而，AXI系统是昂贵的。
允许焊点通过AOI检查的解决方案包括金属侧垫，其从装置的底部上的装置I/O端子至少部分向上延伸到装置的外侧壁。通常，金属侧垫可以由锡、铅或锡铅合金形成。在将装置附着到PCB的焊接工艺期间，焊料将润湿装置的底部上的I/O端子以及金属侧垫。结果，焊点的一部分将是可见的，这允许通过AOI技术进行检查。只要正确焊接了金属侧垫，即使I/O端子未正确焊接到PCB，也可以认为焊点是良好的。
除了易于检查之外，金属侧垫可以减小装置在安装在PCB上时的倾斜。由于增大的焊接面积，金属侧垫还可以改善剪切和弯曲性能。
通常，封装件结构将包括嵌入封装层中的装置晶片阵列。装置晶片将通过诸如共晶接合的任何合适的方式连接到引线框。形成这种无引线装置的工艺涉及使用一系列的平行的行切割和平行的列切割将封装的集成电路的二维阵列分成单个半导体装置封装件。第一系列的平行的分离切割完全延伸穿过限定阵列行的引线框和封装层。在这种工艺中，将暴露出I/O端子，并且由于I/O端子相互电连接，因此可以电镀暴露的I/O端子以形成金属侧垫。电连接有必要维持电连续性，使得可以实现电镀工艺。
在电镀金属侧垫之后，使得第二系列的平行的分离切割完全延伸穿过引线框和封装层。这将阵列的列分开，从而提供单个化的封装件。
然而，对于具有一个或多个功能晶片和定位在装置的一个侧壁处的至少三个I/O端子以及定位在相对侧壁处的至少两个I/O端子的无引线半导体装置，因为分离切割工序要求定位在形成在引线框上的引线框结构上的装置的一个侧壁处的中间的I/O端子将被电隔离，因此不可能根据以上工艺通过电镀来形成侧垫。
图1a示出了由一系列的引线框子结构形成的典型的引线框结构10。
在用于限定行的第一分离切割工序之前，如以上所讨论的，由于用于特定装置引线框的六个I/O端子12、14和16(装置的两个相对侧上的三个I/O端子)中的每一个将通常通过在金属板上进行光蚀刻工艺由单个金属整体形成，因此它们电互连。现在参照图1b，在第一切割工序(由线A指示)之后，I/O端子12、14将从引线框结构10脱离，因此其将不可能电镀I/O端子12、14以形成金属侧垫，因为它们将从引线框结构机械脱离，并且与引线框结构电隔离。
在基本正交于第一切割工序的第二切割工序(由线B指示)之后，每个单独的子引线框将从引线框结构10单个化(singulate)。
如上所述的无引线封装的半导体装置的缺点在于其限于具有金属侧垫的最多四个端子。
发明内容
各种示例实施例针对如上所述的缺点和/或可以从以下公开中变得显而易见的其他缺点。
根据本发明的实施例，无引线封装的半导体装置包括相对的顶部主表面和底部主表面以及在顶部表面与底部表面之间延伸的侧壁。其还包括引线框结构，该引线框结构包括两个或更多个引线框子结构的阵列，每一个引线框子结构具有布置在其上的半导体晶片。另外，无引线封装的半导体装置包括端子和延伸横过半导体装置的底部表面的轨道。轨道提供用于在制造期间互连半导体晶片和端子的区域。轨道被绝缘材料填充以隔离引线框子结构。
根据本发明的实施例，端子中的每一个包括相应的金属侧垫。
根据本发明的实施例，无引线封装的半导体装置可以包括四个或更多个端子。
根据本发明的实施例，绝缘材料是焊接掩模或封装剂。
根据本发明的实施例，半导体晶片和相应的端子可以机械连接且电连接。
根据本发明的实施例，端子使用诸如锡、铅或锡铅化合物的电镀材料进行镀覆。
本发明还涉及一种汽车(automotive)部件，包括如前述实施例中的一个中指定的无引线封装的半导体装置。由于在汽车工业中使用了AOI系统，这是特别有用的。
本发明的一个实施例涉及一种形成无引线封装的半导体装置的方法，该装置包括引线框结构，该引线框结构包括引线框子结构的阵列，每一个引线框子结构具有布置在其上的半导体晶片。该方法包括以下步骤：
设置在所述引线框子结构的端子与所述引线框结构的端子之间的电连接；
设置封装层以封装引线框子结构和各个半导体晶片；
执行延伸穿过所述引线框结构和所述封装层的第一系列的平行切割，以暴露出形成端子的侧部分；
电镀端子以形成金属侧垫；
在引线框结构中形成一系列沟槽，其中，该沟槽延伸横过无引线封装的半导体装置的底部表面；
用绝缘材料填充沟槽；以及
执行相对于第一系列的平行切割成角度的第二系列的平行切割，第二系列的平行切割延伸穿过引线框结构和封装层以使无引线封装的半导体装置单个化。
在本发明的另一实施例中，该方法还可以包括去毛刺步骤，以从端子去除任何剩余的封装层。在电镀步骤之前执行这种去毛刺步骤。
附图说明
为了其中可以详细地理解本公开的特征的方式，参照其中的一些示出在附图中的实施例进行了更具体的描述。然而，应注意，附图仅示出了典型的实施例，因此不应认为是对其范围的限制。附图用于促进对本公开的理解，因此不一定按比例绘制。在结合附图阅读本说明书后，所要求保护的主题的优点对于本领域技术人员而言将变得显而易见，在附图中，同样的附图标记已经用于表示同样的元件，并且在附图中：
图1a示出了已知的引线框结构；
图1b示出了指示分离切割的位置的已知的引线框结构；
图2示出了根据实施例的引线框结构；
图3示出了根据实施例的用于形成无引线半导体装置的工艺流程图；
图4a至图4e示出了根据实施例的用于形成无引线半导体装置的工艺流程步骤；
图5a示出了引线框结构中的单个装置在开槽工艺之后的底视图；以及
图5b示出了根据实施例的完成的无引线封装的半导体装置的相应底侧视图和顶侧视图。
具体实施方式
在附图和以下描述中，同样的附图标记表示同样的特征。总的来说，图2中示出了根据实施例的被称为单元结构的引线框结构20。引线框结构20由互连的子结构的二维(2D)阵列形成，每个互连的子结构构成在单个化时用于无引线封装的半导体装置的单个引线框22、28。在该示例中，每个引线框包括两组三个I/O端子25，然而，本领域技术人员将理解，I/O端子的数量可以如通过封装类型要求的而变化。引线框22、28中的每一个还包括至少两个晶片附着区域27，半导体装置晶片(图2中未示出)可以附着到至少两个晶片附着区域27中的每一个上，如以下所讨论的。两组I/O端子中的每一个与晶片附着区域27中的每一个关联，使得可以对装置晶片进行合适的连接。需要两个晶片的应用包括双晶体管布置，诸如共源共栅晶体管或双二极管。
晶片附着区域27一体地连接到各个I/O端子25，然而，晶片附着区域27被配置和布置为在分离工艺之后与I/O端子25断开，如下所讨论的。在分离之前，I/O端子25中的每一个例如通过系杆(tie bar)
29的方式一体地连接到各个晶片附着区域27。如以下所讨论的，将晶片附着区域27连接到I/O端子25的系杆29被布置为在分离工艺期间被切断或被折断。I/O端子25被布置为使得它们沿着两个平行的轴(被称为引线侧轴)来形成，从而限定阵列或者引线框22、28中的行。引线框结构20通常通过光刻工艺由涂覆有钯金的金属铜合金板来形成。
图3示出了根据实施例的用于制造无引线封装的半导体装置的工艺流程图。图4a至图4e示出了对应于图3的工艺流程的工艺步骤。参照图3的工艺流程和图4a至图4e的工艺流程，在形成如以上所讨论的引线框结构20之后，通过晶片附着步骤30中的晶片接合，将装置晶片40附着到晶片附着区域27(图2中所示)。装置晶片40可以通过任何合适的方式(诸如晶片附着区域27与装置晶片40的背侧金属化之间的共晶接合43或胶粘合剂43)附着到晶片附着区域27。以这种方式，装置晶片40机械连接且电连接至各个I/O端子25。
还参照图4a，在晶片接合步骤30之后，线接合件41根据图3的线接合工艺步骤32从装置晶片40的触点连接至各个引线框22、28(图2中所示)的各个I/O端子25。线接合工艺可以是使用金、铜、铝或银线或者使用金属夹片接合的任何合适的线接合工艺。
如图4b中所示，在线接合之后，利用图3的模制步骤34将引线框22、28的阵列和装置晶片40封装在模制化合物42中。该封装限定了无引线封装的半导体装置的第一组相对侧壁。该封装工艺可以是如本领域技术人员所理解的任何合适的半导体封装工艺。
在封装之后，利用图3的斩波器切割步骤35在引线框结构20中进行第一系列的平行切割，如图4b中所示。参照图2，平行的一系列切割是分离切割，沿着I/O端子25的线沿水平或X轴路径(X-X)进行，以限定引线框22、28的单独的行。这些第一分离切割使得引线框22、28的行中的引线框保持电连接和机械连接。因为引线框中的每个行是电连接的，因此如以下所讨论的，有可能针对构成该行的各个引线框中的每一个利用图3的电镀步骤36对I/O端子25(如图2中所示)中的每一个进行金属侧焊垫的电镀。
分离切割还去除I/O端子25(如图2中所示)附近的封装，使得它们可以利用图3的电镀步骤36进行电镀，以形成图4c中所示的金属侧垫44。该电镀可以通过如本领域技术人员理解的任何合适的工艺来实现。通常，金属侧垫44将使用诸如锡或可替代的铅或者锡铅化合物的电镀材料进行镀覆。另外，以这种方式，I/O端子25中的每一个上的金属侧垫的电镀(图5a和图5b中更清楚地示出)是可能的。如技术人员还将理解，该电镀步骤还将导致引线框结构20的底部表面被电镀，使得电镀材料将延伸横过I/O端子25之间的底部表面。为了确保I/O端子25的电隔离，使得最终的装置中的各个I/O端子之间没有电连续性，电镀材料和系杆29应被切断。
切断电镀材料和系杆29通过图3的开槽步骤37来实现，从而如图4d的左侧上所示，通过切穿引线框20材料以形成延伸穿过封装材料42的第一沟槽46，从晶片附着区域27切断I/O端子25中的一个。
这种开槽步骤使得使用系杆29材料中的典型的半蚀刻特征。这是一种常见的工业设计，以减少对锯切工艺的工作负载。然而，也可能不进行半蚀刻，但是在那种情况下，必须将锯切工艺切入封装件深处，以便于完全去除金属连接。
可选地，另一开槽步骤可以用于形成部分地穿过系杆29a(图5a中所示)材料的第二沟槽48，其中，沟槽形成在晶片附着区域27(图2中和图5a中所示)与图4d的右侧上的第二I/O端子之间。系杆29a的系杆29的替代设计，并且还可以设计有或不具有半蚀刻特征。在图5a中所示的示例实施例中，系杆29被沟槽46完全切断，因此在图5a中不再可见，并且以这种方式，端子25被隔离。图5a中的系杆29a被部分切断，并且保持连接端子25a与晶片垫27。
一些金属侧垫44(也被称为端子，例如，两个晶片封装件示例中的图5a中的端子25a)可以连接到晶片附着区域，使得可以节省一根接合线。图4d的右侧上不是所有的端子连接到晶片附着区域。因此，沟槽48(如图4d中所示)仍然有必要将这些端子与晶片附着垫隔离。
在如图3中所示的步骤37的开槽工艺之后，第一沟槽46和第二沟槽48随后使用如图4e中所示的绝缘材料轨道(track)49利用回填工艺步骤38进行回填。绝缘材料填充沟槽46、48以覆盖作为开槽工艺的结果暴露出的引线框材料。暴露的引线框金属会由于开槽而出现污点，这会缩短两种暴露的金属之间的间隙。尤其是在最终用户应用中高度污染的环境中存在爬电的风险。回填工艺步骤38确保回填覆盖暴露的金属，以防止这种应用问题。如图4e中所示，绝缘材料轨道49延伸横过半导体装置的宽度，并且从不包含I/O端子25(如图2中所示)的第一侧壁到不包含I/O端子的第二侧壁基本平行。
如图3中所示，在工艺步骤最终切割39中进行最终的分离切割，以将半导体装置与在第一水平分离切割之后形成的引线框22、28(如图2中所示)的行分开。与第一水平分离切割正交地进行最终的分离切割。如图5b中所示，该最终的分离切割产生了最终的无引线封装的半导体装置50。
图5b示出了完成的无引线封装的半导体装置的相应底侧视图和顶侧视图。图5b示出了根据实施例的完成的无引线半导体装置的透视底视图。金属侧垫44从各个I/O端子25(如图2中所示)形成在该装置的侧壁上。如技术人员将理解，金属侧垫(从图5b中的视图被遮挡)也设置在该装置的相对侧壁上。图5b还示出了形成在沿着半导体装置的底侧的宽度延伸的沟槽46、48(如图5a中所示)中的绝缘材料49。
尽管图5b示出了两个晶片封装件，但是本发明的所有实施例还应用于通用于任何逻辑装置的单个晶片封装件和/或具有多于2个晶片的封装件。
附加的处理步骤可以包括去毛刺，以从I/O端子去除任何封装化合物，这可以在电镀金属侧垫之前执行。在单个化之后，可以使用其他清洁步骤从最终的装置中去除材料。也可以进行最终的视觉检查。
在所附的独立权利要求中阐述了本发明的特定和优选方面。来自从属权利要求和/或独立权利要求的特征的组合可以适当地组合，而不仅是如权利要求中所阐述的。
本公开的范围包括显式地或隐式地公开在其中的任何新颖特征或这些特征的组合或其任何概括，而不论其是否涉及要求保护的发明或者减轻了由本发明解决的任何或所有问题。申请人特此通知，在本申请或由此衍生的任何此类进一步申请的起诉期间，可以对这些特征提出新的权利要求。特别地，参照所附权利要求，可以将从属权利要求的特征与独立权利要求的特征组合，并且可以以任何合适的方式而不是仅仅以权利要求中列举的特定组合来组合来自各个独立权利要求的特征。
在单独的实施例的上下文中描述的特征也可以在单个实施例中组合提供。相反，为简洁起见，在单个实施例的上下文中描述的各种特征也可以单独地或以任何合适的子组合来提供。
术语“包括”不排除其他元件或步骤，术语“一”或“一个(种)”不排除多个。权利要求中的附图标记不应解释为限制权利要求的范围。

Claims (10)

1.一种无引线封装的半导体装置，包括相对的顶部主表面和底部主表面以及在所述顶部表面与所述底部表面之间延伸的侧壁，所述无引线封装的半导体装置还包括：
引线框结构，其包括两个或更多个引线框子结构的阵列，每一个引线框子结构具有布置在其上的半导体晶片；
端子；以及
轨道，其延伸横过所述半导体装置的底部表面，其中，所述轨道提供用于互连所述半导体晶片和所述端子的区域；
其中，所述轨道被绝缘材料填充以隔离所述引线框子结构。
2.根据权利要求1所述的无引线封装的半导体装置，其中，所述端子中的每一个包括相应的金属侧垫。
3.根据权利要求1所述的无引线封装的半导体装置，其中，无引线封装的半导体装置包括四个或更多个端子。
4.根据权利要求1所述的无引线封装的半导体装置，其中，所述绝缘材料为封装剂和/或焊接掩模。
5.根据权利要求1所述的无引线封装的半导体装置，其中，所述半导体晶片和相应的端子机械连接且电连接。
6.根据权利要求1所述的无引线封装的半导体装置，其中，所述端子用诸如锡、铅或锡铅化合物的电镀材料镀覆。
7.一种汽车部件，包括根据权利要求1至6中任一项所述的无引线封装的半导体装置。
8.一种形成根据权利要求1至6中任一项所述的无引线封装的半导体装置的方法。
9.一种形成无引线封装的半导体装置的方法，所述无引线封装的半导体装置包括引线框结构，所述引线框结构包括引线框子结构的阵列，每一个引线框子结构具有布置在其上的半导体晶片，所述方法包括以下步骤：
设置在所述引线框子结构的端子与所述引线框结构的端子之间的电连接；
设置封装层以封装所述引线框子结构和各个半导体晶片；
执行延伸穿过所述引线框结构和所述封装层的第一系列的平行切割，以暴露出形成端子的侧部分；
电镀所述端子以形成金属侧垫；
在所述引线框结构中形成沟槽，其中，所述沟槽延伸横过所述无引线封装的半导体装置的底部表面；
用绝缘材料填充所述沟槽；以及
执行相对于所述第一系列的平行切割成角度的第二系列的平行切割，所述第二系列的平行切割延伸穿过所述引线框结构和所述封装层，以使所述无引线封装的半导体装置单个化。
10.根据权利要求9所述的形成无引线封装的半导体装置的方法，其中，所述方法还包括去毛刺步骤，以从所述端子去除任何剩余的封装层，其中，在电镀步骤之前执行所述去毛刺步骤。
CN202011526201.7A 2020-03-11 2020-12-22 无引线半导体封装件以及制造方法 Pending CN113394187A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP20162403.8 2020-03-11
EP20162403.8A EP3879569A1 (en) 2020-03-11 2020-03-11 A leadless semiconductor package and method of manufacture

Publications (1)

Publication Number Publication Date
CN113394187A true CN113394187A (zh) 2021-09-14

Family

ID=69804657

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011526201.7A Pending CN113394187A (zh) 2020-03-11 2020-12-22 无引线半导体封装件以及制造方法

Country Status (3)

Country Link
US (1) US11631634B2 (zh)
EP (1) EP3879569A1 (zh)
CN (1) CN113394187A (zh)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7816186B2 (en) * 2006-03-14 2010-10-19 Unisem (Mauritius) Holdings Limited Method for making QFN package with power and ground rings
TW201539674A (zh) * 2014-04-10 2015-10-16 Chipmos Technologies Inc 四方扁平無引腳封裝及其製造方法
EP2980845B1 (en) * 2014-08-01 2019-11-27 Nexperia B.V. A leadless semiconductor package and method
US9425130B2 (en) * 2014-10-29 2016-08-23 Nxp B.V. Package with multiple I/O side-solderable terminals
US9640463B2 (en) * 2015-06-22 2017-05-02 Nexperia B.V. Built-up lead frame package and method of making thereof
JP6828959B2 (ja) * 2017-01-17 2021-02-10 大口マテリアル株式会社 リードフレームおよびその製造方法
DE102017129924B4 (de) * 2017-12-14 2021-04-29 Infineon Technologies Ag Verkapseltes, anschlussleiterloses package mit zumindest teilweise freiliegender innenseitenwand eines chipträgers, elektronische vorrichtung, verfahren zum herstellen eines anschlussleiterlosen packages und verfahren zum herstellen einer elektronischen vorrichtung

Also Published As

Publication number Publication date
US11631634B2 (en) 2023-04-18
EP3879569A1 (en) 2021-09-15
US20210287972A1 (en) 2021-09-16

Similar Documents

Publication Publication Date Title
US7608930B2 (en) Semiconductor device and method of manufacturing semiconductor device
US7579674B2 (en) Semiconductor package configuration with improved lead portion arrangement
US8115299B2 (en) Semiconductor device, lead frame and method of manufacturing semiconductor device
US6437429B1 (en) Semiconductor package with metal pads
US7436049B2 (en) Lead frame, semiconductor chip package using the lead frame, and method of manufacturing the semiconductor chip package
US9443791B2 (en) Leadless semiconductor package and method
US9177836B1 (en) Packaged integrated circuit device having bent leads
US20090032977A1 (en) Semiconductor device
US20150021751A1 (en) Semiconductor device with plated pillars and leads
KR20160006608A (ko) 리드 프레임, 반도체 장치, 및 리드 프레임의 제조 방법
US20080197464A1 (en) Integrated Circuit Device Package with an Additional Contact Pad, a Lead Frame and an Electronic Device
US8659133B2 (en) Etched surface mount islands in a leadframe package
US10861828B2 (en) Molded semiconductor package having a package-in-package structure and methods of manufacturing thereof
US9355995B2 (en) Semiconductor packages utilizing leadframe panels with grooves in connecting bars
CN113496977A (zh) 共源共栅半导体装置和制造方法
EP2973690B1 (en) Stack die package
US11631634B2 (en) Leadless semiconductor package and method of manufacture
US8097952B2 (en) Electronic package structure having conductive strip and method
KR20020093250A (ko) 리드 노출형 리드 프레임 및 그를 이용한 리드 노출형반도체 패키지
KR100291511B1 (ko) 멀티 칩 패키지
US20240055327A1 (en) Pre-plated lead tip for wettable flank leadframe
US20220246505A1 (en) Semiconductor device and a method of manufacturing a semiconductor device
KR100370480B1 (ko) 반도체 패키지용 리드 프레임
KR100268922B1 (ko) 반도체패키지및그제조방법
CN117316911A (zh) 具有可润湿引线侧面和连接杆的半导体封装及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination