TW201330189A - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TW201330189A
TW201330189A TW101137592A TW101137592A TW201330189A TW 201330189 A TW201330189 A TW 201330189A TW 101137592 A TW101137592 A TW 101137592A TW 101137592 A TW101137592 A TW 101137592A TW 201330189 A TW201330189 A TW 201330189A
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lead frame
conductive element
metal substrate
package structure
input
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TW101137592A
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TWI485819B (zh
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Bau-Ru Lu
Jeng-Jen Li
Kai-Ping Chiang
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Cyntec Co Ltd
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Abstract

本發明揭露一種由金屬基板和導線架結合組成之封裝結構。在一具體實施中，在該金屬基板中形成一凹洞，且具有至少一第一輸入/輸出端子之一第一傳導元件於該凹洞中接合。在該金屬基板上形成一導線架，且此導線架包含複數個電性連接端用以連接該第一傳導元件之至少一第一輸入/輸出端子。在另一具體實施中，在該導線架的空隙中設置另一傳導元件。本發明亦揭露一種由金屬基板和導線架結合組成之封裝結構的製造方法。

Description

封裝結構及其製造方法
本發明係有關一種封裝結構，特別指一種由金屬基板和導線架結合組成之封裝結構。
導線架(lead frame)是一種被應用在積體電路(IC)封裝的材料，其具有不同的型式，例如四邊接腳扁平式封裝(QFP)、薄小外型封裝(TSOP)、小外型晶體管(SOT)或J型接腳小外型封裝(SOJ)。藉由組裝和互相連結一半導體元件至一導線架來構成封膠(molding)的半導體元件，此結構常常使用塑性材料封膠。一導線架由金屬帶狀物(metal ribbon)構成，且具有一槳狀物(paddle)(亦為已知的晶粒槳狀物(die paddle)，晶粒附加標籤(die-attach tab)，or島狀物(island))，一半導體元件設置在該槳狀物上。前述導線架具有複數個導線(lead)不與該槳狀物重疊排列。
傳統上，積體電路晶片係使用晶粒結合(die bond)的方式設置在導線架上。前述晶粒結合的製造程序包含很多步驟：打線(wire bond)、積體電路晶片封膠、切單後測試等等。藉由整合或封裝導線架和其他元件，例如電感或電容，可以製造不同的產 品。因為製程容易、成熟且信賴性良好，為目前最主要製程之一。然而，這種傳統製程有很多的缺點，其包含：a.製程成本高，且須使用模具來完成封膠，因此增加模具開發的成本；b.設計面積只能平面而缺乏設計彈性，產品無法縮小；c.只能封裝成單顆元件，並不具模組化的能力；d.散熱表現不佳。
因此，本發明提出了一個封裝結構及其製程方法來克服上述之缺點。
本發明之一目的係提供一個封裝結構，其包含在金屬基板上形成一凹洞，使具有至少一第一輸入/輸出端子之一第一傳導元件於該凹洞中接合；在該金屬基板上形成一導線架(例如：向下設置(down set))，在該導線架上設一第二傳導元件，該第二傳導元件包含至少一第二輸入/輸出端子，其中該導線架包含複數個電性連接端用以連接該第一傳導元件之至少一第一輸入/輸出端子和該第二傳導元件之至少一第二輸入/輸出端子。由於基板為金屬材質，因此具有更佳的散熱以及電傳導。再者，因為金屬基板與導線架係直接結合，所以不需複雜的製程。
第一傳導元件主要封入在金屬基板中，而不是用塑性材料封膠；且藉由表面黏著技術(SMT)的技術，在金屬基板上放置一第 二傳導元件。前述第一傳導元件和第二傳導元件可以是主動元件，例如積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)或二極體等等，或是被動元件，例如電阻、電容或電感等等。第一傳導元件和第二傳導元件係與金屬基板(或接腳)直接電性連結，所以不需要額外的印刷電路板作為連結用。另外，利用點膠(dispensing)或塗膠(gluing)取代封膠用以保護第一傳導元件。因此，不需要額外的模具開發進而可以節省時間和成本，也較容易設計。因此和在傳統積體電路封裝結構中使用的導線架和封膠比較，本發明的結構可以製作元件間最短的電路路徑，故結構整體的阻抗降低且電性效率增加。
本發明之另一目的係提供一個封裝結構，其包含在金屬基板上形成一凹洞，使具有至少一第一輸入/輸出端子之一第一傳導元件於該凹洞中接合；在該金屬基板上形成一導線架(例如：向下設置(down set))，在該導線架上形成一第二凹洞，一第二傳導元件具有至少一第二輸入/輸出端子設於該第二凹洞；一第三傳導元件具有至少一第三輸入/輸出端子設於該導線架上，其中該導線架包含複數個第一電性連接端用以連接該第一傳導元件之至少一第一輸入/輸出端子和該第二傳導元件之至少一第二輸入/輸出端子；其中該金屬基板包含複數個第二電性連接端用以連接該第三傳導元件之至少一第三輸入/輸出端子。
本發明的一個較佳實施為另一種電性連結結構，係將前述的製造方法實現在金屬基板的上下表面。
本發明另一目的係提供一封裝結構之製造方法：提供一金屬基板，在該金屬基板形成一凹洞；在該凹洞中設置一傳導元件，該傳導元件具有至少一輸入/輸出端子；在該金屬基板上形成一導線架，其中該導線架包含複數個電性連接端用以連接該傳導元件之至少一輸入/輸出端。
本發明另一具體實施係提供一封裝結構之製造方法：提供一金屬基板，在該金屬基板形成一凹洞；在該凹洞中設置一第一傳導元件，該傳導元件具有至少一第一輸入/輸出端子；在該金屬基板上形成一第二傳導元件，該傳導元件具有至少一第二輸入/輸出端子；形成一導線架覆蓋於該第二傳導元件，其中該導線架包含複數個第一電性連接端用以連接該第一傳導元件之至少一第一輸入/輸出端子，且該金屬基板包含複數個第二電性連接端用以連接該第二傳導元件之至少一第二輸入/輸出端子。
在參閱圖式及接下來的段落所描述之實施方式之後，該技術領域具有通常知識者便可瞭解本發明之其它目的，以及本發明之技術手段及實施態樣。
本發明的詳細說明於隨後描述，這裡所描述的較佳實施例是作為說明和描述的用途，並非用來限定本發明之範圍。
本發明揭露一種由金屬基板和導線架結合組成之封裝結構。第1A圖為此封裝結構10之剖面示意圖。此結構10包含一金屬基板11、一導線架12、一填充層13、一絕緣層14以及一第一傳導元件15。
金屬基板11具有複數個接腳(未示之)可做為輸入/輸出端子，在接腳的下方放置有複數個墊片(pad)22用以外部電性連結。該金屬基板11可以是具有至少一個空隙19的金屬架，該金屬架係由移除金屬基板11一個或多個部分而形成。該金屬基板11也可以是導線架或是任何其他相等的結構。該金屬基板11可由銅、銀或錫至少其中一個組成。在一個具體實施中，該金屬基板11可以無空隙存在或是具有至少一個空隙19。該空隙19可填入任何適合的填充層13，例如塗膠層(gluing layer)。金屬基板11的外觀和形狀係依墊片22的佈局(layout)而定，且金屬基板11的接腳經由墊片22電性連結至印刷電路板或另一個傳導元件(未示之)，例如積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、扼流線圈(choke)或電容 等。
在該金屬基板11上形成一凹洞16，並利用一般技術(例如：銀膠)將傳導元件15(例如：積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、扼流線圈(choke)或電容)結合於凹洞16中。前述之凹洞16係以不同的形式實現，例如，在一個具體實施中，該凹洞16係形成於該金屬基板11內部，在另一個具體實施中，該凹洞16係具有一邊和金屬基板11的一邊對齊，在更另一個具體實施中，該凹洞16係具有兩邊和金屬基板11的兩邊對齊。在一具體實施中，前述金屬基板11係為複數個次金屬基板結合構成，然後在該金屬基板11上形成該凹洞16。在一具體實施中，至少一個第一傳導元件15結合於凹洞16中。在一具體實施中，該第一傳導元件15之輸入/輸出端子係藉由已知的技術，例如打線、金球結合、導線(藉由薄膜製程、印刷製程或電鍍)或其結合，電性連接該導線架12。在一個具體實施中，該第一傳導元件15的上表面17和金屬基板11的上表面18係位於同一水平面。
於金屬基板11之上形成一導線架12(例如：向下設置(down set))。該導線架12包含複數個電性連接端用以連接該第一傳導元件15之複數個接腳和輸入/輸出端子。在一個具體實施中，為了得到較佳的電性連接，在金屬基板11上會設置至少一導線架 12。該導線架12具有至少一空隙(未示之)。絕緣層14係形成於導線架12之上，且填充該導線架12之空隙。在一個具體實施中，該填充層13與絕緣層14可為同一層。
第1B圖為第1A圖之結構10上具有一第二傳導元件23之一產品結構20示意圖。與結構10相比，該產品結構20進一步包含一第二傳導元件23。藉由已知技術例如薄膜製程、印刷製程或其結合，在導線架12上形成複數個第一墊片21，然後在該第一墊片21上放置該第二傳導元件23(例如：積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、扼流線圈(choke)或電容)。在一個具體實施中，為了得到較佳的電性連接，可在第一墊片21和導線架12之間設置至少一傳導層(未示之)。金屬基板11下方可設置複數個第二墊片22(或接腳)用以外部電性連接。該第二墊片22可由任何導電的材料組成，例如錫、鎳/金合金或其類似物等。該結構20可放置於印刷電路板或與另一傳導元件(未示之)(例如：積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、扼流線圈(choke)或電容)電性連接，如此該第二傳導元件23可經由包含該第一墊片21、該導線架12、該金屬基板11(或接腳)和該第二墊片22等傳導路徑，與該印刷電路板或另一傳導元件電性連接。值得說明的是，電性連接方式並不僅侷限於前述方式，其係根據不同種類的產品和金屬基板的製程而有不同 的電性連接變化。電性連接方式包含很多方法，但不侷限於上面所述，而習知技術者易了解該電性連接方式，在此不進一步描述。
在一個具體實施中，如第1C圖所示，設置一第三傳導元件24於該導線架12之空隙。該第三傳導元件藉由一薄絕緣層25與該導線架12隔離。於另一個具體實施如第1D圖所示，該些導線架12可置於該金屬基板11之上表面41及下表面42。
第2A-2F圖為製造第1B圖之封裝結構20流程剖面示意圖。
如第2A圖所示，一金屬基板111具有至少一空隙119，且至少一凹洞116形成於該金屬基板111。如第2B圖所示，在凹洞116中設置一具有至少一第一輸入/輸出端子(未示之)之第一傳導元件115。然後於凹洞116的剩餘部分填充任何適合之材料。如第2C圖所示，填充一填充層113於該金屬基板111之空隙119，例如一塗膠層。如第2D圖所示，在金屬基板111上形成一導線架112(例如：向下設置(down set))。該導線架112可電性連結該第一傳導元件115的輸入/輸出端子和一部分該金屬基板111。該導線架112具有至少一空隙151。如第2E圖所示，絕緣層114係形成於導線架112之上，且填充該導線架112之空隙151。該絕緣層114可完整保護該導線架112。該絕緣層114之高度超過該導線架112之高度，如此可在該絕緣層114之上進行後 續製程，例如薄膜製程或印刷製程。在一具體實施中，形成第2D圖中之導線架112和形成一絕緣層114的次序係任意的。在一具體實施中，該填充層113和該絕緣層114可以是相同的或者在同一製程步驟中一併形成。接著，如第2F圖所示，該絕緣層114可形成開孔(未示之)用以放置複數個第一墊片121，且在該第一墊片121設置至少一第二傳導元件123。複數個第二墊片122放置於該金屬基板111(或接腳)之下，用以達成上面所述的外部電性連接。該第二傳導元件123可經由包含該第一墊片121、該導線架112、該金屬基板111(或接腳)和該第二墊片122等傳導路徑，與該印刷電路板或另一傳導元件電性(未示之)連接。
第3A-3F圖為製造第1C圖之另一封裝結構30流程剖面示意圖。
如第3A圖所示，一金屬基板211具有至少一空隙219，且至少一凹洞216形成於該金屬基板211。如第3B圖所示，在凹洞216中設置一具有至少一第一輸入/輸出端子(未示之)之第一傳導元件215。然後，於凹洞216的剩餘部分填充任何適合之材料。如第3C圖所示，填充一填充層213於該金屬基板211之空隙219，例如一塗膠層。如第3D圖所示，在金屬基板211上設置一第二傳導元件224。如第3E圖所示，為了隔離該第二傳導元件224與導線架212，沈積一薄絕緣層225覆蓋該第二傳導元件 224，此將於後續描述。為了改善電性，該第二傳導元件224係與該金屬基板211電性連接。該第二傳導元件224可以是主動元件或是被動元件，例如金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)二極體、電阻、扼流線圈(choke)或電容等等。在一個較佳實施中，該第二傳導元件224係為一電阻。然後，在該薄絕緣層225形成開孔226以曝露該第一傳導元件215之輸入/輸出端子和一部分之金屬基板211。如第3F圖所示，形成一導線架212(例如：向下設置(down set))覆蓋於第二傳導元件224上，使得該導線架212可經由該開孔226電性連接該第一傳導元件215之輸入/輸出端子和一部分之金屬基板211。如第3G圖所示，形成一厚絕緣層214覆蓋該第二傳導元件224和一部分該薄絕緣層225。該絕緣層214可完整保護該導線架212。該絕緣層214之高度超過該導線架212之高度，如此可在該絕緣層214之上進行後續製程，例如薄膜製程或印刷製程。在一具體實施中，該填充層213和該絕緣層214可以是相同的或者在同一製程步驟中一併形成。接著，如第3H圖所示，該絕緣層214可形成開孔(未示之)用以放置複數個第一墊片221，且在該第一墊片221上設置一第三傳導元件223。複數個第二墊片222放置於該金屬基板211(或接腳)之下，用以外部電性連接。該第三傳導元件223可經由包含該第一墊片221、該導線架212、該金屬基板211(或接腳)和該第二墊片222等傳導路徑，與該印刷電路板或另一傳導元件電性連接。
從上述實施例描述而知本發明的結構和製造方法可以提供很多的優點，包含：
1.基板由金屬構成且其有較佳的散熱和電傳導的特性。
2.不需使用嵌入式樹脂，不需開發額外的模具，節省時間和成本。
3.因為金屬基板與導線架係直接結合，製程簡單。
4.與一般導線架和積體電路封裝結構相比，由於本發明之結構可以最短電性路徑連接各組成元件，所以能降低總阻抗和增進電性效率，因此有較佳的電性表現。
雖然本發明以前述之較佳實施例揭露如上，然其並非用以限定本發明，任何熟習相像技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。
10,20‧‧‧封裝結構
11,111,211‧‧‧金屬基板
12,112,212‧‧‧導線架
13,113,213‧‧‧填充層
14,114,214‧‧‧絕緣層
15,115,215‧‧‧第一傳導元件
16,116,216‧‧‧凹洞
17,41‧‧‧金屬基板上表面
18,42‧‧‧金屬基板下表面
19,119,151,219‧‧‧空隙
21,121,221‧‧‧第一墊片
22,122,222‧‧‧第二墊片
23,123,224‧‧‧第二傳導元件
24,223‧‧‧第三傳導元件
25,225‧‧‧薄絕緣層
226‧‧‧開孔
第1A圖為此封裝結構之剖面示意圖；第1B圖為第1A圖之結構上具有一傳導元件之一產品結構示意圖；第1C圖為第1A圖之結構上具有一傳導元件之另一產品結 構示意圖；第1D圖為另一封裝結構之剖面示意圖第2A-2F圖為製造第1B圖之封裝結構流程剖面示意圖；第3A-3H圖為製造第1C圖之另一封裝結構流程剖面示意圖。
10‧‧‧封裝結構
11‧‧‧金屬基板
12‧‧‧導線架
13‧‧‧填充層
14‧‧‧絕緣層
15‧‧‧第一傳導元件
16‧‧‧凹洞
17‧‧‧金屬基板上表面
18‧‧‧金屬基板下表面
19‧‧‧空隙
21‧‧‧第一墊片
22‧‧‧第二墊片

Claims (20)

  1. 一種封裝結構，包含：一金屬基板；一凹洞，係形成在該金屬基板上；一第一傳導元件，係設在該凹洞內，且具有至少一第一輸入/輸出端；以及一第一導線架，係設在該金屬基板上，其中該第一導線架包含複數個第一電性連接端用以連接該第一傳導元件之該至少一第一輸入/輸出端。
  2. 如申請專利範圍第1項所述之封裝結構，其中該金屬基板具有複數個接腳。
  3. 如申請專利範圍第1項所述之封裝結構，進一步包含：一空隙，係形成在該第一導線架中；一第二傳導元件，係設在該空隙中，且具有至少一第二輸入/輸出端，其中該金屬基板包含複數個第二電性連接端用以連接該第二傳導元件之該至少一第二輸入/輸出端。
  4. 如申請專利範圍第3項所述之封裝結構，其中該第二傳導元 件係為一電阻。
  5. 如申請專利範圍第1項所述之封裝結構，進一步包含一第二導線架，其中該第一導線架與第二導線架係設於該金屬基板的相對面。
  6. 如申請專利範圍第1項所述之封裝結構，其中該金屬基板具有至少一第一空隙，且一第一填充層填入該至少一第一空隙。
  7. 如申請專利範圍第6項所述之封裝結構，其中該第一導線架具有至少一第二空隙，且一第二填充層填入該至少一第二空隙。
  8. 如申請專利範圍第7項所述之封裝結構，其中該第二填充層為一絕緣層。
  9. 如申請專利範圍第7項所述之封裝結構，其中該第一填充層與第二填充層係由單一層形成。
  10. 如申請專利範圍第1項所述之封裝結構，進一步包含：一第二傳導元件置於該第一導線架上，該第二傳導元件具有至少一第二輸入/輸出端，其中該第一導線架進一步包含複數 個第二電性連接端用以連接該第二傳導元件之該至少一第二輸入/輸出端。
  11. 如申請專利範圍第1項所述之封裝結構，其中該金屬基板係由銅、銀或錫其中至少一個所組成。
  12. 如申請專利範圍第1項所述之封裝結構，其中該第一傳導元件包含積體電路晶片(IC chip)、金屬氧化層場效電晶體(MOSFET)、絕緣閘極雙極性電晶體(IGBT)、二極體、電感、電容或電阻其中至少一個。
  13. 如申請專利範圍第1項所述之封裝結構，其中該金屬基板係為複數個次金屬基板所組成。
  14. 如申請專利範圍第1項所述之封裝結構，其中該第一導線架係為複數個次導線架所組成。
  15. 如申請專利範圍第1項所述之封裝結構，進一步包含一傳導層設在該第一導線架上。
  16. 一種封裝結構之製造方法，該方法包含了下列步驟：a.提供一金屬基板； b.在該金屬基板上形成一凹洞；c.在該凹洞中設置一第一傳導元件，該第一傳導元件具有至少一第一輸入/輸出端子；以及d.在該金屬基板上形成一導線架，其中該導線架包含複數個電性連接端用以連接該第一傳導元件之該至少一第一輸入/輸出端。
  17. 如申請專利範圍第16項所述之方法，其中該金屬基板具有複數個接腳。
  18. 如申請專利範圍第16項所述之方法，其中該導線架包含一空隙，且步驟d進一步包含在該空隙中設置一第二傳導元件。
  19. 如申請專利範圍第18項所述之方法，其中該第二傳導元件係為一電阻。
  20. 如申請專利範圍第16項所述之方法，其中該導線架包含一空隙，該方法進一步包含下列步驟：e.在該導線架上形成一絕緣層填入該空隙。
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