TWI533419B - 封裝結構及其製造方法 - Google Patents
封裝結構及其製造方法 Download PDFInfo
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- TWI533419B TWI533419B TW102128404A TW102128404A TWI533419B TW I533419 B TWI533419 B TW I533419B TW 102128404 A TW102128404 A TW 102128404A TW 102128404 A TW102128404 A TW 102128404A TW I533419 B TWI533419 B TW I533419B
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- Prior art keywords
- substrate
- electronic component
- conductive
- metal material
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- 238000000034 method Methods 0.000 title claims description 51
- 239000000758 substrate Substances 0.000 claims description 135
- 125000006850 spacer group Chemical group 0.000 claims description 67
- 239000007769 metal material Substances 0.000 claims description 64
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- 229910052751 metal Inorganic materials 0.000 claims description 16
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 claims description 5
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000012466 permeate Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
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- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
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- QDOXWKRWXJOMAK-UHFFFAOYSA-N dichromium trioxide Chemical compound O=[Cr]O[Cr]=O QDOXWKRWXJOMAK-UHFFFAOYSA-N 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- Semiconductor Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【0001】本發明係有關一種封裝結構,特別指一種封裝結構,其具有配置在基板貫穿開口( through-opening)中的一導電元件。
【0002】導線架(lead frame)是一種被應用在積體電路(IC)封裝的材料,其具有不同的型式,例如四邊接腳扁平式封裝(QFP)、薄小外型封裝(TSOP)、小外型晶體管(SOT)或J型接腳小外型封裝(SOJ)。藉由組裝和互相連結一半導體元件至一導線架來構成封膠(molding)的半導體元件,此結構常常使用塑性材料封膠。一導線架由金屬帶狀物(metal ribbon)構成,且具有一槳狀物(paddle)(亦為已知的晶粒槳狀物(die paddle)、晶粒附加標籤(die-attach tab)或島狀物(island)),一半導體元件設置在該槳狀物上。前述導線架具有不與該槳狀物重疊排列的複數個導線(lead)。【0003】傳統上,積體電路晶片係使用晶粒結合(die bond)的方式設置在導線架上。前述晶粒結合的製造程序包含很多步驟 : 打線(wirebond)、積體電路晶片封膠、切單後測試等等。藉由整合或封裝導線架和其他元件,例如電感或電容,可以製造不同的產品。因為製程容易、成熟且信賴性良好,為目前最主要製程之一。然而,這種傳統製程有很多的缺點,其包含: a. 製程成本高,且須使用模具來完成封膠,因此增加模具開發的成本; b. 設計面積只能平面而缺乏設計彈性,產品無法縮小;c. 只能封裝成單顆元件,並不具模組化的能力;d.散熱表現不佳且低良率。因此,本發明提出了一個封裝結構及其製程方法來克服上述之缺點。
【0004】本發明之一目的係提供一個封裝結構,其具有配置在第一基板貫穿開口(through-opening)中的至少一部分的第一導電元件。封裝結構包含:一第一基板,包含在其內的一貫穿開口;一第一導電元件,具有至少一第一輸入/輸出端,其中至少一部分的該第一導電元件配置在該第一基板的該貫穿開口中;以及一導電結構,配置在該第一基板和該第一導電元件上方,其中該導電結構電性連接至該第一基板和該第一導電元件的該至少一第一輸入/輸出端。該導電結構包含一第二導電元件、一第二基板或一導電圖案其中至少一個。【0005】在一個實施例中,作為導電電路的導電圖案可形成於第一基板的上表面或第一基板的下表面。基於電性絕緣考量,一介電材料(例如一絕緣材料或一導電材料和一非導電材料的組合)可配置於第一導電元件周圍和第一基板表面。【0006】在一個實施例中,焊球(ball bonding)(較佳來說為一錫球)可形成第一基板下方以作為外部電性連接之用(例如設置於印刷電路板(PCB)或電性連接至另一導電元件)。在一個實施例中,一散熱材料可配置在第一導電元件底部,以使第一導電元件具有較佳的散熱途徑。【0007】此外,利用點膠(dispensing)或塗膠(gluing)取代封膠用以保護第一導電元件。因此,不需要額外的模具開發,進而可以節省時間和成本,也較容易設計。因此和在傳統積體電路封裝結構中使用的導線架和封膠比較,本發明的結構可以製作元件間最短的電路路徑,以使結構的整體阻抗降低且電性效率增加。【0008】本發明之一目的係提供一用於形成一封裝結構的方法,該方法包含了下列步驟:提供一第一基板;在該第一基板中形成一貫穿開口;在該第一基板的該貫穿開口中配置至少一部分的一第一導電元件,其中該第一導電元件具有至少一第一輸入/輸出端;在該第一基板和該第一導電元件上方形成一導電結構,其中該導電結構電性連接至該第一基板和該第一導電元件的該至少一第一輸入/輸出端。【0009】本發明之一目的係提供一種連接結構,用以連接具有一接點的一導電元件。連接結構包含:一墊片,配置在該導電元件的該接點上;以及一第一金屬材料,滲透(permeate)至該墊片且到達該墊片和該導電元件的該接點之間的界面,其中該第一金屬材料電性連接至該導電元件的該接點且封住(encapsulate)至少一部分的該墊片。在一個實施例中,一金屬氧化物存在於墊片和導電元件接點之間的界面,其中該第一金屬材料封住(encapsulate)至少一部分的該金屬氧化物。【0010】 第一金屬材料具有較大附著於墊片的表面積用以增加導電元件和墊片上其他金屬層之間的附著力,藉以大大地降低墊片和導電元件接點之間的界面之接觸電阻。配置在墊片上的第一金屬材料為球狀、橢圖狀、淚滴狀或不規則形狀。【0011】第一金屬材料藉由一打線(wire bond)製程形成在墊片上,用以將第一金屬材料附著於墊片,其中該打線製程結束時不形成一導線。第一金屬材料藉由任何適合的製程形成在墊片上,例如雷射、高壓等方式。【0012】在參閱圖式及接下來的段落所描述之實施方式之後,該技術領域具有通常知識者便可瞭解本發明之其它目的,以及本發明之技術手段及實施態樣。
【0014】本發明的詳細說明於隨後描述,這裡所描述的較佳實施例是作為說明和描述的用途,並非用來限定本發明之範圍。【0015】本發明揭露一種封裝結構,其具有配置在基板貫穿開口(through-opening)中的至少一部分導電元件。封裝結構包含:一第一基板,包含在其內的一貫穿開口;一第一導電元件,具有至少一第一輸入/輸出端,其中至少一部分的該第一導電元件配置在該第一基板的該貫穿開口中;以及一導電結構,配置在該第一基板和該第一導電元件上方,其中該導電結構電性連接至該第一基板和該第一導電元件的該至少一第一輸入/輸出端。【0016】導電結構包含一第二導電元件、一第二基板或一導電圖案其中至少一個。導電結構可為一第二導電元件、一第二基板或一導電圖案的組合。第二導電元件可為積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、電感、扼流線圈(choke)或電容。第二基板可為一印刷電路板(PCB)、一陶瓷基板、一金屬基板或一導線架。導電圖案可由任何適合的製程形成,例如薄膜製程或印刷製程。【0017】實施例一 【0018】在本發明的第一個較佳實施例中,導電結構為一導電圖案。選擇性地,導電結構可為一導電圖案和一第二導電元件的組合。較佳來說,導電圖案可由任何適合的製程形成,例如薄膜製程或印刷製程。【0019】第1A圖為本發明結構10之剖面示意圖。結構10包含第一基板11、一貫穿開口(through-opening)12、一導電圖案13、一絕緣層14以及一第一導電元件15。【0020】第一基板11具有在其內的一導電圖案(未圖示)和可作為外部電性連接的複數個墊片(作為輸入/輸出端)(未圖示)。在一個實施例中,墊片可配置在結構10中任何適合的位置。墊片可配置在第一基板11下方或導電圖案13上方,用以製成最佳的封裝結構。第一基板11可為一印刷電路板(PCB)、一陶瓷基板、一金屬基板、一導線架等。在一個實施例中,第一基板11(例如金屬基板、導線架)具有至少一空隙(vacancy)(未圖示)。空隙可被任何適合的填充層(未圖示)填滿,例如一絕緣層。第一基板11和導電圖案13的外觀和形狀係依墊片的佈局(layout)而定,且結構10經由該墊片電性連結至印刷電路板(PCB)或另一個導電元件(未圖示),例如積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、扼流線圈(choke)或電容等等。在一個實施例中,第一基板11包含複數個次第一基板,其中該複數個次第一基板一起結合。【0021】第一基板11具有在其內的至少一貫穿開口12。貫穿開口12的形成可藉由移除一個或多個部分的第一基板11。在一個實施例中,作為導電電路的導電圖案13可形成於第一基板11的上表面(如第1A圖所示)或第一基板11的下表面(未圖示)。基於電性絕緣考量,一介電材料(例如一絕緣材料或一導電材料和一非導電材料的組合)可配置於第一導電元件15周圍和第一基板11表面(見第1A圖至第1D圖)。至少一部分的第一導電元件15(例如積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、電感、扼流線圈(choke)或電容等)配置在貫穿開口12中。至少一部分的第一導電元件15可電性連接至第一基板11上表面的導電圖案13或第一基板11下表面的導電圖案13。在一個實施例中,一散熱材料可配置在第一導電元件15底部,以使第一導電元件15具有較佳的散熱途徑。【0022】貫穿開口12係以不同的方式實現: 在一個實施例中,貫穿開口12係形成於第一基板11內部;在另一個實施例中,貫穿開口12具有一邊和第一基板11的一邊對齊;在更另一個實施例中,貫穿開口12具有兩邊和第一基板11的兩邊對齊。在一個實施例中,貫穿開口12可形成在包含複數個次第一基板的第一基板11中,其中該複數個次第一基板一起結合。【0023】在一個實施例中,第一基板11具有在其內的至少一貫穿開口12和至少一凹洞(未圖示)。凹洞的形成係藉由移除一個或多個部分的第一基板11。至少一部分的第二導電元件(未圖示)位於凹洞中。凹洞係以不同的方式實現: 在一個實施例中,凹洞係形成於第一基板11內部;在另一個實施例中,凹洞具有一邊和第一基板11的一邊對齊;在更另一個實施例中,凹洞具有兩邊和第一基板11的兩邊對齊。在一個實施例中,凹洞可形成在包含複數個次第一基板的第一基板11上,其中該複數個次第一基板一起結合。【0024一】導電圖案13配置在第一基板11和第一導電元件15上方。導電圖案13電性連接至第一基板11和第一導電元件15的至少一第一輸入/輸出端。第一導電元件15和第一基板11之間可具有直接的電性連接,也可具有非直接的電性連接。在一個實施例中(如第1A圖所示),藉由在第一導電元件15和第一基板11之間填充一絕緣層14,以使第一導電元件15和第一基板11電性絕緣。在一個實施例中,第一導電元件15經由導電圖案13電性連接至第一基板11。【0025】第1B圖為第1A圖之結構10上具有至少一第二導電元件18之一產品結構20示意圖。與第1A圖的結構10相比,產品結構20進一步包含在導電圖案13上的至少一第二導電元件18。複數個第一墊片21形成在導電圖案13上方,以及第二導電元件18 (例如:積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、電感、扼流線圈(choke)或電容等)可配置在第一墊片21上。一第一封膠(encapsulation)材料22可覆蓋導電圖案13。第一墊片21可由任何導電的材料製成,例如錫、鎳/金合金或其類似物。在一個實施例中,第一封膠(encapsulation)材料22和絕緣層14可由相同的材料製成。【0026】第1C圖為第1A圖之結構10上具有至少一第二導電元件18之另一產品結構30示意圖,其中複數個第二墊片16配置於第一基板11下方,用以作為外部電性連接。第二墊片16可由任何導電的材料製成,例如錫、鎳/金合金或其類似物。結構30可設置於印刷電路板(PCB)或電性連接至另一導電元件(未圖示) (例如:積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、電感、扼流線圈(choke)或電容等),以使第二導電元件18可經由包含第一墊片21、導電圖案13、第一基板11和第二墊片16的導電路徑電性連接至印刷電路板(PCB)或另一導電元件(未圖示)。值得說明的是,電性連接方式隨不同種類的產品和製程而變化。電性連接包含很多方式,但不侷限於上面所述。習知技術者易了解該電性連接方式,在此不進一步描述。【0027】第1D圖為第1A圖之結構10上具有至少一第二導電元件18之更另一產品結構40示意圖。與第1C圖的結構30相比,一導電層23配置於第一基板11下方(例如電鍍),以及一第二封膠材料24 (例如焊料遮罩(soldermask))覆蓋導電層23。一焊球(ball bonding) 25可形成在導電層23上以作為外部電性連接之用。較佳來說,焊球25為一錫球。結構40可設置於印刷電路板(PCB)或電性連接至另一導電元件(未圖示) (例如:積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、電感、扼流線圈(choke)或電容等),以使第二導電元件18可經由包含第一墊片21、導電圖案13、第一基板11、導電層23和焊球25的導電路徑電性連接至印刷電路板(PCB)或另一導電元件(未圖示)。值得說明的是,電性連接方式隨不同種類的產品和製程而變化。電性連接包含很多方式,但不侷限於上面所述。習知技術者易了解該電性連接方式,在此不進一步描述。【0028】第1E圖為另一結構50之剖面示意圖。與第1A圖的結構10相比,結構50包含一墊片51和一第一金屬材料52,其中該墊片51配置在第一導電元件15接點上,以及該第一金屬材料52滲透(permeate)至該墊片51且到達該墊片51和該第一導電元件15接點之間的界面,其中該第一金屬材料52電性連接至第一導電元件15的接點且封住(encapsulate)至少一部分的該墊片51。因此,墊片51和第一導電元件15接點之間的接觸電阻可大大地降低。【0029】實施例二【0030】在本發明的第二個較佳實施例中,導電結構為一第二基板。選擇性地,導電結構可為一第二基板和一第二導電元件的組合。【0031】第2A圖至第2D圖為結構110、120、130、140之剖面示意圖。結構110包含一第一基板111、一貫穿開口(through-opening)112、一第二基板113、一絕緣層114以及一第一導電元件115。與第1A圖的結構10相比,導電圖案13由第二基板113取代,其中第二基板113具有在其內的導電圖案113A。【0032】第二基板113係配置在第一基板111上 (例如:向下設置(down set))。第二基板113包含一導電圖案113A,用以電性連接第一基板111和第一導電元件115的至少一輸入/輸出端。前述在第1A圖至第1D圖的特徵可適用於結構110、120、130、140。【0033】在一個實施例中,第二基板113包含一金屬板,其中該金屬板電耦合至結構110、120、130、140的複數個輸入/輸出墊片之其中一個且和結構110、120、130、140內的複數個導電元件之任何一個絕緣,用以降低來外部電磁波對該複數個導電元件造成之干涉。【0034】第二基板113可為一印刷電路板(PCB)、一陶瓷基板、一金屬基板或一導線架等。在一個實施例中,第二基板113(例如金屬基板或導線架)具有至少一空隙(未圖示)。第一基板111和第二基板113的外觀和形狀係依墊片的佈局(layout)而定,結構110、120、130、140經由該墊片電性連結至印刷電路板(PCB)或另一個導電元件(未圖示),例如積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、電感、扼流線圈(choke)或電容等。【0035】由於導電圖案113A已在早期預定階段圖案化於第二基板113上,因此不需要直接在第一基板111上使用複雜的製程(例如薄膜製程(film process)、黃光製程(lithographyprocess)或印刷製程)以形成一導電圖案,其中該導電圖案113A電性連接至第一導電元件115的至少一輸入/輸出端、第二導電元件118 的至少一輸入/輸出端或第一基板111。因此可以節省額外的圖案化製程成本。【0036】第2E圖為具有至少一第三導電元件122之另一產品結構150示意圖。與第2B圖的結構120相比,至少一第三導電元件122配置於第二基板113的空隙(或凹洞)126中。第三導電元件122可為一電阻。前述在特徵也可適用於第2E圖的結構150。【0037】在根據本發明結構160的一個實施例中,如第2F圖所示,第一基板111可配置在第二基板113的上表面和下表面。每一個第一基板111具有至少一貫穿開口112,導電元件115配置在該貫穿開口112中。【0038】在根據本發明結構170的另一個實施例中,如第2G圖所示,第二基板113可配置在第一基板111的上表面和下表面。【0039】第3圖為製造第1A圖至第1D圖或第2A圖至第2D圖的結構之流程示意圖。【0040】在步驟301中,提供一第一基板11、111。第一基板11、111可為一印刷電路板(PCB)、一陶瓷基板、一金屬基板、一導線架等。【0041】在步驟302中,在第一基板11、111中形成一貫穿開口12、112。貫穿開口12、112可由已知的製程形成。貫穿開口12、112係以不同的方式實現: 在一個實施例中,貫穿開口12、112係形成於第一基板11、111內部;在另一個實施例中,貫穿開口12、112具有一邊和第一基板11、111的一邊對齊;在更另一個實施例中,貫穿開口12、112具有兩邊和第一基板11、111的兩邊對齊。【0042】在步驟303中,在第一基板11、111的貫穿開口 12、112中配置至少一部分的第一導電元件15、115,其中該第一導電元件15、115具有至少一第一輸入/輸出端。第一導電元件15、115可為積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、電感、扼流線圈(choke)或電容。【0043】在步驟304中,在第一基板11、111和第一導電元件15、115上方形成一導電結構13、113,其中該導電結構13、113電性連接至該第一基板11、111和該第一導電元件15、115的至少一第一輸入/輸出端。在一個實施例中(見第1A圖至第1D圖),導電結構13、113可為由已知製程(例如薄膜製程(filmprocess)、印刷製程或其結合)形成的一導電圖案13。一第一封膠材料22可覆蓋導電圖案13。【0044】在步驟305中,在導電結構13、113上配置一第二導電元件18、118,其中該第二導電元件18、118具有至少一第二輸入/輸出端,以及該導電結構13、113電性連接至該第二導電元件18、118的該至少一第二輸入/輸出端。第二導電元件18、118可為積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、電感、扼流線圈(choke)或電容。在導電結構13、113上配置第二導電元件18、118之前,一第一墊片21、121可形成在導電結構13、113上方。一第二墊片16、116可配置在第一基板11、111下方,用以作為外部電性連接至印刷電路板(PCB)或另一個導電元件。外部電性連接的結構可由已知的製程形成,其已描述在第1C圖和第1D圖。【0045】傳統上,打線(wire bond)作為積體電路晶片(IC chip)的輸入/輸出端(例如鋁墊)和導線架或任何其他導電圖案上對應接點之間的電性連接。打線製程所使用的導線材料包含金或鋁。此外,一金屬層可直接形成在積體電路晶片表面用以達成上述的電性連接。因為製程容易、成熟且信賴度良好,打線製程成為目前工業界主要製程之一。然而,打線製程仍有很多的缺點,其包含: a. 由於表面的品質較差,接點間的材料將會退化; b. 由於表面的品質較差,接點阻抗將會增加。【0046】請參閱第4A圖;一金屬氧化物505存在於一墊片502和一導電元件501接點(terminal)之間的界面。墊片502(由鋁、鉻等製成)易於遭受氧化。舉例來說,假如墊片502由鋁製成,氧化鋁(A12O3)形成在墊片502和導電元件501接點之間的界面504。氧化鋁(A12O3)的厚度約為2000埃。選擇性地,金屬氧化物505可藉由任何適合的製程移除,例如化學清洗(chemical clean)或超音波震盪(ultrasonic vibration)。如果金屬氧化物505為氧化鋁(A12O3)或氧化鉻(Cr2O3),化學清洗的移除能力較超音波震盪弱。在墊片502上形成一貫穿孔(未圖示)之後,移除貫穿孔底部的金屬氧化物更為困難,因此衍生出污染的問題。此外,氧化物會增加導電材料和墊片之間的接點阻抗; 以及由於殘餘應力施加於導電材料和墊片之間的界面,可能會破壞導電材料和墊片之間的電性連接。【0047】本發明也揭露一種連接結構,用以連接具有一接點的一導電元件以解決上述的問題。第4B圖為具有一導電元件501、一墊片502和一第一金屬材料503之結構500剖面示意圖。導電元件501具有在其上的一墊片502,以及第一金屬材料滲透(permeate)至該墊片502且到達墊片502和導電元件501接點之間的界面504。第一金屬材料503電性連接至導電元件501的接點且封住(encapsulate)至少一部分的墊片502。在一個實施例中,請參閱第4C圖,一金屬氧化物505存在於墊片502和導電元件501接點之間的界面,其中該第一金屬材料503封住(encapsulate)至少一部分的該金屬氧化物505。因此,在墊片502和導電元件501接點之間的接點阻抗可大大地降低。【0048】第一金屬材料503可為任何適合的材料(例如金、銀、銅、錫或其結合)以降低接點阻抗。配置在墊片502上的第一金屬材料503可具有任何適合的形狀,以使第一金屬材料503具有較大的表面積以緊緊地附著於墊片502。配置在墊片502上的第一金屬材料為球狀、橢圖狀、淚滴狀或不規則形狀。因此,導電元件501和第二金屬材料之間的附著力大大地增加。【0049】導電元件501可為積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、電感、扼流線圈(choke)或電容等。結構500可使用在任何複雜的結構,舉例來說,如第1E圖所示,一墊片51配置在第一導電元件15的接點上,以及第一金屬材料52滲透(permeate)至該墊片51且到達該墊片52和該第一導電元件15接點之間的界面,其中該第一金屬材料52電性連接至該第一導電元件15的接點且封住(encapsulate)至少一部分的該墊片51。較佳來說,墊片502為一鋁墊片,以及導電元件501為一裸晶片。【0050】在一個實施例中(見第4D圖),用以連接具有一接點的一導電元件501之連接結構500可延伸至用以電性連接一第二金屬材料513。一絕緣材料511配置在導電元件501上,其中該絕緣材料511具有在其內的一貫穿孔511A,以及墊片502配置在貫穿孔511A底部。絕緣材料511可包含環氧樹脂(epoxy)、氧化物、高分子材料或磁性材料其中至少一個。貫穿孔511A的直徑長約為40~300微米。較佳來說,絕緣材料511可為一光阻。第二金屬材料513配置在絕緣材料511上方且填充於貫穿孔511A中。第二金屬材料513可為任何適合的材料,例如銅、銀或其結合。在一個實施例中,在形成第二金屬材料513之前,一薄金屬材料512可保形地(conformally)沉積在該絕緣材料511上、貫穿孔511A的側壁和底部。薄金屬材料512可為任何適合的材料,較佳來說,薄金屬材料512為金。【0051】第5圖為製造在第4B圖至第4D圖中用以連接具有一接點的一導電元件501之連接結構500流程剖面示意圖,以進一步解決上述的問題,例如源自於第4A圖中的熱膨脹或不穩定結構。【0052】在步驟551中,在導電元件501的接點上配置一墊片502。較佳來說,墊片502為一鋁墊片,以及導電元件501為一裸晶片。【0053】在步驟552中,形成一第一金屬材料503,其中該第一金屬材料503滲透(permeate)至該墊片502且到達該墊片502和該導電元件501接點之間的界面504,其中該第一金屬材料503電性連接至該導電元件501的接點且封住(encapsulate)至少一部分的該墊片502。較佳來說,第一金屬材料503藉由一打線(wire bond)製程形成在墊片502上,用以將第一金屬材料503附著於墊片502,其中該打線製程結束時不形成一導線。第一金屬材料503藉由任何適合的製程形成在墊片502上,例如雷射、高壓等方式。【0054】在步驟553中,在導電元件501上形成一絕緣材料511,其中該絕緣材料511具有在其內的一貫穿孔511A,以及該墊片502配置在該貫穿孔511A底部。【0055】在步驟554中,在絕緣材料511上形成一第二金屬材料513且延伸該第二金屬材料513至該貫穿孔511A中。第二金屬材料513藉由已知的製程形成,例如電鍍。在一個實施例中,在形成第二金屬材料513之前,一薄金屬材料512藉由已知的製程(例如電鍍)可保形地(conformally)沉積在絕緣材料511上、貫穿孔511A的側壁和底部。【0056】雖然本發明以前述之較佳實施例揭露如上,然其並非用以限定本發明,任何熟習相像技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。
10,20,30,40,50,110,120,130,140,150,160,170...結構
11,111...第一基板
12,112...貫穿開口(through-opening)
13,113A...導電圖案
14,114...絕緣層
15,115...第一導電元件
16,116...第二墊片
18,118...第二導電元件
21,121...第一墊片
22...第一封膠材料
23,123...導電層
24,124...第二封膠材料
25,125...焊球
51...墊片
52...第一金屬材料
113...第二基板
122...第三導電元件
126...空隙
301,302,303,304,305,551,552,553,554...步驟
501...接點
502...墊片
503...第一金屬材料
504...界面
505...金屬氧化物
511...絕緣材料
511A...貫穿孔
512...薄金屬材料
513...第二金屬材
【0013】第1A圖為本發明結構之剖面示意圖;第1B圖為第1A圖之結構上具有至少一第二導電元件之一產品結構示意圖;第1C圖為第1A圖之結構上具有至少一第二導電元件之另一產品結構示意圖,其中複數個第二墊片配置於第一基板下方,用以作為外部電性連接;第1D圖為第1A圖之結構上具有至少一第二導電元件之更另一產品結構示意圖;第1E圖為另一結構之剖面示意圖,其中該結構包含一墊片和一第一金屬材料,其中該墊片配置在第一導電元件接點上,以及該第一金屬材料滲透(permeate)至該墊片且到達該墊片和該第一導電元件接點之間的界面;第2A圖至第2D圖為具有一第二基板之結構剖面示意圖,其中第1A圖中的導電圖案由第二基板取代;第2E圖為具有至少一第三導電元件之另一產品結構示意圖,其中至少一第三導電元件配置於第二基板的空隙中;第2F圖為本發明之結構剖面示意圖,其中第一基板可配置在第二基板的上表面和下表面;第2G圖為本發明之結構剖面示意圖,其中第二基板可配置在第一基板的上表面和下表面;第3圖為製造第1A圖至第1 D圖或第2A圖至第2D圖的結構之流程示意圖;第4A圖為結構剖面示意圖,其說明金屬氧化物存在於墊片和導電元件接點之間的界面;第4B圖為本發明之結構剖面示意圖;第4C圖為本發明之結構剖面示意圖,其說明金屬氧化物存在於墊片和導電元件接點之間的界面,其中第一金屬材料封住(encapsulate)至少一部分的該金屬氧化物;第4D圖為本發明之結構剖面示意圖,其說明該結構延伸至用以電性連接一第二金屬材料;第5圖為製造在第4B圖至第4D圖中用以連接具有一接點的一導電元件之連接結構流程剖面示意圖。
10...結構
11...第一基板
12...貫穿開口(through-opening)
13...導電圖案
14...絕緣層
15...第一導電元件
Claims (21)
- 一種封裝結構,包含:一第一基板,包含在其內的一貫穿開口;一第一電子元件,具有至少一第一輸入/輸出端,配置在該第一電子元件的一上表面上,其中至少一部分的該第一電子元件配置在該第一基板的該貫穿開口中,其中一絕緣層配置在該上表面上並填入該貫穿開口中之該第一電子元件與該第一基板間的空間,該至少一第一輸入/輸出端通過該絕緣層而露出;以及一導電結構,配置在該第一基板和該第一電子元件上方,其中該導電結構電性連接至該第一基板和該第一電子元件的該至少一第一輸入/輸出端。
- 如申請專利範圍第1項所述之封裝結構,其中該導電結構包含一第二電子元件、一第二基板或一導電圖案其中至少一個。
- 如申請專利範圍第1項所述之封裝結構,其中該導電結構為一第二電子元件。
- 如申請專利範圍第1項所述之封裝結構,其中該導電結構為一第二基板。
- 如申請專利範圍第1項所述之封裝結構,其中該導電結構為一導電圖案。
- 如申請專利範圍第1項所述之封裝結構,進一步包含配置在該第一基板下方的複數個墊片。
- 如申請專利範圍第1項所述之封裝結構,進一步包含配置在該導電結構上方的複數個墊片。
- 如申請專利範圍第1項所述之封裝結構,其中該第一基板為一印刷電路板、一陶瓷基板、一金屬基板或一導線架。
- 如申請專利範圍第1項所述之封裝結構,其中該第一基板進一步包含在其內的一凹洞,進一步包含具有至少一第二輸入/輸出端的一第二電子元件,其中至少一部分的該第二電子元件配置在該第一基板的該凹洞中,其中該導電結構電性連接該第二電子元件的該至少一第二輸入/輸出端。
- 如申請專利範圍第1項所述之封裝結構,進一步包含配置在該第一電子元件底部的一散熱材料。
- 如申請專利範圍第4項所述之封裝結構,其中該第二基板為一金屬基板。
- 如申請專利範圍第4項所述之封裝結構,進一步包含:一配置在該第二基板內的空隙;以及一第二電子元件,具有至少一第二輸入/輸出端,其中該第二電子元件配置在該第二基板內的該空隙中,其中在該第二基板電性連接至該第二電子元件的該至少一第二輸入/輸出端。
- 一種連接結構,用以連接具有一接點的一電子元件,包含:一墊片,配置在該電子元件的該接點上;以及一第一金屬材料,滲透至該墊片和該電子元件的該接點之間的界面且跨於該界面之至少一部份,其中該第一金屬材料電性連接至該電子元件的該接點且封住至少一部分的該墊片。
- 如申請專利範圍第13項所述之連接結構,進一步包含一金屬氧化物,在該墊片和該電子元件的該接點之間的界面,其中該第一金屬材料封住至少一部分的該金屬氧化物。
- 如申請專利範圍第13項所述之連接結構,其中該第一金屬材料為球狀、橢圖狀、淚滴狀或不規則形狀。
- 如申請專利範圍第13項所述之連接結構,進一步包含:一絕緣材料,配置在該電子元件上,其中該絕緣材料具有在其內的一貫穿孔,以及該墊片配置在該貫穿孔底部;以及一第二金屬材料,配置在該絕緣材料上且延伸至該貫穿孔。
- 如申請專利範圍第13項所述之連接結構,其中該墊片由鋁製成,以及該電子元件為一裸晶片。
- 一種形成一連接結構的方法,用以連接具有一接點的一電子元件,該方法包含了下列步驟:a.在該電子元件的該接點上配置一墊片;以及b.形成一第一金屬材料,以使該第一金屬材料滲透至該墊片和該電子元件的該接點之間的界面且跨於該界面之至少一部份,其中該第一金屬材料電性連接至該電子元件的該接點且封住至少一部分的該墊片。
- 如申請專利範圍第18項所述之方法,其中步驟b中形成一第一金屬材料以使該第一金屬材料滲透至該墊片之方式係藉由一打線製程以將該第一金屬材料附著於該墊片,其中該打線製程結束時不形成一導線。
- 如申請專利範圍第18項所述之連接結構,進一步包含下列步驟:c.在該電子元件上形成一絕緣材料,其中該絕緣材料具有在其內的一貫穿孔,以及該墊片配置在該貫穿孔底部;以及d.在該絕緣材料上形成一第二金屬材料且延伸該第二金屬材料至該貫穿孔中。
- 一種形成一連接結構的方法,用以連接具有一接點的一電子元件,該方法包含了下列步驟:a.在該電子元件的該接點上配置一墊片;以及b.形成一第一金屬材料,以使該第一金屬材料滲透至該墊片且到達該墊片和該導電元件的該接點之間的界面,其中該第一金屬材料滲透至該墊片之方式係藉由一 打線製程以將該第一金屬材料附著於該墊片,其中該打線製程結束時不形成一導線,其中該第一金屬材料電性連接至該導電元件的該接點且封住至少一部分的該墊片。
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