CN103579029A - 封装结构及其制造方法 - Google Patents
封装结构及其制造方法 Download PDFInfo
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- CN103579029A CN103579029A CN201310344356.2A CN201310344356A CN103579029A CN 103579029 A CN103579029 A CN 103579029A CN 201310344356 A CN201310344356 A CN 201310344356A CN 103579029 A CN103579029 A CN 103579029A
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Abstract
本发明公开一种封装结构及其制造方法,该封装结构具有至少一部分的第一导电元件配置在第一基板的贯穿开口(through-opening)中。一导电结构配置在第一基板和第一导电元件上方,其中该导电结构电性连接至该第一基板和该第一导电元件的该至少一第一输入/输出端。导电结构包含一第二导电元件、一第二基板或一导电图案其中至少一个。
Description
技术领域
本发明是有关一种封装结构,特别指一种封装结构,其具有配置在基板贯穿开口(through-opening)中的一导电元件。
背景技术
导线架(lead frame)是一种被应用在集成电路(IC)封装的材料,其具有不同的型式,例如四边接脚扁平式封装(QFP)、薄小外型封装(TSOP)、小外型晶体管(SOT)或J型接脚小外型封装(SOJ)。通过组装和互相连结一半导体元件至一导线架来构成封胶(molding)的半导体元件,此结构常常使用塑性材料封胶。一导线架由金属带状物(metal ribbon)构成,且具有一桨状物(paddle)(亦为已知的晶粒桨状物(die paddle)、晶粒附加标签(die-attach tab)或岛状物(island)),一半导体元件设置在该桨状物上。前述导线架具有不与该桨状物重迭排列的多个导线(lead)。
传统上,集成电路芯片是使用晶粒结合(die bond)的方式设置在导线架上。前述晶粒结合的制造程序包含很多步骤:打线(wire bond)、集成电路芯片封胶、切单后测试等等。通过整合或封装导线架和其他元件,例如电感或电容,可以制造不同的产品。因为制程容易、成熟且信赖性良好,为目前最主要制程之一。然而,这种传统制程有很多的缺点,其包含:a.制程成本高,且须使用模具来完成封胶,因此增加模具开发的成本;b.设计面积只能平面而缺乏设计弹性,产品无法缩小;c.只能封装成单颗元件,并不具模块化的能力;d.散热表现不佳且低良率。因此,本发明提出了一个封装结构及其制程方法来克服上述的缺点。
发明内容
本发明的一目的是提供一个封装结构,其具有配置在第一基板贯穿开口(through-opening)中的至少一部分的第一导电元件。封装结构包含:一第一基板,包含在其内的一贯穿开口;一第一导电元件,具有至少一第一输入/输出端,其中至少一部分的该第一导电元件配置在该第一基板的该贯穿开口中;以及一导电结构,配置在该第一基板和该第一导电元件上方,其中该导电结构电性连接至该第一基板和该第一导电元件的该至少一第一输入/输出端。该导电结构包含一第二导电元件、一第二基板或一导电图案其中至少一个。
在一个实施例中,作为导电电路的导电图案可形成于第一基板的上表面或第一基板的下表面。基于电性绝缘考量,一介电材料(例如一绝缘材料或一导电材料和一非导电材料的组合)可配置于第一导电元件周围和第一基板表面。
在一个实施例中,焊球(ball bonding)(较佳来说为一锡球)可形成第一基板下方以作为外部电性连接之用(例如设置于印刷电路板(PCB)或电性连接至另一导电元件)。在一个实施例中,一散热材料可配置在第一导电元件底部,以使第一导电元件具有较佳的散热途径。
此外,利用点胶(dispensing)或涂胶(gluing)取代封胶用以保护第一导电元件。因此,不需要额外的模具开发,进而可以节省时间和成本,也较容易设计。因此和在传统集成电路封装结构中使用的导线架和封胶比较,本发明的结构可以制作元件间最短的电路路径,以使结构的整体阻抗降低且电性效率增加。
本发明的一目的是提供一用于形成一封装结构的方法,该方法包含了下列步骤:提供一第一基板;在该第一基板中形成一贯穿开口;在该第一基板的该贯穿开口中配置至少一部分的一第一导电元件,其中该第一导电元件具有至少一第一输入/输出端;在该第一基板和该第一导电元件上方形成一导电结构,其中该导电结构电性连接至该第一基板和该第一导电元件的该至少一第一输入/输出端。
本发明的一目的是提供一种连接结构,用以连接具有一接点的一导电元件。连接结构包含:一垫片,配置在该导电元件的该接点上;以及一第一金属材料,渗透(permeate)至该垫片且到达该垫片和该导电元件的该接点之间的界面,其中该第一金属材料电性连接至该导电元件的该接点且封住(encapsulate)至少一部分的该垫片。在一个实施例中,一金属氧化物存在于垫片和导电元件接点之间的界面,其中该第一金属材料封住(encapsulate)至少一部分的该金属氧化物。
第一金属材料具有较大附着于垫片的表面积用以增加导电元件和垫片上其他金属层之间的附着力,藉以大大地降低垫片和导电元件接点之间的界面的接触电阻。配置在垫片上的第一金属材料为球状、椭图状、泪滴状或不规则形状。
第一金属材料通过一打线(wire bond)制程形成在垫片上,用以将第一金属材料附着于垫片,其中该打线制程结束时不形成一导线。第一金属材料通过任何适合的制程形成在垫片上,例如激光、高压等方式。
在参阅图式及接下来的段落所描述的实施方式的后,该技术领域具有通常知识者便可了解本发明的其它目的,以及本发明的技术手段及实施态样。
附图说明
图1A为本发明结构的剖面示意图;
图1B为图1A的结构上具有至少一第二导电元件的一产品结构示意图;
图1C为图1A的结构上具有至少一第二导电元件的另一产品结构示意图,其中多个第二垫片配置于第一基板下方,用以作为外部电性连接;
图1D为图1A的结构上具有至少一第二导电元件的更另一产品结构示意图;
图1E为另一结构的剖面示意图,其中该结构包含一垫片和一第一金属材料,其中该垫片配置在第一导电元件接点上,以及该第一金属材料渗透(permeate)至该垫片且到达该垫片和该第一导电元件接点之间的界面;
图2A至图2D为具有一第二基板的结构剖面示意图,其中第1A图中的导电图案由第二基板取代;
图2E为具有至少一第三导电元件的另一产品结构示意图,其中至少一第三导电元件配置于第二基板的空隙中;
图2F为本发明的结构剖面示意图,其中第一基板可配置在第二基板的上表面和下表面;
图2G为本发明的结构剖面示意图,其中第二基板可配置在第一基板的上表面和下表面;
图3为制造图1A至图1D或图2A至图2D的结构的流程示意图;
图4A为结构剖面示意图,其说明金属氧化物存在于垫片和导电元件接点之间的界面;
图4B为本发明的结构剖面示意图;
图4C为本发明的结构剖面示意图,其说明金属氧化物存在于垫片和导电元件接点之间的界面,其中第一金属材料封住(encapsulate)至少一部分的该金属氧化物;
图4D为本发明的结构剖面示意图,其说明该结构延伸至用以电性连接一第二金属材料;
图5为制造在图4B至图4D中用以连接具有一接点的一导电元件的连接结构流程剖面示意图。
附图标记说明:10,20,30,40,50,110,120,130,140,150,160,170结构;11,111-第一基板;12,112-贯穿开口(through-opening);13,113A-导电图案;14,114-绝缘层;15,115-第一导电元件;16,116-第二垫片;18,118-第二导电元件;21,121-第一垫片;22-第一封胶材料;23,123-导电层;24,124-第二封胶材料;25,125-焊球;51-垫片;52-第一金属材料;113-第二基板;122-第三导电元件;126-空隙;301,302,303,304,305,551,552,553,554-步骤;501-接点;502-垫片;503-第一金属材料;504-界面;505-金属氧化物;511-绝缘材料;511A-贯穿孔;512-薄金属材料;513-第二金属材料。
具体实施方式
本发明的详细说明于随后描述,这里所描述的较佳实施例是作为说明和描述的用途,并非用来限定本发明的范围。
本发明公开一种封装结构,其具有配置在基板贯穿开口(through-opening)中的至少一部分导电元件。封装结构包含:一第一基板,包含在其内的一贯穿开口;一第一导电元件,具有至少一第一输入/输出端,其中至少一部分的该第一导电元件配置在该第一基板的该贯穿开口中;以及一导电结构,配置在该第一基板和该第一导电元件上方,其中该导电结构电性连接至该第一基板和该第一导电元件的该至少一第一输入/输出端。
导电结构包含一第二导电元件、一第二基板或一导电图案其中至少一个。导电结构可为一第二导电元件、一第二基板或一导电图案的组合。第二导电元件可为集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、电感、扼流线圈(choke)或电容。第二基板可为一印刷电路板(PCB)、一陶瓷基板、一金属基板或一导线架。导电图案可由任何适合的制程形成,例如薄膜制程或印刷制程。
实施例一
在本发明的第一个较佳实施例中,导电结构为一导电图案。选择性地,导电结构可为一导电图案和一第二导电元件的组合。较佳来说,导电图案可由任何适合的制程形成,例如薄膜制程或印刷制程。
图1A为本发明结构10的剖面示意图。结构10包含第一基板11、一贯穿开口(through-opening)12、一导电图案13、一绝缘层14以及一第一导电元件15。
第一基板11具有在其内的一导电图案(未图示)和可作为外部电性连接的多个垫片(作为输入/输出端)(未图示)。在一个实施例中,垫片可配置在结构10中任何适合的位置。垫片可配置在第一基板11下方或导电图案13上方,用以制成最佳的封装结构。第一基板11可为一印刷电路板(PCB)、一陶瓷基板、一金属基板、一导线架等。在一个实施例中,第一基板11(例如金属基板、导线架)具有至少一空隙(vacancy)(未图示)。空隙可被任何适合的填充层(未图示)填满,例如一绝缘层。第一基板11和导电图案13的外观和形状系依垫片的布局(layout)而定,且结构10经由该垫片电性连结至印刷电路板(PCB)或另一个导电元件(未图示),例如集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、扼流线圈(choke)或电容等等。在一个实施例中,第一基板11包含多个次第一基板,其中该多个次第一基板一起结合。
第一基板11具有在其内的至少一贯穿开口12。贯穿开口12的形成可通过移除一个或多个部分的第一基板11。在一个实施例中,作为导电电路的导电图案13可形成于第一基板11的上表面(如图1A所示)或第一基板11的下表面(未图示)。基于电性绝缘考量,一介电材料(例如一绝缘材料或一导电材料和一非导电材料的组合)可配置于第一导电元件15周围和第一基板11表面(见图1A至图1D)。至少一部分的第一导电元件15(例如集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、电感、扼流线圈(choke)或电容等)配置在贯穿开口12中。至少一部分的第一导电元件15可电性连接至第一基板11上表面的导电图案13或第一基板11下表面的导电图案13。在一个实施例中,一散热材料可配置在第一导电元件15底部,以使第一导电元件15具有较佳的散热途径。
贯穿开口12是以不同的方式实现:在一个实施例中,贯穿开口12是形成于第一基板11内部;在另一个实施例中,贯穿开口12具有一边和第一基板11的一边对齐;在更另一个实施例中,贯穿开口12具有两边和第一基板11的两边对齐。在一个实施例中,贯穿开口12可形成在包含多个次第一基板的第一基板11中,其中该多个次第一基板一起结合。
在一个实施例中,第一基板11具有在其内的至少一贯穿开口12和至少一凹洞(未图示)。凹洞的形成是通过移除一个或多个部分的第一基板11。至少一部分的第二导电元件(未图示)位于凹洞中。凹洞是以不同的方式实现:在一个实施例中,凹洞是形成于第一基板11内部;在另一个实施例中,凹洞具有一边和第一基板11的一边对齐;在更另一个实施例中,凹洞具有两边和第一基板11的两边对齐。在一个实施例中,凹洞可形成在包含多个次第一基板的第一基板11上,其中该多个次第一基板一起结合。
一导电图案13配置在第一基板11和第一导电元件15上方。导电图案13电性连接至第一基板11和第一导电元件15的至少一第一输入/输出端。第一导电元件15和第一基板11之间可具有直接的电性连接,也可具有非直接的电性连接。在一个实施例中(如图1A所示),通过在第一导电元件15和第一基板11之间填充一绝缘层14,以使第一导电元件15和第一基板11电性绝缘。在一个实施例中,第一导电元件15经由导电图案13电性连接至第一基板11。
图1B为图1A的结构10上具有至少一第二导电元件18的一产品结构20示意图。与图1A的结构10相比,产品结构20进一步包含在导电图案13上的至少一第二导电元件18。多个第一垫片21形成在导电图案13上方,以及第二导电元件18(例如:集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、电感、扼流线圈(choke)或电容等)可配置在第一垫片21上。一第一封胶(encapsulation)材料22可覆盖导电图案13。第一垫片21可由任何导电的材料制成,例如锡、镍/金合金或其类似物。在一个实施例中,第一封胶(encapsulation)材料22和绝缘层14可由相同的材料制成。
图1C为图1A的结构10上具有至少一第二导电元件18的另一产品结构30示意图,其中多个第二垫片16配置于第一基板11下方,用以作为外部电性连接。第二垫片16可由任何导电的材料制成,例如锡、镍/金合金或其类似物。结构30可设置于印刷电路板(PCB)或电性连接至另一导电元件(未图示)(例如:集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、电感、扼流线圈(choke)或电容等),以使第二导电元件18可经由包含第一垫片21、导电图案13、第一基板11和第二垫片16的导电路径电性连接至印刷电路板(PCB)或另一导电元件(未图示)。值得说明的是,电性连接方式随不同种类的产品和制程而变化。电性连接包含很多方式,但不局限于上面所述。现有技术者易了解该电性连接方式,在此不进一步描述。
图1D为图1A的结构10上具有至少一第二导电元件18的更另一产品结构40示意图。与图1C的结构30相比,一导电层23配置于第一基板11下方(例如电镀),以及一第二封胶材料24(例如焊料遮罩(solder mask))覆盖导电层23。一焊球(ball bonding)25可形成在导电层23上以作为外部电性连接之用。较佳来说,焊球25为一锡球。结构40可设置于印刷电路板(PCB)或电性连接至另一导电元件(未图示)(例如:集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、电感、扼流线圈(choke)或电容等),以使第二导电元件18可经由包含第一垫片21、导电图案13、第一基板11、导电层23和焊球25的导电路径电性连接至印刷电路板(PCB)或另一导电元件(未图示)。值得说明的是,电性连接方式随不同种类的产品和制程而变化。电性连接包含很多方式,但不局限于上面所述。现有技术者易了解该电性连接方式,在此不进一步描述。
图1E为另一结构50的剖面示意图。与图1A的结构10相比,结构50包含一垫片51和一第一金属材料52,其中该垫片51配置在第一导电元件15接点上,以及该第一金属材料52渗透(permeate)至该垫片51且到达该垫片51和该第一导电元件15接点之间的界面,其中该第一金属材料52电性连接至第一导电元件15的接点且封住(encapsulate)至少一部分的该垫片51。因此,垫片51和第一导电元件15接点之间的接触电阻可大大地降低。
实施例二
在本发明的第二个较佳实施例中,导电结构为一第二基板。选择性地,导电结构可为一第二基板和一第二导电元件的组合。
图2A至图2D为结构110、120、130、140的剖面示意图。结构110包含一第一基板111、一贯穿开口(through-opening)112、一第二基板113、一绝缘层114以及一第一导电元件115。与图1A的结构10相比,导电图案13由第二基板113取代,其中第二基板113具有在其内的导电图案113A。
第二基板113配置在第一基板111上(例如:向下设置(down set))。第二基板113包含一导电图案113A,用以电性连接第一基板111和第一导电元件115的至少一输入/输出端。前述在图1A至图1D的特征可适用于结构110、120、130、140。
在一个实施例中,第二基板113包含一金属板,其中该金属板电耦合至结构110、120、130、140的多个输入/输出垫片的其中一个且和结构110、120、130、140内的多个导电元件的任何一个绝缘,用以降低来外部电磁波对该多个导电元件造成的干涉。
第二基板113可为一印刷电路板(PCB)、一陶瓷基板、一金属基板或一导线架等。在一个实施例中,第二基板113(例如金属基板或导线架)具有至少一空隙(未图示)。第一基板111和第二基板113的外观和形状是依垫片的布局(layout)而定,结构110、120、130、140经由该垫片电性连结至印刷电路板(PCB)或另一个导电元件(未图示),例如集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、电感、扼流线圈(choke)或电容等。
由于导电图案113A已在早期预定阶段图案化于第二基板113上,因此不需要直接在第一基板111上使用复杂的制程(例如薄膜制程(film process)、黄光制程(lithography process)或印刷制程)以形成一导电图案,其中该导电图案113A电性连接至第一导电元件115的至少一输入/输出端、第二导电元件118的至少一输入/输出端或第一基板111。因此可以节省额外的图案化制程成本。
图2E具有至少一第三导电元件122的另一产品结构150示意图。与图2B的结构120相比,至少一第三导电元件122配置于第二基板113的空隙(或凹洞)126中。第三导电元件122可为一电阻。前述在特征也可适用于第2E图的结构150。
在根据本发明结构160的一个实施例中,如图2F所示,第一基板111可配置在第二基板113的上表面和下表面。每一个第一基板111具有至少一贯穿开口112,导电元件115配置在该贯穿开口112中。
在根据本发明结构170的另一个实施例中,如图2G所示,第二基板113可配置在第一基板111的上表面和下表面。
图3为制造图1A至图1D或图2A至图2D的结构的流程示意图。
在步骤301中,提供一第一基板11、111。第一基板11、111可为一印刷电路板(PCB)、一陶瓷基板、一金属基板、一导线架等。
在步骤302中,在第一基板11、111中形成一贯穿开口12、112。
贯穿开口12、112可由已知的制程形成。贯穿开口12、112系以不同的方式实现:在一个实施例中,贯穿开口12、112是形成于第一基板11、111内部;在另一个实施例中,贯穿开口12、112具有一边和第一基板11、111的一边对齐;在更另一个实施例中,贯穿开口12、112具有两边和第一基板11、111的两边对齐。
在步骤303中,在第一基板11、111的贯穿开口12、112中配置至少一部分的第一导电元件15、115,其中该第一导电元件15、115具有至少一第一输入/输出端。第一导电元件15、115可为集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、电感、扼流线圈(choke)或电容。
在步骤304中,在第一基板11、111和第一导电元件15、115上方形成一导电结构13、113,其中该导电结构13、113电性连接至该第一基板11、111和该第一导电元件15、115的至少一第一输入/输出端。在一个实施例中(见图1A至图1D),导电结构13、113可为由已知制程(例如薄膜制程(film process)、印刷制程或其结合)形成的一导电图案13。一第一封胶材料22可覆盖导电图案13。
在步骤305中,在导电结构13、113上配置一第二导电元件18、118,其中该第二导电元件18、118具有至少一第二输入/输出端,以及该导电结构13、113电性连接至该第二导电元件18、118的该至少一第二输入/输出端。第二导电元件18、118可为集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、电感、扼流线圈(choke)或电容。在导电结构13、113上配置第二导电元件18、118之前,一第一垫片21、121可形成在导电结构13、113上方。一第二垫片16、116可配置在第一基板11、111下方,用以作为外部电性连接至印刷电路板(PCB)或另一个导电元件。外部电性连接的结构可由已知的制程形成,其已描述在第1C图和第1D图。
传统上,打线(wire bond)作为集成电路芯片(IC chip)的输入/输出端(例如铝垫)和导线架或任何其他导电图案上对应接点之间的电性连接。打线制程所使用的导线材料包含金或铝。此外,一金属层可直接形成在集成电路芯片表面用以达成上述的电性连接。因为制程容易、成熟且信赖度良好,打线制程成为目前工业界主要制程之一。然而,打线制程仍有很多的缺点,其包含:a.由于表面的品质较差,接点间的材料将会退化;b.由于表面的品质较差,接点阻抗将会增加。
请参阅图4A;一金属氧化物505存在于一垫片502和一导电元件501接点(terminal)之间的界面。垫片502(由铝、铬等制成)易于遭受氧化。举例来说,假如垫片502由铝制成,氧化铝(A12O3)形成在垫片502和导电元件501接点之间的界面504。氧化铝(A12O3)的厚度约为2000埃。选择性地,金属氧化物505可通过任何适合的制程移除,例如化学清洗(chemical clean)或超音波震荡(ultrasonic vibration)。如果金属氧化物505为氧化铝(A12O3)或氧化铬(Cr2O3),化学清洗的移除能力较超音波震荡弱。在垫片502上形成一贯穿孔(未图示)的后,移除贯穿孔底部的金属氧化物更为困难,因此衍生出污染的问题。此外,氧化物会增加导电材料和垫片之间的接点阻抗;以及由于残余应力施加于导电材料和垫片之间的界面,可能会破坏导电材料和垫片之间的电性连接。
本发明也公开一种连接结构,用以连接具有一接点的一导电元件以解决上述的问题。图4B为具有一导电元件501、一垫片502和一第一金属材料503的结构500剖面示意图。导电元件501具有在其上的一垫片502,以及第一金属材料渗透(permeate)至该垫片502且到达垫片502和导电元件501接点之间的界面504。第一金属材料503电性连接至导电元件501的接点且封住(encapsulate)至少一部分的垫片502。在一个实施例中,请参阅图4C,一金属氧化物505存在于垫片502和导电元件501接点之间的界面,其中该第一金属材料503封住(encapsulate)至少一部分的该金属氧化物505。因此,在垫片502和导电元件501接点之间的接点阻抗可大大地降低。
第一金属材料503可为任何适合的材料(例如金、银、铜、锡或其结合)以降低接点阻抗。配置在垫片502上的第一金属材料503可具有任何适合的形状,以使第一金属材料503具有较大的表面积以紧紧地附着于垫片502。配置在垫片502上的第一金属材料为球状、椭图状、泪滴状或不规则形状。因此,导电元件501和第二金属材料之间的附着力大大地增加。
导电元件501可为集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、电感、扼流线圈(choke)或电容等。结构500可使用在任何复杂的结构,举例来说,如图1E所示,一垫片51配置在第一导电元件15的接点上,以及第一金属材料52渗透(permeate)至该垫片51且到达该垫片52和该第一导电元件15接点之间的界面,其中该第一金属材料52电性连接至该第一导电元件15的接点且封住(encapsulate)至少一部分的该垫片51。较佳来说,垫片502为一铝垫片,以及导电元件501为一裸芯片。
在一个实施例中(见图4D),用以连接具有一接点的一导电元件501的连接结构500可延伸至用以电性连接一第二金属材料513。一绝缘材料511配置在导电元件501上,其中该绝缘材料511具有在其内的一贯穿孔511A,以及垫片502配置在贯穿孔511A底部。绝缘材料511可包含环氧树脂(epoxy)、氧化物、高分子材料或磁性材料其中至少一个。贯穿孔511A的直径长约为40~300微米。较佳来说,绝缘材料511可为一光阻。第二金属材料513配置在绝缘材料511上方且填充于贯穿孔511A中。第二金属材料513可为任何适合的材料,例如铜、银或其结合。在一个实施例中,在形成第二金属材料513之前,一薄金属材料512可保形地(conformally)沉积在该绝缘材料511上、贯穿孔511A的侧壁和底部。薄金属材料512可为任何适合的材料,较佳来说,薄金属材料512为金。
图5为制造在图4B至图4D中用以连接具有一接点的一导电元件501的连接结构500流程剖面示意图,以进一步解决上述的问题,例如源自于图4A中的热膨胀或不稳定结构。
在步骤551中,在导电元件501的接点上配置一垫片502。较佳来说,垫片502为一铝垫片,以及导电元件501为一裸芯片。
在步骤552中,形成一第一金属材料503,其中该第一金属材料503渗透(permeate)至该垫片502且到达该垫片502和该导电元件501接点之间的界面504,其中该第一金属材料503电性连接至该导电元件501的接点且封住(encapsulate)至少一部分的该垫片502。较佳来说,第一金属材料503通过一打线(wire bond)制程形成在垫片502上,用以将第一金属材料503附着于垫片502,其中该打线制程结束时不形成一导线。第一金属材料503通过任何适合的制程形成在垫片502上,例如激光、高压等方式。
在步骤553中,在导电元件501上形成一绝缘材料511,其中该绝缘材料511具有在其内的一贯穿孔511A,以及该垫片502配置在该贯穿孔511A底部。
在步骤554中,在绝缘材料511上形成一第二金属材料513且延伸该第二金属材料513至该贯穿孔511A中。第二金属材料513通过已知的制程形成,例如电镀。在一个实施例中,在形成第二金属材料513之前,一薄金属材料512通过已知的制程(例如电镀)可保形地(conformally)沉积在绝缘材料511上、贯穿孔511A的侧壁和底部。
虽然本发明以前述的较佳实施例公开如上,然其并非用以限定本发明,任何熟习相像技艺者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的专利保护范围须视本说明书所附的申请专利范围所界定者为准。
Claims (20)
1.一种封装结构,其特征在于,包含:一第一基板,包含在其内的一贯穿开口;一第一导电元件,具有至少一第一输入/输出端,其中至少一部分的该第一导电元件配置在该第一基板的该贯穿开口中;以及一导电结构,配置在该第一基板和该第一导电元件上方,其中该导电结构电性连接至该第一基板和该第一导电元件的该至少一第一输入/输出端。
2.根据权利要求1所述的封装结构,其特征在于,该导电结构包含一第二导电元件、一第二基板或一导电图案其中至少一个。
3.根据权利要求1所述的封装结构,其特征在于,该导电结构为一第二导电元件。
4.根据权利要求1所述的封装结构,其特征在于,该导电结构为一第二基板。
5.根据权利要求1所述的封装结构,其特征在于,该导电结构为一导电图案。
6.根据权利要求1所述的封装结构,其特征在于,进一步包含配置在该第一基板下方的多个垫片。
7.根据权利要求1所述的封装结构,其特征在于,进一步包含配置在该导电结构上方的多个垫片。
8.根据权利要求1所述的封装结构,其特征在于,该第一基板为一印刷电路板、一陶瓷基板、一金属基板或一导线架。
9.根据权利要求1所述的封装结构,其特征在于,该第一基板进一步包含在其内的一凹洞,进一步包含具有至少一第二输入/输出端的一第二导电元件,其中至少一部分的该第二导电元件配置在该第一基板的该凹洞中,其中该导电结构电性连接该第二导电元件的该至少一第二输入/输出端。
10.根据权利要求1所述的封装结构,其特征在于,进一步包含配置在该第一导电元件底部的一散热材料。
11.根据权利要求4所述的封装结构,其特征在于,该第二基板为一金属基板。
12.根据权利要求4所述的封装结构,其特征在于,进一步包含:一配置在该第二基板内的空隙;以及一第二导电元件,具有至少一第二输入/输出端,其中该第二导电元件配置在该第二基板内的该空隙中,其中在该第二基板电性连接至该第二导电元件的该至少一第二输入/输出端。
13.一种连接结构,其特征在于,用以连接具有一接点的一导电元件,包含:一垫片,配置在该导电元件的该接点上;以及一第一金属材料,渗透至该垫片且到达该垫片和该导电元件的该接点之间的界面,其中该第一金属材料电性连接至该导电元件的该接点且封住至少一部分的该垫片。
14.根据权利要求13所述的连接结构,其特征在于,进一步包含一金属氧化物,在该垫片和该导电元件的该接点之间的界面,其中该第一金属材料封住至少一部分的该金属氧化物。
15.根据权利要求13所述的连接结构,其特征在于,该第一金属材料为球状、椭图状、泪滴状或不规则形状。
16.根据权利要求13所述的连接结构,其特征在于,进一步包含:一绝缘材料,配置在该导电元件上,其中该绝缘材料具有在其内的一贯穿孔,以及该垫片配置在该贯穿孔底部;以及一第二金属材料,配置在该绝缘材料上且延伸至该贯穿孔。
17.根据权利要求13所述的连接结构,其特征在于,该垫片由铝制成,以及该导电元件为一裸芯片。
18.一种形成一连接结构的方法,其特征在于,用以连接具有一接点的一导电元件,该方法包含了下列步骤:a.在该导电元件的该接点上配置一垫片;以及b.形成一第一金属材料,以使该第一金属材料渗透至该垫片且到达该垫片和该导电元件的该接点之间的界面,其中该第一金属材料电性连接至该导电元件的该接点且封住至少一部分的该垫片。
19.根据权利要求18所述的形成一连接结构的方法,其特征在于,步骤b中形成一第一金属材料以使该第一金属材料渗透至该垫片的方式是通过一打线制程以将该第一金属材料附着于该垫片,其中该打线制程结束时不形成一导线。
20.根据权利要求18所述的形成一连接结构的方法,其特征在于,进一步包含下列步骤:c.在该导电元件上形成一绝缘材料,其中该绝缘材料具有在其内的一贯穿孔,以及该垫片配置在该贯穿孔底部;以及d.在该绝缘材料上形成一第二金属材料且延伸该第二金属材料至该贯穿孔中。
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CN103579029B (zh) | 2017-09-08 |
TW201407732A (zh) | 2014-02-16 |
CN107591372A (zh) | 2018-01-16 |
TW201620099A (zh) | 2016-06-01 |
US10373930B2 (en) | 2019-08-06 |
TWI631677B (zh) | 2018-08-01 |
TWI533419B (zh) | 2016-05-11 |
US20140042610A1 (en) | 2014-02-13 |
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