JPH0473297B2 - - Google Patents

Info

Publication number
JPH0473297B2
JPH0473297B2 JP58083187A JP8318783A JPH0473297B2 JP H0473297 B2 JPH0473297 B2 JP H0473297B2 JP 58083187 A JP58083187 A JP 58083187A JP 8318783 A JP8318783 A JP 8318783A JP H0473297 B2 JPH0473297 B2 JP H0473297B2
Authority
JP
Japan
Prior art keywords
semiconductor device
external electrode
package
mold layer
resin mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58083187A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59208755A (ja
Inventor
Katsuhiko Akyama
Juji Kajama
Tetsuo Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP58083187A priority Critical patent/JPS59208755A/ja
Publication of JPS59208755A publication Critical patent/JPS59208755A/ja
Publication of JPH0473297B2 publication Critical patent/JPH0473297B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP58083187A 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法 Granted JPS59208755A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58083187A JPS59208755A (ja) 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58083187A JPS59208755A (ja) 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法

Publications (2)

Publication Number Publication Date
JPS59208755A JPS59208755A (ja) 1984-11-27
JPH0473297B2 true JPH0473297B2 (zh) 1992-11-20

Family

ID=13795315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58083187A Granted JPS59208755A (ja) 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法

Country Status (1)

Country Link
JP (1) JPS59208755A (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131449U (zh) * 1986-02-13 1987-08-19
JPH0421320Y2 (zh) * 1986-02-14 1992-05-15
JPS63301531A (ja) * 1987-06-01 1988-12-08 Nec Corp 混成集積回路装置
JPH08148603A (ja) * 1994-11-22 1996-06-07 Nec Kyushu Ltd ボールグリッドアレイ型半導体装置およびその製造方法
US6329711B1 (en) 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
JP3129169B2 (ja) * 1995-11-08 2001-01-29 富士通株式会社 半導体装置及びその製造方法
US5977613A (en) * 1996-03-07 1999-11-02 Matsushita Electronics Corporation Electronic component, method for making the same, and lead frame and mold assembly for use therein
DE10063041B4 (de) 2000-12-18 2012-12-06 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Leadless-Gehäuse-Schaltung und integrierte Leadless-Gehäuse-Schaltung
JP4611569B2 (ja) * 2001-05-30 2011-01-12 ルネサスエレクトロニクス株式会社 リードフレーム及び半導体装置の製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921047A (ja) * 1982-07-27 1984-02-02 Fuji Xerox Co Ltd リ−ドレスチツプキヤリア

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921047A (ja) * 1982-07-27 1984-02-02 Fuji Xerox Co Ltd リ−ドレスチツプキヤリア

Also Published As

Publication number Publication date
JPS59208755A (ja) 1984-11-27

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