CN102244057B - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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Publication number
CN102244057B
CN102244057B CN201110212849.1A CN201110212849A CN102244057B CN 102244057 B CN102244057 B CN 102244057B CN 201110212849 A CN201110212849 A CN 201110212849A CN 102244057 B CN102244057 B CN 102244057B
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opening
conductive carrier
semiconductor packages
dielectric layer
chip
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CN102244057A (zh
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凯.史提芬.艾希格
伯恩.卡尔.阿培得
李明锦
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明公开一种半导体封装及其制造方法。该半导体封装包括导电载体、设置于邻近于所述导电载体的上表面的芯片、图案化导电层以及包封所述芯片的介电材料。所述介电材料定义出开口，所述图案化导电层穿过所述开口电连接到所述导电载体的所述上表面。所述导电载体具有侧表面，所述侧表面包括邻近于所述导电载体的所述上表面的第一部分和邻近于所述导电载体的下表面的第二部分，其中所述第二部分相对于所述导电载体的所述下表面而向内倾斜。

Description

半导体封装及其制造方法
技术领域
本发明涉及半导体装置封装(semiconductor device package)及其制造方法。更特定来说，本发明涉及具有嵌入式芯片(embedded die)的半导体装置封装及其制造方法。
背景技术
在由较小尺寸的需求和增强处理速度的需求中的至少一部分地驱动下，半导体装置已变得越来越复杂。同时，存在使包括这些半导体装置的许多电子产品进一步微型化的需求。半导体装置通常经封装，且随后可被安装在包括电路的基底(例如，电路板)上。半导体装置也可安装在金属层上，以获得增强的热传导性(thermal dissipation)。这导致空间被半导体装置封装和基底及/或金属层所占据，且导致基底及/或金属层上的表面区域被半导体装置封装所占据。另外，以单独的工艺来执行封装、板制造和组装可能导致额外的成本。减少基底及/或金属层上由半导体装置所占据的空间以及简化和组合应用于半导体装置和基底及/或金属层的封装、板制造和组装工艺将会是令人满意的。
针对此背景技术，需要开发本文所描述的半导体封装和相关方法。
发明内容
本发明的一个方面涉及一种半导体封装。在实施例中，所述半导体封装包括：(1)导电载体，其具有上表面、下表面和侧表面，所述侧表面包括邻近于导电载体的上表面的第一部分和邻近于导电载体的下表面的第二部分，其中第二倾斜部分相对于导电载体的下表面而向内倾斜；(2)芯片，设置于邻近于导电载体的上表面；(3)图案化导电层；以及(4)介电材料，其包封芯片，其中所述介电材料定义出开口，图案化导电层穿过所述开口电连接到导电载体的上表面。
在另一实施例中，所述半导体封装包括：(1)导电载体，其具有上表面、下表面和侧表面，所述侧表面包括邻近于导电载体的上表面的第一部分、邻近于导电载体的下表面的第二部分以及位于第一部分与第二部分之间的接面处的顶点；(2)芯片，设置于邻近于导电载体的上表面；以及(3)介电材料，其具有实质上垂直的侧表面且实质上包封第一部分。第二部分具有相对于所述实质上垂直的侧表面的角偏移。
本发明的另一方面涉及一种形成半导体封装的方法。在实施例中，所述方法包括：(1)提供具有上表面和下表面的金属层；(2)形成从金属层的上表面延伸且部分地穿过金属层的第一开口；(3)将芯片设置于邻近于金属层的上表面；(4)用具有背对芯片的上表面的介电层包封芯片和金属层的上表面的至少一部分，所述介电层实质上填入第一开口；(5)在介电层中形成第二开口，所述第二开口暴露出金属层的上表面；(6)邻近于介电层的上表面而形成图案化导电层；(7)形成延伸穿过第二开口的导电孔(conductivevia)，所述导电孔将图案化导电层电连接到金属层；以及(8)形成从金属层的下表面延伸且部分地穿过金属层的第三开口，第三开口与第一开口实质上对准。
本发明的其它方面和实施例也同样被预期。上述概要和以下详细描述无意将本发明限于任一特定实施例，而是仅用于描述本发明的一些实施例。
附图说明本发明的实施例，且连同描述内容一起用以阐释本发明一些实施例的原理。现在将详细参考本发明的一些实施例，其实例在附图中得以说明。只要可能，便在附图和描述内容中使用相同参考标号来表示相同或相似特征。
附图说明
图1说明根据本发明实施例的半导体封装的剖面图。
图2说明根据本发明实施例的半导体封装的剖面图。
图3说明根据本发明实施例的半导体封装的剖面图。
图4说明根据本发明实施例的半导体封装的剖面图。
图5说明根据本发明实施例的半导体封装的剖面图。
图6A到图6P说明根据本发明实施例的制造半导体封装的方法。
附图标记说明
100、200、300、401、500：半导体封装
102：芯片                     103：有源表面
104：背面                     105：导电载体
106、124、402：上表面         107：高度
108、126、406：下表面         109：深度
110、111、128：侧表面         112：凹槽
113：厚度                     114、403：壁
115：凹槽底部                 116：芯片贴附层
120、410、413、414：介电层
121、123、132、150、152、412：开口
122：纤维                     130：图案化导电层
133、134：接触区              135、136、137：表面处理层
140：介电层                   142、144：导电孔
154：顶点                     160：侧壁
164：下半部分                 166：上半部分
170：第一平面                 172：下半部
174：上半部                   400：基体基底带
404：导电片                   420、430：虚线
具体实施方式
首先参见图1，其说明根据本发明实施例的半导体封装100的剖面图。半导体封装100可包括有源组件(例如，芯片102)、无源组件或有源和无源组件两者。在图1中，半导体封装100包括芯片102、导电载体(conductivebase)105、介电层(dielectric layer)120和图案化导电层(patterned conductivelayer)130。芯片102具有有源表面103、与有源表面103相对的背面104以及侧表面(lateral surface)111。导电载体105具有上表面106、与上表面106相对的下表面108以及侧表面110。在实施例中，芯片102的背面104设置于邻近于导电载体105的上表面106。介电层120具有上表面124、下表面126以及从上表面124延伸到下表面126的侧表面128。介电层120实质上包封导电载体105的上表面106以及芯片102的侧表面111和有源表面103，以提供机械稳定性以及对氧化、潮湿和其它环境条件的防护。图案化导电层130设置于邻近于介电层120的上表面124。介电层120位于图案化导电层130与芯片102的有源表面103之间，且位于图案化导电层130与导电载体105的上表面106之间。
导电载体105可由金属及/或金属合金(例如铜及/或铜合金)形成。导电载体105可为铜箔(copper foil)，且可称为引线框(1eadframe)。在实施例中，导电载体105的厚度113可在约100μm到约300μm的范围内，例如约200μm到约300μm的范围内。在实施例中，导电载体105的厚度113近似为250μm。
在实施例中，导电载体105定义出具有壁114的凹槽112。芯片102可至少部分地设置于凹槽112中，使得芯片102的背面104邻近于凹槽112的凹槽底部115。凹槽底部115可包括于导电载体105的上表面106中。介电层120可实质上填入凹槽的位于芯片102与壁114之间的部分。在实施例中，芯片102的高度107不大于凹槽112的深度109。凹槽112的深度109可等于或大于芯片102的高度107。或者，凹槽112的深度109可小于芯片102的高度107。在实施例中，凹槽112的深度109可在芯片102的高度107的约50％到芯片102的高度107的约100％的范围内，例如高度107的约60％到约80％的范围内、高度107的约80％到约100％的范围内和高度107的约90％到约100％的范围内。芯片102至少部分地放置于凹槽112中可允许介电层120的厚度减小，且因此允许封装100的厚度减小。另外，在实施例中，如果芯片102的高度107小于或近似等于凹槽112的深度109，那么介电层120无需预先形成以产生对应于芯片102的开口(见图6D)。或者，如果凹槽112的深度109小于芯片102的高度107，那么可能需要在介电层120中预先形成开口，但由于凹槽112的缘故，此开口可小于图6C中所示的开口。
凹槽112的壁114可倾斜。在实施例中，壁114可弯曲。凹槽112的壁114可倾斜以使得凹槽底部115处的壁114比凹槽底部115上方的壁114更靠近芯片102。
芯片102可通过芯片贴附层(die attach layer)116贴附到导电载体105。在实施例中，芯片贴附层116可由金属及/或金属合金形成，以促进从芯片102到导电载体105的热传导。在此实施例中，形成芯片贴附层116的过程可称为共晶接合(eutectic bonding)。这对于热传导性尤其重要的半导体封装(例如嵌入式芯片电力封装等)来说可为令人满意的。芯片贴附层116可由例如锡与铅的合金等软焊料(soft solder)形成。或者，芯片贴附层116可由例如金与锡的合金等硬焊料形成。由硬焊料形成芯片贴附层116可为令人满意的，因为这可使得芯片贴附层116具有较均匀的厚度和较好的热传导性能。在其它实施例中，芯片102可通过例如环氧树脂(epoxy)等芯片贴附膜贴附到导电载体105。
在实施例中，介电层120可由聚合或非聚合的介电材料形成。举例来说，介电层120可由(但不限于)液晶聚合物(liquid crystal polymer，LCP)、双马来酰亚胺三嗪(bismaleimide triazine，BT)、预浸渍体(prepreg，PP)、味的素堆积膜(Ajinomoto Build-up Film，ABF)、环氧树脂以及聚酰亚胺(polyimide)中的至少一者形成。对于某些实施方案，介电层120可由可光成像(photoimageable)或感光(photoactive)的介电材料形成。另外，介电层120可为以例如玻璃纤维或Kevlar纤维(芳族聚酸胺纤维)等纤维122加强以强化介电层120的树脂材料。在介电层120中使用的可由纤维加强的树脂材料的实例包括ABF、BT、预浸渍体、聚酰亚胺、LCP、环氧树脂和其它树脂材料。如以下在图6B和图6D所示，纤维290最初在介电层614内沿着大体水平的平面定向，之后进行层压以形成介电层214。如图2所示，纤维122在介电层120的层压之后重定向，其中邻近于芯片102的部分被沿着芯片102的垂直延伸方向推动，且远离导电载体105。
如图1中所说明，介电层120经形成而定义出开口121和123。开口121可从图案化导电层130延伸到导电载体105的上表面106，且可暴露出上表面106。图案化导电层130可穿过开口121电连接到导电载体105。开口123可暴露出芯片102的有源表面103的若干部分。开口121和123可具有若干形状中的任一者。这些形状包括柱体形状，例如圆形柱体形状、椭圆形柱体形状、正方形柱体形状或矩形柱体形状，或包括非柱体形状，例如圆锥形、漏斗形或另一锥形形状。这些开口的侧向边界可弯曲或带粗糙纹理也同样被预期。
如图1中所说明，导电孔(conductive via)142可设置于每一开口121中，且导电孔144可设置于每一开口123中。举例来说，导电孔142和144可为经电镀导电柱(plated conductive post)。或者，导电孔142可实质上填入开口121，且/或导电孔144可实质上填入开口123。虽然图1中绘示一个导电孔142，但预期封装100可含有一个以上导电孔142。导电孔142可从图案化导电层130延伸到导电载体105。导电孔142可将图案化导电层130中所包括的接触区(contact)133电连接到导电载体105。在实施例中，接触区133可为用于导电载体105的接地接触区。导电孔144可从图案化导电层130延伸到芯片102。导电孔144可将接触区134电连接到芯片102的有源表面103。在实施例中，接触区134可包括用于芯片102的电力、信号及/或接地接触区。
在实施例中，图1所示的图案化导电层和导电孔中的每一者可由金属、金属合金、其中散布有金属或金属合金的基质(matrix)或另一合适的导电材料形成。举例来说，图1所示的图案化导电层和导电孔中的每一者可由铝、铜、钛或其组合所形成。图1所示的图案化导电层和导电孔可由相同的导电材料或不同的导电材料所形成。
如图1中所说明，由图案化导电层130定义出的开口132可实质上由介电层140填入。介电层140可由例如干式膜可成像焊罩(solder mask)等焊罩(焊料光致抗蚀剂)或另一类型的可图案化层或介电层形成。开口132以及介电层140中暴露出电接触区133和134的开口可具有若干形状中的任一者。这些形状包括柱体形状，例如圆形柱体形状、椭圆形柱体形状、正方形柱体形状或矩形柱体形状，或包括非柱体形状，例如圆锥形、漏斗形或另一锥形形状。这些开口的侧向边界可弯曲或带粗糙纹理也同样被预期。
如图1中所说明，接触区133和134可分别电镀有表面处理层(surfacefinish layer)135和136。在实施例中，表面处理层135和136可采用类似于图1所示的形成图案化导电层和导电孔的方式而形成，如先前所述。或者，表面处理层135和136可采用不同方式形成。举例来说，表面处理层135和136可由锡、镍和金或包括锡或包括镍与金的合金中的至少一者形成。表面处理层135和136可由相同的导电材料或不同的导电材料形成。
图2说明根据本发明实施例的半导体封装200的剖面图。半导体封装200在许多方面类似于参见图1而描述的半导体封装100，因此在此处论述半导体封装200的不同的观点。在此实施例中，芯片102可设置于邻近于导电基座105的上表面106，而不设置于凹槽中。特定来说，凹槽112(见图1)不形成于导电基座105中。因为芯片102设置于邻近于导电基座105的上表面106，而不设置于凹槽中，所以介电层120经预先形成以产生对应于芯片102的开口(见图6B)。
参见图1，在实施例中，导电基座105定义出开口150和152。开口150和152也可称为凹槽150和152及/或凹口150和152。开口150和152各自部分地延伸穿过导电基座105，其中开口150从导电基座105的上表面106延伸，且开口152从导电基座105的下表面108延伸。每一开口150可与开口152中的对应一者相对定位。在实施例中，开口150可实质上由介电层120填入。每一开口152可暴露出介电层120。或者，在实施例中，每一开口150可通过导电基座105的一部分(未图示)与开口152中的对应一者分离。
如图1中所说明，侧表面110可包括下半部分164和上半部分166。下半部分164可倾斜，且可在导电基座105的下表面108与上半部分166之间延伸。在实施例中，下半部分164可相对于下表面108而向内倾斜。侧表面110的上半部分166可在导电基座105的上表面106与下半部分164之间延伸。下半部分164对应于开口152的边界。侧表面110的上半部分166也可倾斜，且可实质上由介电层120覆盖。在实施例中，侧表面110可包括位于下半部分164与上半部分166之间的接面处的顶点(apex)154。
在实施例中，封装100包括侧壁160。侧壁160可包括介电层120的侧表面128。在实施例中，侧壁160还可包括导电基座105的侧表面110的可从下半部分164延伸到上半部分166的部分(未图示)。侧表面110的此部分与侧表面128可实质上共面。
参见图1，下半部分164及/或上半部分166可具有实质上凹入的轮廓。下半部分164及/或上半部分166可向内朝向芯片102圆化及/或弯曲。在实施例中，下半部分164及/或上半部分166可包括呈例如粗糙体(asperity)等小峰的形式的表面不均匀性或粗糙性，其可从芯片102向外圆化及/或弯曲。
如图1中所说明，下表面108和侧表面110的下半部分164可电镀有表面处理层(电镀层)137。在实施例中，表面处理层137可类似于图1所示的图案化导电层和导电孔而形成，如先前所述。或者，表面处理层137可以不同方式形成。举例来说，表面处理层137可由锡、镍和金或包括锡或包括镍与金的合金中的至少一者形成。
在实施例中，介电层120的侧表面128可定义出第一平面170。侧表面128可实质上垂直。下半部分164可具有相对于侧表面128的角偏移。下半部分164可包括邻近于导电载体105的下表面108的下半部172，以及在下半部172与上半部分166之间延伸的上半部174。下半部172可相对于第一平面170倾斜少于或近似等于15度，例如在约5度到约10度的范围内，和约10度到约15度的范围内。
在实施例中，下半部分164可包括位于侧表面110中的凹口。举例来说，下半部172可相对于上半部174凹进。凹口可环绕封装100。
图3说明根据本发明实施例的半导体封装300的剖面图。半导体封装300在许多方面类似于参见图1而描述的半导体封装100，因此此处论述半导体封装300的不同的观点。在此实施例中，侧表面110的上半部分166可实质上与介电层120的侧表面128共面。上半部分166可被暴露出来，使得介电层120或表面处理层137均不覆盖上半部分166。表面处理层137可覆盖下半部分164，而不覆盖上半部分166。或者，上半部分166可由表面处理层137覆盖。
图4说明根据本发明实施例的半导体封装401的剖面图。半导体封装401在许多方面类似于参见图1而描述的半导体封装100，因此此处论述半导体封装401的不同的观点。不同于图1的实施例，整个侧表面110可实质上与介电层120的侧表面128共面。表面处理层137可覆盖下表面108，而不覆盖侧表面110。或者，表面处理层137可覆盖下表面108以及导电基座105的侧表面110。
或者，侧表面110可包括具有与图1所示的上半部166类似的特性的上半部(未图示)。特定来说，所述上半部(未图示)可倾斜，且可实质上由介电层120覆盖。在此实施例中，侧表面110的其余部分可实质上与介电层120的侧表面128共面。表面处理层137可覆盖下表面108以及侧表面110的其余部分。或者，表面处理层137可覆盖下表面108，而不覆盖侧表面110的任一部分。
图5说明根据本发明实施例的半导体封装500的剖面图。半导体封装500在许多方面类似于参见图4而描述的半导体封装401，因此此处论述半导体封装500的不同的观点。在此实施例中，介电层120可具有比导电基座105的侧向范围大的侧向范围，使得介电层120的侧表面128不与侧表面110共面，且不与表面处理层137共面。
或者，侧表面110可包括具有与图1所示的上半部166相似特性的上半部(未图示)。特定来说，所述上半部(未图示)可倾斜，且可实质上由介电层120覆盖。在此实施例中，介电层120可具有比导电基座105的侧向范围大的侧向范围，使得介电层120的侧表面128不与侧表面110的任一部分共面，且不与表面处理层137共面。
图6A到图6P说明根据本发明实施例的制造半导体封装的方法。为了便于呈现，参见图1的封装100及/或图2的封装200来描述以下制造操作。然而，可类似地进行制造操作以形成可具有与封装100和200不同的内部结构的其它半导体封装是可被预期的，例如图3中所说明的封装300。进行制造操作以形成基底带也同样被预期，其包括连接的半导体封装阵列，所述半导体封装各自可对应于例如图1到图3中所说明的那些封装的封装。图6A到图6L中描述方法的第一实施例。图6A到图6I和随后图6M到图6N中描述方法的第二实施例。方法的第二实施例可用以形成图4中所说明的封装401。图6A到图6I和随后图6O到图6P中描述方法的第三实施例。方法的第三实施例可用以形成图5中所说明的封装500。如图6L、图6N、图6O和图6P中所描述，连接的半导体封装阵列可单一化为例如图1到图5中所说明的封装的个别封装。
首先参见图6A，提供基体基底带400。基体基底带400具有与先前针对图1和图2的导电载体105所描述类似的材料组成和厚度特性。在实施例中，开口150可形成于基体基底带400中，且从基体基底带400的上表面402部分地延伸穿过基体基底带400。每一开口150可充当对准标记以促进单一化(见图6K和图6L)。在实施例中，开口150是通过化学蚀刻而形成。开口150的壁403可倾斜。在实施例中，壁403可弯曲。壁403远离实质上垂直于上表面402的平面的倾斜程度可取决于用于蚀刻的化学溶液。或者，开口150可不形成于基体基底带400中。
或者，如图6B中所说明，凹槽112可形成于基体基底带400中。除开口150之外还可形成凹槽112。半导体装置502可至少部分地设置于凹槽504中。在实施例中，凹槽112是通过化学蚀刻而形成。凹槽112的壁114可倾斜。在实施例中，壁114可弯曲。壁114远离实质上垂直于上表面402的平面的倾斜程度可取决于用于蚀刻的化学溶液。
如图6C中所说明，将芯片102设置于邻近于基体基底带400。芯片贴附层116可设置于芯片102与基体基底带400之间。如先前参见图1所描述，芯片102可通过共晶接合贴附到基体基底带400。在共晶接合的实施例中，芯片贴附层116可由例如锡与铅的合金等软焊料形成。在此实施例中，由锡与铅的合金形成的金属丝可熔化，且随后被分配于基体基底带400上将贴附芯片102的位置处。在共晶接合的另一实施例中，芯片贴附层116可由例如金与锡的合金等硬焊料形成。金与锡的合金可设置于半导体芯片上，使得金与锡的合金贴附到芯片102。随后可通过使金与锡的合金熔化将芯片102直接贴附到基体基底带400，而无需单独的分配步骤。或者，如果不使用共晶接合，那么芯片贴附层116可由例如环氧树脂等黏合剂材料形成。可将黏合剂材料分配于基体基底带400上将贴附芯片102的位置处。
参见图6C，提供介电层410，其中介电层410预先形成有一组开口412，且开口412的位置对应于半导体装置102的位置。介电层410具有类似于先前参见图1而描述的介电层120的特性。在实施例中，介电层410包括纤维加强的树脂材料，例如预浸渍体材料，其包括纤维122以强化介电层410。如图6C所示，纤维122最初沿介电层410内的大体水平平面定向。
或者，如图6D中所说明，芯片102至少部分地设置于凹槽112中，且邻近于凹槽底部115。芯片贴附层116可设置于芯片102与凹槽底部115之间。以类似于先前参见图6C而描述的方式，芯片102可通过共晶接合或通过使用例如环氧树脂等黏合剂来贴附到凹槽底部115。而且，提供介电层414。如先前参见图1而描述，在实施例中，介电层414无需预先形成有对应于半导体装置102的位置的任何开口。这简化了形成图1的封装100和其中芯片102设置于凹槽112中的类似封装的工艺。介电层414具有与先前参见图1而描述的介电层120类似的特性。在实施例中，介电层414包括纤维加强的树脂材料，例如预浸渍体材料，其包括纤维122以强化介电层414。如图6C所示，纤维122最初沿介电层414内的大体水平的平面定向。
如所说明，图6E到图6L接在图6C之后以形成图2的封装200，但所属领域的技术人员将了解，类似的步骤可接在图6D之后以形成图1的封装100及/或图3的封装300。
如图6E中所说明，将介电层410设置于邻近于基体基底带400，且覆盖芯片102。介电层410可实质上填入开口150。如先前参见图1而描述，对于包括凹槽112的实施例，介电层414(见图6D)也可实质上填入凹槽112的尚未由芯片102填入的剩余部分。介电层410可使导电片404与芯片102分离。图6E所示的介电层410包括图2的介电层120。在实施例中，纤维122在介电层410的层压之后经重定向，其中邻近于芯片102的部分被沿着芯片102的垂直延伸方向推动，且远离基底带400。例如铜箔等导电片404可设置于邻近于介电层410，以形成(例如)覆盖芯片102的涂覆有树脂的铜层。介电层410可具有单个树脂层，或可包括由树脂制成的第一子层和由加强树脂制成的第二子层，加强树脂例如为以玻璃纤维及/或Kevlar纤维加强的树脂。
在另一实施例中，介电层410可由预浸渍体材料形成，且可将导电片404设置于邻近于介电层410。可将预浸渍体材料设置于邻近于基体基底带400，且可经预先形成以在芯片102的位置处定义出开口(见图6C)。预浸渍体材料可由一个预浸渍体层或由两个或两个以上预浸渍体层形成。或者，介电层410可包括预浸渍体子层与树脂子层的组合，且可将导电片404设置于邻近于介电层410。可将预浸渍体子层设置于邻近于基体基底带400，且可预先形成以在芯片102的位置处定义出开口(见图6C)。可将树脂子层设置于邻近于预浸渍体子层，且也可邻近于基体基底带400而设置于由预浸渍体子层定义出的开口内(见图6C)。
在另一实施例中，介电层410可由例如包封剂材料等环氧树脂模制化合物形成，且可将导电片404设置于邻近于介电层410。
在实施例中，介电层410可层压于基体基底带400上。或者，可使用例如注射模制等若干模制技术中的任一者来形成介电层410。一但实施，便(例如)通过使温度降低到低于模制材料的熔点来使模制材料硬化或固化，进而形成介电层410。或者，可使用例如印刷、旋涂或喷涂等若干涂覆技术中的任一者来形成介电层410。
在实施例中，导电片404可贴附到介电层410，之后可将介电层410设置于邻近于基体基底带400。在实施例中，可将已贴附有导电片404的介电层410设置于邻近于基体基底带400。
如图6F中所说明，形成包括开口121和123的开口。开口121延伸穿过导电片404和介电层410，以暴露出导电载体105的上表面106。开口123延伸穿过导电片404和介电层410，以暴露出半导体装置202的有源表面103。可通过激光钻孔、机械钻孔或此项技术中已知的其它合适方法来形成开口121和123。
如图6G中所说明，开口121和123以导电材料填入以形成导电孔142和144。可使用例如无电电镀及/或电解电镀等若干涂覆技术中的任一者来形成导电孔142和144。
如图6H中所说明，包括接触区133和134的图案化导电层130邻近于介电层410而形成。可通过加成工艺、半加成工艺或削去工艺(subtractiveprocess)形成图案化导电层130。图案化导电层130可包括一组焊垫(pad)和一组迹线(trace)，其可在常见工艺操作中实质上同时形成。
如图6I中所说明，将介电层413设置于邻近于介电层410和基体基底带400。图6I中所示的介电层413包括图1的介电层140。介电层413可采用类似于先前参见图6E针对介电层410描述的方式形成。
如图6J中所说明，开口152形成于基体基底带400中。在实施例中，开口152可从下表面406延伸穿过基体基底带400，使得开口152暴露出介电层120。或者，开口152可从基体基底带400的下表面406部分地延伸穿过基体基底带400，且可通过导电载体105的一部分(未图示)与开口152中的对应一者分离。此部分(未图示)的厚度可显著小于基体基底带400的其它部分的厚度，这可促进单一化。
如先前参见图1所描述，每一开口150可与开口152中的对应一者相对定位，使得每一开口150实质上与开口152中的对应一者对准。每一开口150可具有实质上与开口152中的对应一者相同的宽度，或可具有与开口152中的对应一者不同的宽度。
在实施例中，开口152是通过化学蚀刻而形成。如先前参见图1而描述，开口152的壁的下半部分164可实质上凹入。下半部分164可朝芯片102向内圆化及/或弯曲。下半部分164远离平面170的倾斜程度(见图1)可取决于用于蚀刻的化学溶液。
如图6K中所说明，表面处理层135和136分别邻近于接触窗133和134而形成。表面处理层137邻近于导电载体105的下表面406以及侧表面110的下半部分164而形成。可使用无电镍/浸渍金(immersion gold)工艺来形成表面处理层135、136和137。
如图6L中所说明，接着可沿着虚线420执行单一化以获得例如图2的封装200等个别封装。单一化产生切割裂缝，其将基体基底带400细分为具有包括下半部分164的侧表面110的导电载体105(见图1到图3)。
参见图1，如果使用小尺寸刀及/或锯来进行参见图6L而描述的单一化及/或穿孔步骤，那么可在对应于开口150的位置处执行单一化。当使用较小的且成本较低的锯时，在此位置执行单一化可为令人满意的，因为导电载体105在此位置处的厚度由于开口150而减小。在此实施例中，由于沿着虚线420的单一化而产生的切割裂缝延伸穿过介电层120、第一开口150和对应的第二开口152。在此位置处，由于单一化而产生的封装100的侧壁160是包括介电层120的侧表面128的实质上共面表面。侧壁160可实质上垂直于介电层120的上表面124。在此实施例中，侧表面110的下半部分164对应于开口152的边界。侧表面110的上半部分166可实质上由介电层120覆盖。
参见图3，如果使用大尺寸刀及/或锯来进行参见图6L而描述的单一化及/或穿孔步骤(punch step)，那么可在从开口150移开(displace)的位置处执行单一化。在此实施例中，由于沿着虚线420的单一化而产生的切割裂缝延伸穿过介电层120、导电载体105的上半部分166以及上半部分166下方的第二开口152。在此位置处，由于单一化而产生的封装100的侧壁160是包括介电层120的侧表面128以及导电载体105的侧表面110的上半部分166的实质上共面表面。侧壁160可实质上垂直于介电层120的上表面124。在此实施例中，侧表面110的上半部分166可从介电层120的侧表面128延伸到侧表面110的下半部分164。不同于图1的实施例，单一化可从开口150移开。在实施例中，在单一化之后，表面处理层137可邻近于侧表面110的上半部分166而形成。
参见图1和图6L，在替代实施例中，由于沿着虚线420的单一化及/或穿孔而产生的切割裂缝可延伸穿过介电层120、第一开口150和第一开口150下方的对应第二开口152。在此实施例中，切割裂缝还延伸穿过导电载体105的使第一开口150与对应第二开口152分离的部分(未图示)。在单一化之后，侧表面110的半部分164可在导电载体105的下表面406与介电层120的侧表面128之间延伸。
如图6M中所说明，在替代实施例中，表面处理层135和136分别邻近于接触区133和134而形成。表面处理层137邻近于基体基底带400的下表面406而形成。可使用无电镍/浸渍金工艺来形成表面处理层135、136和137。如先前参见图6A所描述，开口150可形成于基体基底带400中，或可不形成于基体基底带400中。
如图6N中所说明，接着可沿着虚线420执行单一化以获得例如图4的封装401等个别封装。单一化产生切割裂缝，其将基体基底带400细分为具有侧表面110的导电载体105(见图4)。在此实施例中，侧表面110可实质上与介电层120的侧表面128共面。或者，侧表面110的一部分(未图示)可实质上由介电层120覆盖，且侧表面110的剩余部分可实质上与侧表面128共面。因为基体基底带400的单一化是在导电载体105的下表面406上形成表面处理层137之后发生，所以侧表面110未由表面处理层137覆盖。在实施例中，在单一化之后，可邻近于侧表面110的至少一部分而形成表面处理层137。
如图6O中所说明，在另一替代实施例中，可沿着虚线430执行基体基底带400的单一化。单一化产生将基体基底带400细分为具有侧表面110的导电载体105(见图5)的切割裂缝。可用适合于切割金属材料的第一锯来执行此单一化。在此实施例中，侧表面110可实质上为平面的。或者，侧表面110的一部分(未图示)可相对于由虚线430定义出的平面倾斜，且可实质上由介电层120覆盖。
如图6P中所说明，表面处理层135和136分别邻近于接触区133和134而形成。表面处理层137可邻近于下表面406而形成。在实施例中，表面处理层137也可邻近于导电载体105的侧表面110的至少一部分而形成。可使用无电镍/浸渍金工艺来形成表面处理层135、136和137。
接着可沿着虚线420执行介电层120的单一化以获得例如图5的封装500等个别封装。可用适合于切割介电材料的第二锯来执行此单一化，其中第二锯不同于参见图6O的使基体基底带400单一化的第一锯。如果基体基底带400中存在开口150，那么切割裂缝可与开口150对准。
虽然已参见本发明的具体实施例描述和说明了本发明，但这些描述和说明不限制本发明。所属领域的技术人员应理解，在不脱离如由权利要求界定的本发明的真实精神和范围的情况下，可进行各种改变且等同特征可被取代。附图可能不一定按比例绘制，且制造公差可能会导致偏离本文所阐述的工艺概念。可能存在未具体说明的本发明的其它实施例。因此，说明书和附图应视为说明性的而不是限制性的。另外，为了清楚，说明本发明实施例的图式可着重于某些主要特性特征。此外，可进行修改以使特定情形、材料、物质组成、方法或工艺适于本发明的目标、精神和范围。所有这些修改在权利要求的范围内。特定来说，虽然已参考以特定次序执行的特定操作而描述了本文所揭示的方法，但可理解的是，在不脱离本发明教导的情况下，这些操作可经组合、细分或重排序以形成等同方法。因此，除非本文具体指示，否则操作的次序和分组不是对本发明的限制。

Claims (17)

1.一种半导体封装，包括：
导电载体，其具有上表面、下表面和侧表面，所述侧表面包括邻近于所述导电载体的所述上表面的第一部分和邻近于所述导电载体的所述下表面的第二部分，其中所述第二部分相对于所述导电载体的所述下表面而向内倾斜；
芯片，设置于邻近于所述导电载体的所述上表面；
图案化导电层；以及
介电材料，其包封所述芯片，其中所述介电材料定义出开口，所述图案化导电层穿过所述开口电连接到所述导电载体的所述上表面，其中所述第二部分包括环绕所述半导体封装的凹口。
2.如权利要求1所述的半导体封装，其中所述第一部分倾斜。
3.如权利要求2所述的半导体封装，其中所述介电材料具有侧表面，且包封所述第一部分。
4.如权利要求1所述的半导体封装，其中所述导电载体的所述侧表面包括位于所述第一部分与所述第二部分之间的接面处的顶点。
5.如权利要求1所述的半导体封装，其中：
所述介电材料具有侧表面；以及
所述第一部分与所述介电材料的所述侧表面共面。
6.如权利要求1所述的半导体封装，其中：
所述介电材料具有定义出平面的侧表面；
所述第二部分包括邻近于所述导电载体的所述下表面的下半部，以及在所述下半部与所述导电载体的所述侧表面的所述第一部分之间延伸的上半部；以及
所述第二部分的所述下半部相对于所述平面倾斜少于15度。
7.如权利要求1所述的半导体封装，其还包括耦合到所述导电载体的所述下表面的电镀层。
8.如权利要求7所述的半导体封装，其中所述电镀层更耦合到所述第二部分。
9.如权利要求1所述的半导体封装，其中所述导电载体定义出包括于所述导电载体的所述上表面中的具有凹槽底部的凹槽。
10.一种半导体封装，包括：
导电载体，其具有上表面、下表面和侧表面，所述侧表面包括邻近于所述导电载体的所述上表面的第一部分、邻近于所述导电载体的所述下表面的第二部分，以及位于所述第一部分与所述第二部分之间的接面处的顶点；
芯片，设置于邻近于所述导电载体的所述上表面；以及
介电材料，其具有垂直的侧表面，且包封所述第一部分，
其中所述第二部分具有相对于所述垂直的侧表面的角偏移；以及
其中所述第二部分包括环绕所述半导体封装的凹口。
11.如权利要求10所述的半导体封装，其中：
所述导电载体定义出包括于所述导电载体的所述上表面中的凹槽；
所述凹槽具有第一高度；
所述芯片具有第二高度；以及
所述第一高度至少与所述第二高度一样大。
12.如权利要求10所述的半导体封装，其还包括耦合到所述导电载体的所述下表面的电镀层。
13.一种形成半导体封装的方法，包括：
提供具有上表面和下表面的金属层；
形成从所述金属层的所述上表面延伸且部分地穿过所述金属层的第一开口；
将芯片设置于邻近于所述金属层的所述上表面；
用具有背对所述芯片的上表面的介电层包封所述芯片和所述金属层的所述上表面的至少一部分，所述介电层填入所述第一开口；
在所述介电层中形成第二开口，所述第二开口暴露出所述金属层的所述上表面；
邻近于所述介电层的所述上表面而形成图案化导电层；
形成延伸穿过所述第二开口的导电孔，所述导电孔将所述图案化导电层电连接到所述金属层；
形成从所述金属层的所述下表面延伸且部分地穿过所述金属层的第三开口，所述第三开口与所述第一开口对准及所述金属层包括邻近于所述第三开口的凹口；以及
邻近于所述金属层的所述下表面而形成表面处理层。
14.如权利要求13所述的形成半导体封装的方法，其中所述第三开口延伸穿过所述金属层以暴露出所述介电层。
15.如权利要求13所述的形成半导体封装的方法，其中所述金属层包括邻近于所述第三开口的倾斜部分，且所述方法还包括形成切割裂缝，所述切割裂缝延伸穿过所述介电层、所述第一开口和所述第三开口，使得所述金属层经细分以形成具有包括所述倾斜部分的侧表面的导电载体。
16.如权利要求15所述的形成半导体封装的方法，其中：
所述介电层具有定义出平面的侧表面；
所述倾斜部分包括邻近于所述导电载体的所述下表面的下半部，以及由所述介电层覆盖的上半部；以及
所述下半部相对于所述平面倾斜少于15度。
17.如权利要求13所述的形成半导体封装的方法，其还包括：
在所述金属层中形成凹槽，所述凹槽具有包括于所述金属层的所述上表面中的具有凹槽底部的凹槽；以及
将所述芯片设置于邻近于所述凹槽底部，其中所述凹槽的第一高度与所述芯片的第二高度至少一样大。
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US8487426B2 (en) 2013-07-16

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