TWI550741B - 四方扁平無接腳封裝及其製造方法 - Google Patents

四方扁平無接腳封裝及其製造方法 Download PDF

Info

Publication number
TWI550741B
TWI550741B TW101118113A TW101118113A TWI550741B TW I550741 B TWI550741 B TW I550741B TW 101118113 A TW101118113 A TW 101118113A TW 101118113 A TW101118113 A TW 101118113A TW I550741 B TWI550741 B TW I550741B
Authority
TW
Taiwan
Prior art keywords
package
lead frame
pin
conductive layer
matrix
Prior art date
Application number
TW101118113A
Other languages
English (en)
Other versions
TW201250885A (en
Inventor
沈更新
Original Assignee
南茂科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南茂科技股份有限公司 filed Critical 南茂科技股份有限公司
Publication of TW201250885A publication Critical patent/TW201250885A/zh
Application granted granted Critical
Publication of TWI550741B publication Critical patent/TWI550741B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8191—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Description

四方扁平無接腳封裝及其製造方法
本發明係關於一種四方扁平無接腳(Quad Flat Non-leaded；QFN)封裝及其製造方法，更具體而言，係關於一種具有複數個複合凸塊之四方扁平無接腳封裝。
半導體封裝方法已廣泛用於以較佳之可靠性電性連接一半導體晶片至一外部組件，且亦用於保護半導體晶片免受外部條件所造成之損壞。然而，所用之封裝材料及封裝方法不僅與製造成本相關聯，且亦影響所封裝之晶片之運作效能。為此，所選用之封裝結構及其材料變得至關重要。
在若干種封裝技術中，四方扁平無接腳(Quad Flat Non-leaded；QFN)半導體封裝近年來由於其封裝尺寸較小而廣受歡迎。在一習知四方扁平無接腳半導體封裝中，一晶片藉由導線而電性連接至一導線框架，該晶片之每一接合焊墊(bond pad)分別電性連接至該導線框架之一相對應接腳。對於一覆晶(flip chip)四方扁平無接腳封裝10，一晶片101藉由凸塊105而電性連接至一導線框架103，如第1A圖或第1C圖所示。晶片101係藉由以一焊錫凸塊(第1A圖)或一具有一焊帽(solder cap)之銅柱(copper pillar)進行焊接接合而被倒裝並接合於導線框架103上。因採用使該焊錫凸塊或銅柱上之焊帽熔融之迴流焊接來焊接接合晶片101之凸塊105與導線框架103之接腳，故接腳寬度將受限於是否具有足 夠之空間以避免熔融之焊錫在迴流焊接製程期間溢流至接腳之相對側(第1B圖)。若該熔融之焊錫107溢流於接腳之相對側上，將導致其他製程(例如封裝或表面黏著技術(surface mounting technology，SMT))之組裝缺陷。
遺憾地，有時因晶片尺寸及封裝尺寸之限制，可能無法將接腳寬度設計成具有足夠之空間以避免熔融之焊錫溢流。有鑒於此，此項技術中亟需提供一種可改良接腳寬度之限制且亦能降低一封裝結構之製造成本之解決方案。
本發明之主要目的在於提供一種四方扁平無接腳(Quad Flat Non-leaded，QFN)封裝，其包含一晶片、一導線框架、複數個複合凸塊及一封裝體。該晶片具有複數個焊墊，且該導線框架具有複數個接腳。在該晶片接合至該導線框架之前，一半固化封裝體形成於該導線框架之該等接腳間之空間中。每一該等複合凸塊具有一第一導電層及一第二導電層。該第一導電層電性連接於該等焊墊其中之一與該第二導電層之間，且該第二導電層電性連接於該第一導電層與該等接腳其中之一之間。該封裝體適可封裝該晶片、該等接腳及該等複合凸塊。藉此，提供一種具有複數個複合凸塊及一半固化封裝體之四方扁平無接腳封裝，其中該半固化封裝體係在該晶片接合至該導線框架之前形成於該導線框架之該等接腳間之空間中。
為提供所述四方扁平無接腳封裝，本發明之製造方法包含以下 步驟：形成複數個導線框架模組；形成複數個晶片模組，各該晶片模組具有一晶片，該晶片與複數個複合凸塊連接；分別連接該等複合凸塊至該等接腳而將該等導線框架模組接合至該等晶片模組；以及封裝並單離(singulating)該等晶片模組與該等導線框架模組而形成複數個四方扁平無接腳封裝。
當採用一熱超音波接合(thermo-ultrasonic bonding)時，該形成複數個導線框架模組之步驟包含以下步驟：藉由一半固化封裝體形成一上部單元至一頂部載體上；藉由設置一矩陣導線框架於一底部載體上而形成一下部單元，其中該矩陣導線框架包含複數個接腳；層壓該半固化封裝體與該矩陣導線框架以使該等接腳接觸該頂部載體，進而接合該上部單元與該下部單元；完全固化該封裝體並移除該頂部載體以確保接腳之上表面不低於該封裝體，進而形成該等導線框架模組。須注意者，該將該等導線框架模組接合至該等晶片模組之步驟可藉由熱超音波接合、迴流焊接(reflowing)及施用一導電膠其中之一而執行。
相較於習知技術，本發明具有以下有益效果：本發明之四方扁平無接腳封裝及其製造方法以複合凸塊及一所封裝之矩陣導線框架取代習知凸塊，故該四方扁平無接腳封裝之該等複合凸塊間之節距及該等複合凸塊之高度可得以控制，且由該等複合凸塊形成之較短的互連迴路可減小電阻及電感並改良整個該四方扁平無接腳封裝之效能。
為讓本發明之上述目的、技術特徵和優點能更明顯易懂，下文係以較佳實施例配合所附圖式進行詳細說明。
以下將透過實施例來解釋本發明內容。本發明係關於一種四方扁平無接腳封裝及其製造方法。然而，本發明的實施例並非用以限制本發明需在如實施例所述之任何環境、應用或方式方能實施。因此，關於實施例之說明僅為闡釋本發明之目的，而非用以直接限制本發明。需說明者，在以下實施例及圖示中，與本發明非直接相關之元件已省略而未繪示；且為易於理解，圖式中各元件間之尺寸關係係以誇大之方式繪示。
參照第2A圖，其中顯示根據本發明之一四方扁平無接腳封裝1之一較佳實施例。四方扁平無接腳封裝1包含一晶片11、一導線框架13、複數個複合凸塊15以及一封裝體17。
晶片11具有一有效表面113、複數個焊墊111以及一鈍化層。焊墊111形成於晶片11之有效表面113上。更具體而言，焊墊111佈置於有效表面113之四側；在其他態樣中，焊墊111可僅佈置於有效表面113之二平行側。各該焊墊111皆被鈍化層115局部覆蓋，故各該焊墊111之某一部分係為暴露的以供電性連接。在本發明中，晶片11可為例如一顯示驅動器電路積體電路(integrated circuit；IC)、一影像感測器積體電路、一記憶體積體電路、一邏輯積體電路、一類比積體電路、一超高頻(ultra-high frequency；UHF)積體電路或一射頻(radio frequency；RF)積體電路，但本發明並不僅限於此。
導線框架13具有複數個接腳131，接腳131在本實施例中被佈 置於四個側而形成一正方形(圖未示出)。每一接腳131具有一內部接腳區131a及一外部接腳區131b。如第2A圖所示，各該內部接腳區131a與各該外部接腳區131b具有一高度差，內部接腳區131a係高於外部接腳區131b。
複合凸塊15電性連接於晶片11與導線框架13之間。每一複合凸塊15具有一第一導電層151及一第二導電層153，且第二導電層153係軟於第一導電層151。第一導電層151電性連接於晶片11之該等焊墊111其中之一相對應焊墊111與第二導電層153之間。第二導電層153電性連接於第一導電層151與導線框架13之接腳131之內部接腳區131a其中之一相對應內部接腳區131a之間。因此，複合凸塊15係藉由第一導電層151而電性連接至晶片11之焊墊111，且藉由第二導電層153而電性連接至導線框架13之接腳131之內部接腳區131a。第一導電層151之一材料可選自由以下組成之群組：銅、鎳、鋁、鋅及其組合。第二導電層153之一材料可選自由以下組成之群組：金、銅、銀、錫、鋅、銦及其組合。由金製成之第二導電層153所形成之一厚度係至少小於複合凸塊15之總高度之一半。減少金會降低製造成本。
須注意者，上述複合凸塊15僅供作為一實例；如此項技術中之通常知識者可理解，複合凸塊15亦可為由其他現有凸塊相組合而形成之「複合」凸塊結構(例如，複合凸塊係由二層柱形凸塊形成)，以滿足對不同種類之倒裝晶片與基板間之電性連接之不同需求並藉由減少金之使用而降低製造成本。
封裝體17封裝晶片11、接腳131及複合凸塊15。在該實施例 中，封裝體17係圍繞晶片11及複合凸塊15而形成，並覆蓋除導線框架13之接腳131之外部接腳區131b之底面以外的導線框架13之幾乎整個表面。封裝體17之一材料可選自：例如丙烯酸樹脂、聚醯亞胺樹脂或聚碸樹脂等熱塑性樹脂，例如環氧樹脂、酚醛樹脂、三聚氰胺樹脂或聚脂樹脂等熱固性樹脂，或其組合。此外，封裝體17較佳係由具有低熱膨脹係數(coefficient of thermal expansion，CTE)及低模量之材料製成。
各該複合凸塊15藉由熱超音波接合、迴流焊接或在其之間施用導電膠而連接至導線框架13之接腳131之相對應內部接腳區131a之上表面。在該實施例中，複合凸塊15係藉由熱超音波接合而連接至接腳131。在本發明之另一態樣中，四方扁平無接腳封裝更包含複數個電鍍結構，該等電鍍結構其中之一係附著於該第二導電層與接腳之間以藉由迴流焊接而將各該複合凸塊連接至該導線框架之接腳之相對應內部接腳區。該電鍍結構係為一焊錫或一具有一焊帽之銅柱。此外，在本發明之另一態樣中，四方扁平無接腳封裝更包含複數個導電膠，該等導電膠分別設置及附著於每一該等複合凸塊與該等接腳其中之一相對應接腳之間。導電膠可為銀膠或焊錫。
須注意者，在熱超音波接合之後將出現熱應力，且內部接腳區131a之上表面將會彎曲、裂開或甚至斷裂。同時，若應用一低熔融溫度之軟熔融材料作為焊料(圖未示出)以接合凸塊15與導線框架13之接腳131之內部接腳區131a，則該軟熔融材料將會溢流並於另一組裝過程中造成某些缺陷。為避免此類缺陷，本發明更 提供一種四方扁平無接腳封裝1'，其採用一種特定製造方法並將稍後予以詳述，四方扁平無接腳封裝1'更具有一封裝介面19，封裝介面19不高於導線框架13之一上表面，如第2B圖所示。更詳細而言，封裝體17係僅圍繞晶片及複合凸塊形成，完全固化封裝體17'係於封裝體17下面圍繞導線框架13之接腳131形成，且封裝體17與完全固化封裝體17'間之介面即為封裝介面19。
在下文中，將參照上述說明以及附圖第3A圖至第3E圖、第4A圖至第4C圖、第5A圖至第5B圖詳細說明用於製造本發明上述實施例之四方扁平無接腳封裝之製造方法。須注意者，為簡明起見，在以下說明及附圖中僅以一個晶片作為一代表性實例來說明用於製造四方扁平無接腳封裝之製造方法，且各元件之材料或相關說明與上述相同而予以省略。
在該特定製造方法中，並非在熟知之四方扁平無接腳封裝製造方法中提供一矩陣導線框架，而是提供複數個導線框架模組。參照第3A圖，如圖所示，形成一半固化封裝體17"至一頂部載體41上而形成一上部單元3a。頂部載體41可為金屬、玻璃、有機薄膜或塑膠，其可為半固化封裝體17"提供一扁平表面及適當強度。然後，如第3B圖所示，藉由設置一矩陣導線框架6(如第6圖所示)於一底部載體31上而形成一下部單元3b，載體31可為有機薄膜、玻璃、塑膠或金屬。如第3B圖及第6圖所示，矩陣導線框架6包含複數個導線框架13，各該導線框架13包含複數個接腳131，且每一接腳131具有一內部接腳區131a及一外部接腳區131b。底部載體31與導線框架13間之適當附著係為另一製程所需。須注意 者，並不限制第3A圖及第3B圖所示過程之執行順序。
然後，如第3C圖所示，層壓半固化封裝體17"與該矩陣導線框架以使接腳131接觸頂部載體41，進而接合上部單元3a與下部單元3b。更詳細而言，頂部載體41接觸接腳131之內部接腳區131a之上表面。因半固化封裝體17"被部分地固化且係為一半流質物質(semifluid substance)，故除內部接腳區131a之上表面及外部接腳區131b之底面外之接腳131將被上部單元3a之半固化封裝體17"密封。
接著，參照第3D圖，如圖所示，將半固化封裝體17"完全固化為完全固化封裝體17'並移除頂部載體41，進而形成一導線框架模組3d(或第3E圖所示之3e)於該矩陣導線框架之每一導線框架13上。在移除頂部載體41之後，完全固化封裝體17'之上表面可與接腳131之內部接腳區131a之上表面一樣高(或如第3E圖所示低於內部接腳區131a之上表面)。因此，形成矩陣導線框架上之導線框架模組3d(或第3E圖所示之3e)。
參照第4A圖，如圖所示，提供一晶圓30。晶圓30形成有內部電路、一有效表面113、複數個焊墊111以及一鈍化層115。焊墊111設置於有效表面113上且被鈍化層115局部覆蓋以提供暴露區域(或稱為「開口」)。訊號將經由焊墊111之該等暴露區域而自該等內部電路傳送或傳送至該等內部電路。
參照第4B圖，如圖所示，形成一複合凸塊15於每一焊墊111上。每一複合凸塊15包含一第一導電層151及一第二導電層153，且第一導電層151直接連接至且設置於焊墊111其中之一相對應 焊墊111與第二導電層153之間。因此，晶圓30之該等內部電路與複合凸塊15經由焊墊111之該等暴露區域而電性連接。然後，如第4C圖所示，切割晶圓30以提供複數個晶片11，各該晶片11皆電性連接複數個複合凸塊15。如此項技術中之通常知識者在迴顧上述說明之後將理解，在本發明中亦可應用用於複合凸塊之其他習知方法，且對此不再予以贅述。
另一方面，根據第3A圖至第3E圖所示步驟提供複數個導線框架模組，該等導線框架模組設置於並形成於一底部載體31上之矩陣導線框架6上。矩陣導線框架6(如第6圖所示)包含複數個導線框架13，且各該導線框架13具有複數個如上所述之接腳131。並且，除內部接腳區131a之上表面及外部接腳區131b之底面外，矩陣導線框架6之接腳131被完全固化封裝體17'封閉。第5A圖顯示以下步驟：藉由複合凸塊15來接合各該晶片11至該矩陣導線框架上之導線框架模組之導線框架13的相對應複數個接腳131。各該晶片11藉由複數個複合凸塊15而電性連接至該矩陣導線框架之部分接腳131。每一複合凸塊15之第二導電層153藉由熱超音波接合、迴流焊接及施用一導電膠而直接連接至導線框架13之相對應接腳131之內部接腳區131a的上表面。已知若應用迴流焊接，則複合凸塊15與內部接腳區131a之間會存在焊錫，此種焊錫未示出於第5A圖中。
然後，如第5B圖所示，對晶片11、該矩陣導線框架上之導線框架13以及複合凸塊15予以封裝。封裝體17係圍繞晶片11及複合凸塊15而形成，並藉由轉移模塑(transfer molding)、絲網印 刷、塗布或注射等而覆蓋除接腳131之外部接腳區131b之底面外的導線框架13之幾乎整個表面。在此類情形中會形成封裝介面19，無論封裝體17之材料是否與完全固化封裝體17'者相同。最後，如第2圖所示，單離該矩陣導線框架並剝除底部載體31以形成四方扁平無接腳封裝1。四方扁平無接腳封裝1包含已封裝之晶片11其中之一及部分已封裝之該矩陣導線框架。
當採用熱超音波接合時，在熱超音波接合之後將出現熱應力，且內部接腳區131a之上表面將不會彎曲、開裂或甚至斷裂。並且，在本發明中將不再出現熔融焊錫溢流。
在另一態樣中，複合凸塊可更包含至少一凸塊下金屬化(under bump metallization；UBM)層、或一第三導電覆蓋層及一阻隔層。參照第7圖，如圖所示，晶片11經由複數個焊墊111而電性連接至複數個複合凸塊。各該複合凸塊2包含一凸塊下金屬化(UBM)層21、一第一導電層23、一第二導電層25、一第三導電覆蓋層27以及一阻隔層29。凸塊下金屬化層21設置於第一導電層23與晶片11之焊墊111之間。第一導電層23位於凸塊下金屬化層21上，第二導電層25繼而位於第一導電層23上。第三導電覆蓋層27覆蓋各該複合凸塊2之表面，其包括第二導電層25及第一導電層23。阻隔層29位於第一導電層23與第二導電層25之間。凸塊下金屬化層21之一材料可選自鈦、鎢、銅、金及其合金。第三導電覆蓋層27可由金製成，但本發明並不僅限於此。阻隔層29可由鎳製成，但本發明並不僅限於此。
此外，第4A圖所示形成晶圓30之步驟可更包含以下步驟：形 成一重佈層(redistribution layer；RDL)51於晶片11之各該焊墊111上，以用於各該複合凸塊2之第一導電層151間之電性連接；以及如第8圖所示，形成一第一導電層151於各該重佈層51上並形成一第二導電層153於第一導電層151上以重新佈置凸塊位置，進而形成複合凸塊15。
藉由該等複合凸塊，四方扁平無接腳封裝1之複合凸塊15間之節距及其高度可得以控制，且由該等複合凸塊15形成之短互連迴路可減小電阻及電感並改良整個四方扁平無接腳封裝之效能。此外，對導線框架進行預先模製可避免內部接腳區之不同水平高度等問題並保護接腳表面。
上述之實施例僅用來舉例本發明之實施態樣，以及闡述本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。
1‧‧‧四方扁平無接腳封裝
1'‧‧‧四方扁平無接腳封裝
2‧‧‧複合凸塊
3a‧‧‧上部單元
3b‧‧‧下部單元
3d‧‧‧導線框架模組
3e‧‧‧導線框架模組
6‧‧‧矩陣導線框架
10‧‧‧覆晶四方扁平無接腳封裝
11‧‧‧晶片
13‧‧‧導線框架
15‧‧‧複合凸塊
17‧‧‧封裝體
17'‧‧‧完全固化封裝體
17"‧‧‧半固化封裝體
19‧‧‧封裝介面
21‧‧‧凸塊下金屬化層
23‧‧‧第一導電層
25‧‧‧第二導電層
27‧‧‧第三導電覆蓋層
29‧‧‧阻隔層
30‧‧‧晶圓
31‧‧‧底部載體
41‧‧‧頂部載體
51‧‧‧重佈層
101‧‧‧晶片
103‧‧‧導線框架
105‧‧‧凸塊
107‧‧‧焊錫
111‧‧‧焊墊
113‧‧‧有效表面
115‧‧‧鈍化層
131‧‧‧接腳
131a‧‧‧內部接腳區
131b‧‧‧外部接腳區
151‧‧‧第一導電層
153‧‧‧第二導電層
第1A圖至第1C圖係為習知覆晶四方扁平無接腳封裝之示意圖；第2A圖係為根據本發明一較佳實施例之一四方扁平無接腳封裝結構之剖面圖；第2B圖係為根據本發明一較佳實施例之另一四方扁平無接腳封裝結構之剖面圖；第3A圖至第3E圖係為例示根據本發明一實施例之一種製造一四方扁平無接腳封裝之一導線框架模組之方法之示意圖； 第4A圖至第4C圖係為例示根據本發明一實施例之一種製造一四方扁平無接腳封裝之一晶片之方法之示意圖，該晶片電性連接複數個複合凸塊；第5A圖至第5B圖係為例示根據本發明一實施例之一種製造一四方扁平無接腳封裝之方法之示意圖；第6圖係為本發明之一矩陣導線框架之示意圖；第7圖係為根據本發明較佳實施例之另一態樣之一複合凸塊之剖面圖；以及第8圖係為根據本發明較佳實施例之另一態樣之一晶片之剖面圖。
1'‧‧‧四方扁平無接腳封裝
11‧‧‧晶片
13‧‧‧導線框架
15‧‧‧複合凸塊
17‧‧‧封裝體
17'‧‧‧完全固化封裝體
19‧‧‧封裝介面
111‧‧‧焊墊
113‧‧‧有效表面
115‧‧‧鈍化層
131‧‧‧接腳
131a‧‧‧內部接腳區
131b‧‧‧外部接腳區
151‧‧‧第一導電層
153‧‧‧第二導電層

Claims (3)

  1. 一種用於複數個四方扁平無接腳封裝之製造方法，包含以下步驟：提供一導線框架模組，包含以下步驟：形成一半固化封裝體至一頂部載體上，以構成一上部單元；設置一矩陣導線框架於一底部載體上，以構成一下部單元；其中各該矩陣導線框架包含複數接腳，且每一接腳係由一內部接腳區及一外部接腳區一體成型而成，而該內部接腳區高於該外部接腳區，其中該內部接腳區具有一第一上表面以及與該第一上表面平行設置之一第一底面，該外部接腳區具有一第二上表面以及與該第二上表平行設置之一第二底面，且該第一上表面高於該第二上表面，該第一底面高於該第二底面；層壓該半固化封裝體與該矩陣導線框架，以接合該上部單元與該下部單元；其中該內部接腳區的該第一上表面接觸該頂部載體，該外部接腳區的該第二底面接觸該底部載體；固化該半固化封裝體，以形成一完全固化封裝體；以及移除頂部載體，以形成該導線框架模組，其中該完全固化封裝體的一上表面不高於該內部接腳區的該第一上表面； 接合複數個晶片於該導線框架模組之該矩陣導線框架上，其中該等晶片藉由複數個凸塊與該矩陣導線框架之該等接腳之該內部接腳區之該第一上表面電性連接；以一封裝體依序封裝該等晶片、該等凸塊及該導線框架模組，其中該封裝體覆蓋於該內部接腳區之該第一上表面，並圍繞該等晶片及該等凸塊而成，其中該封裝體與該完全固化封裝體之間具有一封裝介面，該封裝介面不高於該矩陣導線框架之該內部接腳區之該第一上表面；及單離(singulating)已封裝之該等晶片及已封裝之該導線框架模組以形成一四方扁平無接腳封裝，其中該四方扁平無接腳封裝包含已封裝之該等晶片其中之一及部分已封裝之該矩陣導線框架。
  2. 如請求項1所述之製造方法，其中每一該等凸塊係為一複合凸塊，該複合凸塊具有一第一導電層及一第二導電層，該第二導電層較該第一導電層軟。
  3. 如請求項1所述之製造方法，其中該等凸塊係藉由一熱超音波接合(thermo-ultrasonic bonding)直接連接該矩陣導線框架之該等接腳。
TW101118113A 2011-06-10 2012-05-22 四方扁平無接腳封裝及其製造方法 TWI550741B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/158,124 US20120313234A1 (en) 2011-06-10 2011-06-10 Qfn package and manufacturing process thereof

Publications (2)

Publication Number Publication Date
TW201250885A TW201250885A (en) 2012-12-16
TWI550741B true TWI550741B (zh) 2016-09-21

Family

ID=47292469

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101118113A TWI550741B (zh) 2011-06-10 2012-05-22 四方扁平無接腳封裝及其製造方法

Country Status (3)

Country Link
US (2) US20120313234A1 (zh)
CN (1) CN102820276B (zh)
TW (1) TWI550741B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5271949B2 (ja) * 2009-09-29 2013-08-21 ルネサスエレクトロニクス株式会社 半導体装置
KR101970361B1 (ko) * 2012-08-20 2019-04-19 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조방법
JP6238121B2 (ja) * 2013-10-01 2017-11-29 ローム株式会社 半導体装置
CN103730429B (zh) * 2013-12-05 2017-06-20 通富微电子股份有限公司 封装结构
CN103730380B (zh) * 2013-12-05 2017-02-15 通富微电子股份有限公司 封装结构的形成方法
CN103730428B (zh) * 2013-12-05 2017-09-08 通富微电子股份有限公司 封装结构
WO2015123952A1 (zh) 2014-02-24 2015-08-27 南通富士通微电子股份有限公司 半导体封装结构及其形成方法
CN103903989A (zh) * 2014-02-24 2014-07-02 南通富士通微电子股份有限公司 半导体封装结构的形成方法
CN104064545A (zh) * 2014-02-24 2014-09-24 南通富士通微电子股份有限公司 半导体封装结构
CN103887187B (zh) * 2014-02-24 2018-11-23 通富微电子股份有限公司 半导体封装结构的形成方法
CN104835772B (zh) * 2015-04-24 2018-01-09 江苏长电科技股份有限公司 一种qfn后贴膜球焊压板
CN105118818B (zh) * 2015-07-20 2018-08-21 东南大学 一种方形扁平无引脚封装结构的功率模块
US10804185B2 (en) 2015-12-31 2020-10-13 Texas Instruments Incorporated Integrated circuit chip with a vertical connector
JP2017147272A (ja) 2016-02-15 2017-08-24 ローム株式会社 半導体装置およびその製造方法、ならびに、半導体装置の製造に使用されるリードフレーム中間体
CN106373931B (zh) * 2016-10-11 2019-05-17 江阴芯智联电子科技有限公司 一种高密度芯片重布线封装结构及其制作方法
CN106409786A (zh) * 2016-12-02 2017-02-15 上海芯石微电子有限公司 一种双向esd防护二极管的dfn封装结构及制造方法
US10748863B2 (en) * 2016-12-30 2020-08-18 Texas Instruments Incorporated Semiconductor devices having metal posts for stress relief at flatness discontinuities
JP7416638B2 (ja) 2020-02-05 2024-01-17 ローム株式会社 半導体装置および半導体装置の製造方法
JP2022113952A (ja) * 2021-01-26 2022-08-05 エイブリック株式会社 半導体装置およびその製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW530398B (en) * 2002-03-19 2003-05-01 Chipmos Technologies Inc Method for manufacturing bumps of chip scale package (CSP)
US20050077624A1 (en) * 2003-10-09 2005-04-14 Advanpack Solutions Pte. Ltd. Pillar structures
US20070001278A1 (en) * 2005-06-30 2007-01-04 Oseob Jeon Semiconductor die package and method for making the same
TW200737472A (en) * 2006-03-24 2007-10-01 Chipmos Technologies Inc Leadless semiconductor package with electroplated layer embedded in encapsualnt and the method for fabricating the same
TW200933853A (en) * 2008-01-24 2009-08-01 Chipmos Technologies Inc Wafer with bump structure and the forming method thereof
US20110101521A1 (en) * 2009-11-05 2011-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect with oxidation prevention layer

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998034285A1 (fr) * 1997-01-31 1998-08-06 Matsushita Electronics Corporation Element electroluminescent, dispositif electroluminescent a semiconducteur, et leur procede de production
TWI279887B (en) 2001-08-24 2007-04-21 Chipbond Technology Corp Manufacturing method of flip chip electronic device
JP4001112B2 (ja) * 2002-03-29 2007-10-31 松下電器産業株式会社 熱伝導性基板の製造方法
TWI233188B (en) * 2003-10-07 2005-05-21 United Microelectronics Corp Quad flat no-lead package structure and manufacturing method thereof
US6867072B1 (en) 2004-01-07 2005-03-15 Freescale Semiconductor, Inc. Flipchip QFN package and method therefor
JP4525079B2 (ja) * 2004-01-13 2010-08-18 住友ベークライト株式会社 熱硬化性液状封止樹脂組成物及びそれを用いた半導体装置
US8067823B2 (en) 2004-11-15 2011-11-29 Stats Chippac, Ltd. Chip scale package having flip chip interconnect on die paddle
US7880313B2 (en) * 2004-11-17 2011-02-01 Chippac, Inc. Semiconductor flip chip package having substantially non-collapsible spacer
TWI303854B (en) 2005-03-23 2008-12-01 Siliconware Precision Industries Co Ltd Flip-chip semiconductor package and method for fabricating the same
US7615851B2 (en) 2005-04-23 2009-11-10 Stats Chippac Ltd. Integrated circuit package system
TWI311358B (en) 2005-11-16 2009-06-21 Advanced Semiconductor Eng Flip-chip integrated circuit packaging method
US20080079149A1 (en) * 2006-09-28 2008-04-03 Harry Hedler Circuit board arrangement and method for producing a circuit board arrangement
US7790512B1 (en) * 2007-11-06 2010-09-07 Utac Thai Limited Molded leadframe substrate semiconductor package
US7923846B2 (en) * 2007-11-16 2011-04-12 Stats Chippac Ltd. Integrated circuit package-in-package system with wire-in-film encapsulant
US20090189296A1 (en) 2008-01-30 2009-07-30 Chipmos Technologies Inc. Flip chip quad flat non-leaded package structure and manufacturing method thereof and chip package structure
TWI398933B (zh) * 2008-03-05 2013-06-11 Advanced Optoelectronic Tech 積體電路元件之封裝結構及其製造方法
US8592995B2 (en) * 2009-07-02 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump
US8400784B2 (en) 2009-08-10 2013-03-19 Silergy Technology Flip chip package for monolithic switching regulator

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW530398B (en) * 2002-03-19 2003-05-01 Chipmos Technologies Inc Method for manufacturing bumps of chip scale package (CSP)
US20050077624A1 (en) * 2003-10-09 2005-04-14 Advanpack Solutions Pte. Ltd. Pillar structures
US20070001278A1 (en) * 2005-06-30 2007-01-04 Oseob Jeon Semiconductor die package and method for making the same
TW200737472A (en) * 2006-03-24 2007-10-01 Chipmos Technologies Inc Leadless semiconductor package with electroplated layer embedded in encapsualnt and the method for fabricating the same
TW200933853A (en) * 2008-01-24 2009-08-01 Chipmos Technologies Inc Wafer with bump structure and the forming method thereof
US20110101521A1 (en) * 2009-11-05 2011-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect with oxidation prevention layer

Also Published As

Publication number Publication date
CN102820276B (zh) 2016-05-11
TW201250885A (en) 2012-12-16
CN102820276A (zh) 2012-12-12
US8962395B2 (en) 2015-02-24
US20130280865A1 (en) 2013-10-24
US20120313234A1 (en) 2012-12-13

Similar Documents

Publication Publication Date Title
TWI550741B (zh) 四方扁平無接腳封裝及其製造方法
US11289409B2 (en) Method for fabricating carrier-free semiconductor package
US7772685B2 (en) Stacked semiconductor structure and fabrication method thereof
TWI495021B (zh) 半導體封裝結構的製造方法
TWI527175B (zh) 半導體封裝件、基板及其製造方法
US7772687B2 (en) Multiple electronic component containing substrate
US20100164091A1 (en) System-in-package packaging for minimizing bond wire contamination and yield loss
US8569885B2 (en) Stacked semiconductor packages and related methods
US20210202337A1 (en) Semiconductor device
JP2013115336A (ja) 半導体装置及びその製造方法
CN106463427B (zh) 半导体装置及其制造方法
KR20050105361A (ko) 솔더 범프와 골드 범프의 접합을 갖는 시스템 인 패키지및 그 제조방법
US20060214308A1 (en) Flip-chip semiconductor package and method for fabricating the same
US7642639B2 (en) COB type IC package to enhanced bondibility of bumps embedded in substrate and method for fabricating the same
JP2010263108A (ja) 半導体装置及びその製造方法
US20110298124A1 (en) Semiconductor Structure
US10854576B2 (en) Semiconductor device and manufacturing method thereof
US8058109B2 (en) Method for manufacturing a semiconductor structure
TWI394240B (zh) 免用凸塊之覆晶封裝構造及其中介板
TWI508243B (zh) 封裝結構及其製造方法
US6953711B2 (en) Flip chip on lead frame
JP2001007238A (ja) ウエハーレベルの集積回路装置のパッケージ方法
JP3703960B2 (ja) 半導体装置
TWI420626B (zh) 封裝結構與封裝製程
KR20240032287A (ko) 반도체 패키지