CN106409786A - 一种双向esd防护二极管的dfn封装结构及制造方法 - Google Patents

一种双向esd防护二极管的dfn封装结构及制造方法 Download PDF

Info

Publication number
CN106409786A
CN106409786A CN201611097226.3A CN201611097226A CN106409786A CN 106409786 A CN106409786 A CN 106409786A CN 201611097226 A CN201611097226 A CN 201611097226A CN 106409786 A CN106409786 A CN 106409786A
Authority
CN
China
Prior art keywords
chip
elargol
dfn
framework
plastic packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201611097226.3A
Other languages
English (en)
Inventor
薛维平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SHANGHAI CORE STONE MICRO-ELECTRONIC Co Ltd
Original Assignee
SHANGHAI CORE STONE MICRO-ELECTRONIC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHANGHAI CORE STONE MICRO-ELECTRONIC Co Ltd filed Critical SHANGHAI CORE STONE MICRO-ELECTRONIC Co Ltd
Priority to CN201611097226.3A priority Critical patent/CN106409786A/zh
Publication of CN106409786A publication Critical patent/CN106409786A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

常规双向ESD防护二极管的芯片电极一个从正面引出，一个从背面引出，DFN封装时，芯片背面和框架用银胶连接，正面打金属线连接，常规结构的局限性是芯片尺寸要小于框架尺寸，芯片需要减薄至150微米以下，且背面需要金属化，此发明所使用的双向ESD防护二极管的芯片，其两个电极可以都从正面引出，两个电极都通过银胶和框架连接，芯片只需要使用单晶片制造，不再用外延片，降低成本；芯片厚度只需做到200微米，降低碎片率；背面无需金属化，减少工艺；芯片尺寸可以是原来的1.5‑2倍，给超低电容芯片、更强抗浪涌能力芯片提供了更多的设计空间。

Description

一种双向ESD防护二极管的DFN封装结构及制造方法
技术领域
本发明属于一种DFN封装的制造，适用于双向ESD防护二极管芯片的DFN封装。
背景技术
半导体电路集成度不断提高，ESD防护二极管的封装尺寸也随之变小，从原来的SOD523、SOD723到SOD923，再到DFN1006、DFN0603、 DFN0201，乃至将来的CSP封装，封装尺寸不断在缩小，但是对ESD防护二极管的性能要求却越来越高，抗浪涌能力，低电容，低电压等等参数标准不断提升，怎么样在更小的芯片上实现更强大的功能逐渐成为难题，由于最开始的ESD防护二极管是用在SOD523，SOD723封装上的，发展到后来，DFN封装仍然延续了SOD封装的工艺，即背面银胶连接，正面打金属线连接，目的是不改变最开始芯片的设计。随着封装尺寸变的越来越小，当到达DFN0603封装时，打线工艺已经占去了1/4的封装体高度空间，产生很多工艺上的难题，芯片厚度需要做到小于100微米，芯片尺寸也要做到小于200微米×200微米，芯片的成品率下降，封装的成品率同时也在下降，本发明的封装结构，两个芯片电极可以都是从正面引出，两个电极都通过银胶和框架连接，抛弃了正面打线工艺，芯片厚度只需做到200微米，而且省去了背面金属化，此结构提升了芯片成品率，提升了封装成品率，减少了芯片制造工艺，最重要的是芯片尺寸可以是原来的1.5-2倍，为超低电容产品、更强抗浪涌能力产品提供更大的芯片设计空间。
发明内容
1、一种双向ESD防护二极管的DFN封装结构，其结构包括：DFN框架上（105）连接银胶（104），银胶连接芯片电极（103），两个芯片电极都是从芯片（102）正面引出，芯片厚度小于200微米。
2、一种双向ESD防护二极管的DFN封装的制造方法，其方法包括：
A、将晶圆芯片通过划片切割成单个芯片，然后通过倒片使芯片正面与蓝膜粘接；
B、使用点胶机和固晶机，将芯片与框架通过银胶连接，然后固化银胶；
C、使用塑封机将载有芯片的框架塑封；
D、将塑封后裸露在外部的框架表面通过电镀，镀上银或者金；
E、将整个电镀好的塑封模块切割成单个的DFN封装体。
附图说明
图1是双向ESD防护二极管的DFN封装的截面图。
编号说明
101：DFN封装体；
102：双向ESD防护二极管芯片，厚度小于200微米；
103：芯片电极，金属，一般情况下是铝或者银，不局限于铝和银；
104：银胶，导电的胶状物，内含有银粉成分，高温固化；
105：框架，金属，一般情况下是铜，不局限于铜。
具体实施方式
1．芯片划片及倒片，芯片背面贴蓝膜，用划片机将整个的晶圆芯片，切割成单个芯片，切割完成后，用倒片机，将蓝膜上的芯片倒到另外一张蓝膜上，此时芯片的正面与蓝膜接触。
2．芯片与框架连接，用点胶机将银胶点到框架上，固晶机将单个芯片从蓝膜上取下，放在银胶上，芯片电极和银胶连接，进入固化炉固化。
3．塑封，将载有芯片的框架，放入塑封机进行塑封。
4．电镀，将漏在外部的框架电镀，一般镀银或者金。
5．塑封切割，将整个塑封模块切割成单个的DFN封装体。
6．测试包装。
通过上述实施例阐述了本发明，同时也可以采用其它实施例实现本发明，本发明不局限于上述具体实施例，因此本发明由所附权利要求范围限定。

Claims (2)

1.一种双向ESD防护二极管的DFN封装结构，其结构包括：DFN封装体（101）的框架（105）上连接银胶（104），银胶连接芯片电极（103），两个芯片电极都是从芯片（102）正面引出，芯片厚度小于200微米。
2.一种双向ESD防护二极管的DFN封装的制造方法，其方法包括：
A、将晶圆芯片通过划片切割成单个芯片，然后通过倒片使芯片正面与蓝膜粘接；
B、使用点胶机和固晶机，将芯片与框架通过银胶连接，然后固化银胶；
C、使用塑封机将载有芯片的框架塑封；
D、将塑封后裸露在外部的框架表面通过电镀，镀上银或者金；
E、将整个电镀好的塑封模块切割成单个的DFN封装体。
CN201611097226.3A 2016-12-02 2016-12-02 一种双向esd防护二极管的dfn封装结构及制造方法 Pending CN106409786A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201611097226.3A CN106409786A (zh) 2016-12-02 2016-12-02 一种双向esd防护二极管的dfn封装结构及制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611097226.3A CN106409786A (zh) 2016-12-02 2016-12-02 一种双向esd防护二极管的dfn封装结构及制造方法

Publications (1)

Publication Number Publication Date
CN106409786A true CN106409786A (zh) 2017-02-15

Family

ID=58083730

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611097226.3A Pending CN106409786A (zh) 2016-12-02 2016-12-02 一种双向esd防护二极管的dfn封装结构及制造方法

Country Status (1)

Country Link
CN (1) CN106409786A (zh)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101764114A (zh) * 2009-12-30 2010-06-30 上海凯虹电子有限公司 一种倒装式封装结构及其制作方法
CN102820276A (zh) * 2011-06-10 2012-12-12 南茂科技股份有限公司 四方扁平无接脚封装及其制造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101764114A (zh) * 2009-12-30 2010-06-30 上海凯虹电子有限公司 一种倒装式封装结构及其制作方法
CN102820276A (zh) * 2011-06-10 2012-12-12 南茂科技股份有限公司 四方扁平无接脚封装及其制造方法

Similar Documents

Publication Publication Date Title
EP2033220B1 (en) Stack die packages
CN101017786B (zh) 半导体封装的制造方法
US20070278701A1 (en) Semiconductor package and method for fabricating the same
TW563232B (en) Chip scale package and method of fabricating the same
CN107910307A (zh) 一种半导体芯片的封装结构及其封装方法
US9768146B2 (en) Battery protection package and process of making the same
US20130069223A1 (en) Flash memory card without a substrate and its fabrication method
JP2003174131A (ja) 樹脂封止型半導体装置及びその製造方法
CN102263077A (zh) 一种双扁平无载体无引脚的ic芯片封装件
US20130009294A1 (en) Multi-chip package having leaderframe-type contact fingers
CN102403236A (zh) 芯片外露的半导体器件及其生产方法
CN105990298A (zh) 一种芯片封装结构及其制备方法
CN104916599A (zh) 芯片封装方法和芯片封装结构
CN206250175U (zh) 一种双向esd防护二极管的dfn封装结构
CN106409786A (zh) 一种双向esd防护二极管的dfn封装结构及制造方法
TW200828525A (en) Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product
CN107611097A (zh) 晶圆级芯片封装结构及其制备方法
CN210136868U (zh) 一种晶圆键合堆叠芯片的封装结构
CN203589000U (zh) 一种基于无框架csp封装背面植球塑封封装件
CN202196776U (zh) 一种扁平无载体无引线引脚外露封装件
CN207250484U (zh) 晶圆级芯片封装结构
CN103107098B (zh) 方形扁平无引脚的封装方法及其封装结构
CN104112811B (zh) 一种led的封装方法
CN104952736A (zh) 四方平面无引脚的封装结构及其方法
CN115985783B (zh) 一种mosfet芯片的封装结构和工艺

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20170215