CN104916599A - 芯片封装方法和芯片封装结构 - Google Patents

芯片封装方法和芯片封装结构 Download PDF

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CN104916599A
CN104916599A CN201510283826.8A CN201510283826A CN104916599A CN 104916599 A CN104916599 A CN 104916599A CN 201510283826 A CN201510283826 A CN 201510283826A CN 104916599 A CN104916599 A CN 104916599A
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chip
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叶佳明
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Hangzhou Silergy Semiconductor Technology Ltd
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Abstract

本申请提供了芯片封装方法以及芯片封装结构，所述方法为使芯片和位于芯片周围的塑封料来形成具有更大面积的封装单元，再在所述封装单元上形成重布线层以将芯片表面的输入输出端子引出重新排布，最后再将所述重布线层通过外部电连接体与引线框架或印刷电路板电连接。这样的封装方法和封装结构适应于具有高密度的输入输出端子芯片的封装，且封装成本低，封装可靠性高。

Description

芯片封装方法和芯片封装结构
技术领域
本发明涉及芯片封装技术领域，尤其涉及一种芯片封装方法和芯片封装结构。
背景技术
传统的芯片封装方法为先切割晶圆，以将芯片从晶圆上切割出来，形成一颗颗独立的芯片，然后将每一颗芯片贴装于引线框架上，并将芯片上的输入输出焊盘通过金属引线电连接到引线框架上，最后再塑封形成芯片封装体。这种通过引线键合的封装方式，由于引脚排布与芯片的周围，而引脚之间的间距对封装体来说又不能小于限定的值，因此不适应于具有高密度输入输出(I/O)端子的芯片的封装。通过增加芯片的面积可以增加位于芯片周围的引脚数量，以适应具有更多I/O端子芯片的封装，但这种方式却会增加芯片的制造成本。
基于上述问题的存在，芯片级封装(CSP封装)技术、倒装封装技术应运而生，然而由于位于芯片表面的焊球或导电凸块具有一定的尺寸(通常会大于焊盘的尺寸)，当芯片表面上的I/O端子数量越来越多时，这些I/O端子的焊盘与焊盘之间的间距也会越来越小，从而无法在焊盘上制作焊球或导电凸块来实现与外部电路的电连接。因此，CSP封装技术和倒装封装技术也同样无法满足具有超高密度I/O端子的芯片的封装需求。
发明内容
有鉴于此，本发明提供一种新的芯片封装方法和芯片封装结构，以适合具有超高密度I/O端子的芯片的封装需求。
一种芯片封装方法，包括步骤：
将芯片从晶圆上切割下来，所述芯片的有源面上设置输入输出端子的焊盘；
将所述芯片以有源面朝上的方式排布贴装于一平盘上；
利用塑封工艺在所述芯片之间填充塑封材料，使每一所述芯片与其周围的所述塑封材料形成一个封装单元；
在所述封装单元上形成具有开口的绝缘层，每一所述开口至少裸露出每一个所述焊盘的一部分；
在所述绝缘层之上形成重布线层，重布线层与裸露出的所述焊盘相接触，以重新布置所述输入输出端子的位置；
将所述重布线层通过外部电连接体与引线框架或印刷电路板电连接。
优选的，所述的封装方法还包括在将所述重布线层通过外部电连接体与引线框架或印刷电路板电连接之前，在所述重布线层之上形成所述外部电连接体，并切割填充于所述芯片之间的塑封材料，以及将每一个所述封装单元从所述平盘上剥离下来。
优选的，所述外部连电接体为焊球，被剥离下来的所述封装单元上的重布线层通过所述焊球与所述印刷电路板电连接。
优选的，在形成焊球之前还包括在所述重布线层之上形成保护层，所述保护层裸露出部分所述重布线层，以在裸露的所述重布线层处形成所述焊球。
优选的，所述外部电连体为导电凸块，被剥离下来的所述封装单元上的重布线层通过所述导电凸块与所述引线框架电连接。
优选的，所述外部电连接体为金属引线，所述重布线层通过所述金属引线与所述引线框架电连接，所述方法还包括在形成所述重布线层之后和将所述重布线层通过所述金属引线与所述引线框架电连接之前，先切割填充于所述芯片之间的塑封材料，并将每一个所述封装单元从所述平盘上剥离下来。
优选的，所述的封装方法还包括利用塑封工艺，使塑封材料囊封所述封装单元和所述引线框架。
优选的，相邻的两个所述输入输出端子之间的间距小于120微米。
一种芯片封装结构，包括：
芯片，具有有源面，所述有源面上设置有输入输出端子的焊盘；
位于所述芯片周围的塑封材料；
绝缘层，至少覆盖所述有源面，并具有开口，每一个所述开口至少裸露出每一个所述焊盘的一部分；
重布线层，位于所述绝缘层之上，并与裸露出的所述焊盘相接触，以重新布置所述输入输出端子的位置。
优选的，所述的封装结构还包括一端与所述重布线层电连接，另一端与引线框架或印刷电路板电连接的外部电连接体。
由上可见，在本申请提供的芯片封装方法及芯片封装结构中，使芯片和位于芯片周围的塑封料来形成具有更大面积的封装单元，再在所述封装单元上形成重布线层以将芯片表面的输入输出端子引出重新排布，最后再将所述重布线层通过外部电连接体与引线框架或印刷电路板电连接。这样的封装方法和封装结构适应于具有高密度的输入输出端子芯片的封装，且封装成本低，封装可靠性高。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1为带芯片的晶圆结构示意图；
图2为芯片排布贴装与平盘之上的结果示意图；
图3排布与平盘上的芯片在塑封工艺之后结构的切面视图；
图4为图2中所示的封装单元的放大图；
图5为将芯片有源面上的I/O端子引到整个封装单元的表面上进行重排布封装结构的俯视图；
图6为图5所示的将芯片有源面上的I/O端子引到整个封装单元的表面上进行重排布封装结构的截面图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的组成部分采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本发明的许多特定的细节，例如每个组成部分的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
本申请提供了一种芯片封装方法，其封装芯片的工艺流程主要包括以下步骤：
步骤1：切割晶圆，以将芯片从晶圆上切割下来，形成彼此分离的芯片。
图1示出了包含芯片的晶圆结构，晶圆1通常为硅片，其上已经制作好了电子器件或电路，每一块晶圆上包括很多块芯片2，这些芯片具有有源面，所述有源面上设置了多个输入输出端子(I/O端子)的焊盘(图1中暂未示出)，这些I/O端子可以设置得非常密，例如相邻的两个I/O端子之间的间距可小于120微米，具体可以为100微米、80微米、50微米等等。I/O端子设置得密，有利于提高芯片的集成度。
步骤2：在切割完晶圆后，将彼此隔开的所述芯片以有源面超上的方式排布贴装于一个平盘上。
图2为芯片排布贴装于平盘之上的示意图，各个芯片2以一定的间距排布放置于平板3之上，芯片与芯片之间的间距例如可以为芯片宽度(或长度)的1/4～3/4等。芯片2的有源面朝上，背面(非有源面)贴装于平板3之上，从而将各个芯片2以一定的间距固定在平盘上。平板3可以为容易从塑封材料上剥离开的金属板，或者为绷直于硬圈上的薄膜(例如薄膜胶)。
步骤3：在进行完步骤2之后，利用塑封工艺在各个芯片之间填充塑封材料，使每一所述芯片2与其周围的所述塑封材料形成一个封装单元。
利用塑封工艺形成后的封装结构如图2所示，塑封材料4填充于芯片2之间，其形成的具体过程为：将塑封模具放置于芯片2上，即塑封模具的底面与芯片2的有源面交界，芯片2被塑封模具覆盖住，然后在塑封模具与平盘之间注入塑封材料4，使塑封材料4填充满芯片2之间的间隙，即芯片2的周围均为塑封材料。需要注意的是，塑封工艺后，塑封材料4固化所形成的塑封体的上表面一般不会高于芯片2的有源面，下表面贴在平盘之上，各个芯片2嵌在塑封材料4所形成的塑封体之中。这里塑封材料可以为环氧树脂等最终容易从平盘3上脱离下来的绝缘材料。每一块芯片2在进行塑封工艺后，均被塑封材料4所包围，从而可使每一块芯片2与其周围的塑封料4构成一个塑封单元5，在每一个塑封单元中，塑封材料4均位于芯片2的周围，并与芯片2的侧壁(与有源面垂直的面)相接触。优选的，如图3所示，其为塑封工艺后，塑封材料4和芯片2构成的结构的切面视图，从图中可以清楚的看出，且塑封材料4形成的塑封体的上表面与芯片2的有源面为在同一个平面上。
图4为图2中所示的封装单元5的放大图，从图中可以看出，在封装单元5中，芯片2被塑封材料4所包围，且塑封材料4所形成的塑封体的上表面与芯片的有源面齐平，则这样的封装单元的面积比芯片2的面积大量很多，若将芯片的输入输出端子在整个封装单元的表面进行重排布再与外部电路电连接，便可以允许芯片2具有更高密度的I/O端子，即例如相邻的两个I/O端子之间的间距(即图4中相邻的两个所述焊盘6的中心间距A)可小于120微米，具体可以为100微米、80微米、50微米等等。I/O端子设置得密，有利于提高芯片的集成度。
步骤5：在所述封装单元上形成具有开口的绝缘层，每一所述开口至少裸露出每一个所述焊盘的一部分。
步骤6：在所述绝缘层之上形成重布线层，重布线层与裸露出的所述焊盘相接触，以重新布置所述输入输出端子的位置。
步骤7：将所述重布线层通过外部电连接与引线框架或印刷电路板电连接。
图5为将芯片有源面上的I/O端子引到整个封装单元的表面上进行重排布封装结构的俯视图，图6为图5所示的将芯片有源面上的I/O端子引到整个封装单元的表面上进行重排布封装结构的截面图。
如图5和图6所示，在步骤4完成之后，在所有的封装单元的表面形成一绝缘层7，绝缘层7可以只位于每一个封装单元中的芯片上方，也可以延伸至每一个封装单元的塑封料上去。此外，绝缘层还具有开口，以至少裸露出每一个焊盘6的一部分，即每一个焊盘6的至少一部分均被均层裸露在外。绝缘层7可以选择为二氧化硅、或二氧化硅与氮化硅的叠层等。
在形成完绝缘层之后，再在绝缘层之上形成重布线层，重布线层为一个图案化的金属导电层，如5中的重布线层8所示，该层被图案化成多个隔离开的导电迹线，每一个导电迹线与一个裸露出的所述焊盘6相接触，从而将芯片2的I/O端子引到了所述导电迹线上来，且导电迹线可延伸至塑封材料4形成的塑封体表面上，从而可将I/O端子引到塑封材料4形成的塑封体的表面上，而不局限于只位于芯片2上，这样在将重布线层与外部电连接体9与引线框架或印刷电路板电连接时，外部电连接体9在封装单元上的排布区域的面积增大(包括芯片的面积和塑封材料所形成的塑封体的面积)，从而可以在封装单元上引出更多的I/O端子。由此可见，通过这种图案化重布线层与裸露出的所述焊盘相接触，以重新布置所述输入输出端子的位置，可有效的增加I/O端子的排布区域，使芯片2上的I/O端子的排列间距可以很密。
在本实施例中，外部电连接体可以为焊球，本申请的封装方法还进一步包括在进行步骤7之前，在所述重布线层之上形成所述外部电连接体9，然而切割填充于所述芯片2之间的塑封材料4，再将每一个所述封装单元5从所述平盘3上剥离下来，以形成一个个彼此隔离的封装单元。之后再进行步骤7，使每一个封装单元上的外部电连体与引线框架或印刷电路板电连接，从而实现封装单元中芯片上的I/O端子与外部的电连接。
具体的外部电连接体可以为焊球，如锡焊球等，被剥离下来的所述封装单元上的重布线层通过所述焊球与所述印刷电路板电连接。作为一种优选的实现方案，在形成焊球之前还可在所述重布线层之上形成保护层(图中未示出)，所述保护层裸露出部分所述重布线层，以在裸露的所述重布线层处形成所述焊球。这样便可保证焊球与焊球之间的隔离，以防短路。
另外，外部电连接体还可以为导电凸块，如铜块等，被剥离下来的所述封装单元上的重布线层通过所述导电凸块与所述引线框架电连接。在封装单元与引线框架电连接后，利用塑封工艺，使塑封材料囊封所述封装单元和所述引线框架。囊封封是指不完全包封，即引线框架的引脚部分裸露在塑封材料外面，以与外部电路电连接。
在另一些实施例中，外部电连接体还可以为金属引线，所述重布线层通过所述金属引线与所述引线框架电连接。因此，本申请的封装方法还包括在形成所述重布线层之后和将所述重布线层通过所述金属引线与所述引线框架电连接之前，先切割填充于所述芯片之间的塑封材料，并将每一个所述封装单元从所述平盘上剥离下来。在将封装单元剥离下来后，再使金属引线的一端与封装单元上的重布线层电连接，另一端与引线框架电连接，具体的为与引线框架上的引脚电连接。在所述重布线层通过所述金属引线与所述引线框架电连接之后，利用塑封工艺，使塑封材料囊封所述封装单元和所述引线框架。囊封封是指不完全包封，即引线框架的引脚部分裸露在塑封材料外面，以与外部电路电连接。
此外，本申请还提供一种芯片封装结构，如图6所示，所述芯片封装结构主要包括芯片2、塑封材料4、绝缘层7、重布线层8，此外还包括一端与重布线层电连接，另一端与引线框架或印刷电路板电连接的外部电连接体9。
芯片2具有有源面，且有源面上设置有输入输出端子的焊盘6，这输入输出端子之间的间距一般小于120微米，例如可以为100微米、80微米、50微米等。由于I/O端子之间的间距较小，从而无法直接在焊盘6上放置外部电连接体9。
塑封材料4位于芯片2的周围而与芯片2的侧壁(与有源面垂直的面)相接触，且塑封材料形成的塑封体的表面与芯片的有源面齐平，当然也可以稍微低于所述有源面的表面。则芯片2与位于其周围的塑封料形成的封装单元面积比芯片2的面积大量很多，若将芯片的输入输出端子在整个封装单元的表面进行重排布再与外部电路电连接，便可以允许芯片2具有更高密度的I/O端子。
绝缘层6至少覆盖所述有源面，并具有开口，每一个所述开口至少裸露出每一个所述焊盘6的一部分。在一个实施例中，绝缘层可以延伸至塑封材料4上。绝缘层可以选择为二氧化硅等材料形成。
重布线层8，位于所述绝缘层之上，并与裸露出的所述焊盘6相接触，以重新布置所述输入输出端子的位置。其中，重布线层8可延伸至塑封材料4形成的塑封体表面上，有利于增加外部电连接体9的排布面积，从而增加了I/O端子的排布面积，使芯片2允许有更加密的I/O端子。外部电连接体可以选自焊球、导电凸块、金属引线等中的一种。
由上可见，在本申请提供的芯片封装方法及芯片封装结构中，使芯片和位于芯片周围的塑封料来形成具有更大面积的封装单元，再在所述封装单元上形成重布线层以将芯片表面的输入输出端子引出重新排布，最后再将所述重布线层通过外部电连接体与引线框架或印刷电路板电连接。这样的封装方法和封装结构适应于具有高密度的输入输出端子芯片的封装，且封装成本低，封装可靠性高。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (10)

1.一种芯片封装方法，包括步骤：
将芯片从晶圆上切割下来，所述芯片的有源面上设置输入输出端子的焊盘；
将所述芯片以有源面朝上的方式排布贴装于一平盘上；
利用塑封工艺在所述芯片之间填充塑封材料，使每一所述芯片与其周围的所述塑封材料形成一个封装单元；
在所述封装单元上形成具有开口的绝缘层，每一所述开口至少裸露出每一个所述焊盘的一部分；
在所述绝缘层之上形成重布线层，重布线层与裸露出的所述焊盘相接触，以重新布置所述输入输出端子的位置；
将所述重布线层通过外部电连接体与引线框架或印刷电路板电连接。
2.根据权利要求1所述的封装方法，其特征在于，还包括在将所述重布线层通过外部电连接体与引线框架或印刷电路板电连接之前，在所述重布线层之上形成所述外部电连接体，并切割填充于所述芯片之间的塑封材料，以及将每一个所述封装单元从所述平盘上剥离下来。
3.根据权利要求2所述的封装方法，其特征在于，所述外部连电接体为焊球，被剥离下来的所述封装单元上的重布线层通过所述焊球与所述印刷电路板电连接。
4.根据权利要求3所述的封装方法，其特征在于，在形成焊球之前还包括在所述重布线层之上形成保护层，所述保护层裸露出部分所述重布线层，以在裸露的所述重布线层处形成所述焊球。
5.根据权利要求2所述的封装方法，其特征在于，所述外部电连体为导电凸块，被剥离下来的所述封装单元上的重布线层通过所述导电凸块与所述引线框架电连接。
6.根据权利要求1所述的封装方法，其特征在于，所述外部电连接体为金属引线，所述重布线层通过所述金属引线与所述引线框架电连接，所述方法还包括在形成所述重布线层之后和将所述重布线层通过所述金属引线与所述引线框架电连接之前，先切割填充于所述芯片之间的塑封材料，并将每一个所述封装单元从所述平盘上剥离下来。
7.根据权利要求6所述的封装方法，其特征在于，还包括利用塑封工艺，使塑封材料囊封所述封装单元和所述引线框架。
8.根据权利要求1所述的封装方法，其特征在于，相邻的两个所述输入输出端子之间的间距小于120微米。
9.一种如权利要求芯片封装结构，包括：
芯片，具有有源面，所述有源面上设置有输入输出端子的焊盘；
位于所述芯片周围的塑封材料，所述芯片与所述塑封材料构成封装单元；
绝缘层，位于所述封装单元之上，并具有开口，每一个所述开口至少裸露出每一个所述焊盘的一部分；
重布线层，位于所述绝缘层之上，并与裸露出的所述焊盘相接触，以重新布置所述输入输出端子的位置。
10.根据权利要求9所述的封装结构，其特征在于，还包括一端与所述重布线层电连接，另一端与引线框架或印刷电路板电连接的外部电连接体。
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