TWI417039B - 增進電磁遮蔽層接地連接之半導體封裝構造 - Google Patents

增進電磁遮蔽層接地連接之半導體封裝構造 Download PDF

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TWI417039B
TWI417039B TW100115356A TW100115356A TWI417039B TW I417039 B TWI417039 B TW I417039B TW 100115356 A TW100115356 A TW 100115356A TW 100115356 A TW100115356 A TW 100115356A TW I417039 B TWI417039 B TW I417039B
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shielding layer
electromagnetic shielding
substrate
semiconductor package
wire
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TW201247092A (en
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Shou Chian Hsu
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Powertech Technology Inc
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Description

增進電磁遮蔽層接地連接之半導體封裝構造
本發明係有關於半導體裝置，特別係有關於一種增進電磁遮蔽層接地連接之半導體封裝構造。
按，半導體晶片是一種微小型電子零件，即使經過封裝之後，仍有可能受到電磁干擾(EMI)而導致晶片運算異常或是電性功能失效，特別是晶片的運算頻率越高時越容易受到干擾。故依已知的傳統作法之其中之一，於其內密封有晶片的封膠體之外表面覆蓋上一電磁遮蔽層(或可稱為射頻遮蔽層)。然而，電磁遮蔽層必須有效接地連接才能發揮良好的遮蔽效果。又，封膠體本身為電性絕緣材料，僅能利用基板之特殊接地結構與特殊封裝製程方可達成電磁遮蔽層之接地連接，導致封裝成本的提高。
美國專利US 7,342,303 B1揭示一種使電磁遮蔽層接地連接之半導體封裝技術，在封裝製程中需要多道半切割操作，基板於切割道尚需要預先製作可被半切之鍍通孔。第1圖所示者為依該習知方法製得之半導體封裝構造100，包含一具有特殊結構之基板110，在側邊設有鍍通孔114，晶片120設置於基板110上，利用銲線160電性連接該晶片120至該基板110，再以一封膠體140密封該晶片120。封膠體140之表面(如第1圖所示之頂面141與切割側面142)形成有一導電塗層，作為電磁遮蔽層150。該基板110之下方則設有複數個銲球170。在形成該電磁遮蔽層150之前，必須先執行一預切割步驟，切穿該封膠體140以及切到該基板110之一部分，以形成該封膠體140之切割側面142與該基板110之上切緣113A，且第一次切割寬度大於第二次切割寬度使該鍍通孔114露出，方能連接該電磁遮蔽層150。在形成該電磁遮蔽層150之後，再以第二次切割步驟單體化分離該半導體封裝構造100。因此，第一次切割基板的深度如果不夠便會影響該電磁遮蔽層150之接地連接效果，然而只切到基板預定深度的切割操作需要相當高的精準度與基板平坦度。此外，如單純以基板側面外露的線路切斷端連接該電磁遮蔽層150，則因線路切斷端過小容易會有接地連接失敗的問題發生。
有鑒於此，本發明之主要目的係在於提供一種增進電磁遮蔽層接地連接之半導體封裝構造，不需要半切基板之多次切割操作，以達到製程簡化之功效。
本發明之次一目的係在於提供一種增進電磁遮蔽層接地連接之半導體封裝構造，使基板結構簡化或是不需要設置與電磁遮蔽層接地連接之特殊基板結構。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種增進電磁遮蔽層接地連接之半導體封裝構造包含一基板、一晶片、一銲線殘留部份、一封膠體以及一電磁遮蔽層。該基板係具有一上表面以及複數個切緣，於該上表面之周邊係設有一接地墊。該晶片係設置於該基板上。該銲線殘留部份係包含一打線結球銲點，該打線結球銲點係設置於該接地墊上。該封膠體係形成於該基板之該上表面上，以密封該晶片與該銲線殘留部份，該封膠體係具有一頂面以及複數個切割側面，該銲線殘留部份係具有一顯露於該切割側面之金屬切面。該電磁遮蔽層係形成於該封膠體之該頂面與該些切割側面，並覆蓋連接至該銲線殘留部份之該金屬切面。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述的半導體封裝構造中，該打線結球銲點係可為非完整，而使該金屬切面位於該打線結球銲點之外側。
在前述的半導體封裝構造中，該接地墊係可延伸至該基板之鄰近切緣並被該電磁遮蔽層所覆蓋連接。
在前述的半導體封裝構造中，該銲線殘留部份係可更包含一殘留線段，係由該打線結球銲點拉出並截斷於與該封膠體相鄰之切割側面。
在前述的半導體封裝構造中，該電磁遮蔽層係可更延伸覆蓋至該基板之該些切緣。
在前述的半導體封裝構造中，該封膠體之該些切割側面係可與該些切緣垂直向切齊。
在前述的半導體封裝構造中，該封膠體之該些切割側面係可與該些切緣傾斜地切齊。
在前述的半導體封裝構造中，該基板之該上表面係可更設有複數個接指，該基板內係具有一線路，係連接至少一之該些接指至該接地墊，該半導體封裝構造另包含複數個完整銲線，其兩端係分別連接該晶片之複數個銲墊與該些接指，並且該封膠體係更密封該些完整銲線。
在前述的半導體封裝構造中，可另包含複數個銲球，係設於該基板之一下表面。
在前述的半導體封裝構造中，該些銲球係可包含一殘留銲料，係緊鄰該些切緣之其中之一並被該電磁遮蔽層連接。
由以上技術方案可以看出，本發明之增進電磁遮蔽層接地連接之半導體封裝構造，具有以下優點與功效：
一、可藉由在基板上形成之一銲線殘留部份與一形成於封膠體表面之電磁遮蔽層的連接關係作為其中之一技術手段，電磁遮蔽層覆蓋連接至該銲線殘留部份之金屬切面，不需要半切基板之多次切割操作，以達到製程簡化之功效。
二、可藉由在基板上形成之一銲線殘留部份與一形成於封膠體表面之電磁遮蔽層的連接關係作為其中之一技術手段，電磁遮蔽層覆蓋連接至該銲線殘留部份之金屬切面，使基板結構簡化或是不需要設置與電磁遮蔽層接地連接之特殊基板結構。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明之第一具體實施例，一種增進電磁遮蔽層接地連接之半導體封裝構造舉例說明於第2圖之截面示意圖以及第3A至3G圖於製造過程中各步驟形成元件之截面示意圖。該半導體封裝構造200係主要包含一基板210、一晶片220、一銲線殘留部份230、一封膠體240以及一電磁遮蔽層250。
如第2圖所示，該基板210係具有一上表面211、一下表面212以及複數個切緣213，於該上表面211之周邊係設有一接地墊214。該些切緣213係位於該上表面211與該下表面212之間的側緣並以切割形成。通常該基板210係為適用於半導體封裝之印刷電路板或軟性電路板，用以承載與電性連接半導體晶片，可具有單層或是多層的線路結構。其中，該上表面211係為晶片設置表面。在本實施例中，該晶片220與該基板210之電性連接方式係為打線連接(wire-bonding connection)。除了該接地墊214，該上表面211係更設置有複數個接指215，其中至少一接指215係經由該基板210內之一線路216連接至該接地墊214。
該晶片220係設置於該基板210上。可利用一黏晶材料，例如熱固性樹脂，黏著該晶片220之背面至該基板210之該上表面211。該晶片220係為由一半導體晶圓切割出之晶粒，內有各式積體電路或光主動元件，例如特殊應用積體電路(ASIC)、記憶體、或邏輯元件。此外，該基板210上不限於設置一個晶片，亦可設置更多相同或不同功能、尺寸的晶片，以達到多晶片封裝。在本實施例中，該晶片220之主動面係設有複數個銲墊221，可為平墊狀或是凸出狀。而該半導體封裝構造200另包含複數個完整銲線260，其兩端係分別連接該晶片220之該些銲墊221與該些接指215，並且該些完整銲線260係被該封膠體240密封。
如第2與3C圖所示，該銲線殘留部份230係包含一打線結球銲點232，該打線結球銲點232係設置於該接地墊214上。該打線結球銲點232係為一銲線在打線開始的接合點，通常稱其為球結合點(ball bond)，但實際上非球狀，而是依銲嘴的形狀並壓合形成，並且在該接地墊214上接合面積大於銲線的線截面圓形面積。該打線結球銲點232係可為完整銲點或是非完整銲點，在本實施例中，該打線結球銲點232係為非完整銲點。而「銲線殘留部份」表示為非完整的銲線，即一完整銲線中至少包含在打線結束尾端之部位係不形成於該半導體封裝構造200內。
再如第2圖所示，該封膠體240係形成於該基板210之該上表面211上，以密封該晶片220與該銲線殘留部份230。該封膠體240係可由轉移模注或是壓縮模封等方法形成。該封膠體240之材質係可為包含無機填充材與色料之電絕緣性熱固性樹脂。該封膠體240係具有一頂面241以及複數個切割側面242。在本實施例中，該封膠體240之該些切割側面242係可與該些切緣213垂直向切齊。特別的是，該銲線殘留部份230係具有一顯露於該切割側面242之金屬切面231。
該電磁遮蔽層250係形成於該封膠體240之該頂面241與該些切割側面242，即沿著該封膠體240之外形輪廓而形成，並覆蓋連接至該銲線殘留部份230之該金屬切面231。因此，該電磁遮蔽層250不是直接與該基板210接地連接，該基板210不需要特別製造位在切割道供接地連接之鍍通孔或線路。該電磁遮蔽層250係提供該晶片220之電磁遮蔽，其材質可為金屬，其形成方法可利用濺鍍、蒸鍍、化學鍍、物理氣相沉積、印刷或噴塗等方式。較佳地，該打線結球銲點232係可為非完整，如第3C圖所示，該打線結球銲點232於製程中是完整的，但經切割後為非完整(如第3F圖所示)，而使該金屬切面231位於該打線結球銲點232之外側，能提供被該打線結球銲點232覆蓋連接之較大面積。尤佳地，如第2圖所示，該接地墊214係可延伸至該基板210之鄰近切緣213並被該電磁遮蔽層250所覆蓋連接，以確保該電磁遮蔽層250之接地連接。在本實施例中，該電磁遮蔽層250係可更延伸覆蓋至該基板210之該些切緣213，以避免該基板210之核心層外露並增進側向的電磁遮蔽效果。此外，該半導體封裝構造200可另包含複數個銲球270，係設於該基板210之該下表面212，作為該半導體封裝構造200之外接端子。
第3A至3G圖繪示該半導體封裝構造200之製造過程，用以說明該半導體封裝構造200不需要半切基板之多次切割操作，以達到製程簡化之功效。
首先，如第3A與4圖所示，提供該基板210，其係複數個型態形成於一基板條。基板210與基板210之間係定義有一切割線201。該基板210的接指215中接地作用之接指係藉由一線路216連接至該接地墊214，而該接地墊214係可超過該切割線201或不超過。在本實施例中，如第4圖所示，該接地墊214係可超過該切割線201。第3B圖係為在黏晶步驟中，至少一之該晶片220設置於該基板210上但不超過該切割線201。第3C圖係為在打線步驟中，利用打線形成之該些銲線260連接該晶片220之銲墊221與該基板210之接指215；同時，在本實施例中，亦利用打線方式在該接地墊214上形成打線結球銲點232，該打線結球銲點232的尺寸可大於或等於該些銲線260之結球銲點，在較佳的結構中，該打線結球銲點232的尺寸是大於該些銲線260之結球銲點，可利用多銲點堆疊接合或是選用較粗的銲線構成，以確保該打線結球銲點232超過該切割線201。
第3D圖係為在模封步驟中之元件截面圖，在該基板210上形成該封膠體240。在本實施例中，該模封步驟係模封陣列製程(MAP)，該封膠體240係連續覆蓋多個基板及其之間的切割線201，以密封該晶片220、該打線結球銲點232以及該些銲線260。第3E圖係為在植球步驟中之元件截面圖，利用球放置加上回焊的方式或是銲料印刷與回焊的方式設置該些銲球270於該基板210之下表面212。第3F圖係為在單體化切割步驟中之元件截面圖，利用刀具沿著上述切割線201切穿該封膠體240與該基板210，使該基板210分離。在單體化切割步驟中除了形成該封膠體240之該些切割側面242與該基板之該些切緣213，同時切過該打線結球銲點232，以構成具有該金屬切面231之銲線殘留部份230。最後，如第3G圖所示，形成該電磁遮蔽層250於該封膠體240之該頂面241與該些切割側面242，並覆蓋連接至該銲線殘留部份230之該金屬切面231。因此，本發明達成該電磁遮蔽層250之接地連接並不需要包含半切基板之多次切割操作。
在本發明之第二具體實施例中，揭示另一種增進電磁遮蔽層接地連接之半導體封裝構造，說明於第5圖之截面示意圖以及第6圖在單體化切割之前之截面示意圖。該半導體封裝構造300主要包含一基板210、一晶片220、一銲線殘留部份230、一封膠體240以及一電磁遮蔽層250。主要元件大體與第一具體實施例相同，相同圖號的元件不再詳細贅述。
該銲線殘留部份230係具有一顯露於該封膠體240切割側面242之金屬切面231。該電磁遮蔽層250係形成於該封膠體240之該頂面241與該些切割側面242，並覆蓋連接至該銲線殘留部份230之該金屬切面231。在本實施例中，該銲線殘留部份230係可更包含一殘留線段333，係由一打線結球銲點332拉出並截斷於與該封膠體240相鄰之切割側面242。較佳地，該封膠體240之該些切割側面242係可與該些切緣213傾斜地切齊，藉以擴大該金屬切面231之面積，以利該電磁遮蔽層250之覆蓋連接。此外，該些銲球270係可包含一殘留銲料371，係緊鄰該些切緣213之其中之一並被該電磁遮蔽層250連接，藉以增進該電磁遮蔽層250之接地連接。
如第6圖所示，在單體化切割之前，上述銲線殘留部份230係為一銲線330A之一部份，該銲線330A之中間線段係穿過該切割線201。而該殘留銲料371在切割前係為位於該切割線201之銲球，可與該些銲球270同時形成。
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。
100．．．習知半導體封裝構造
110．．．基板
113A．．．上切緣
113B．．．下切緣
114．．．鍍通孔
120．．．晶片
140．．．封膠體
141．．．頂面
142．．．切割側面
150．．．電磁遮蔽層
160．．．銲線
170．．．銲球
200．．．半導體封裝構造
201．．．切割線
210．．．基板
211．．．上表面
212．．．下表面
213．．．切緣
214．．．接地墊
215．．．接指
216．．．線路
220．．．晶片
221．．．銲墊
230．．．銲線殘留部份
231．．．金屬切面
232．．．打線結球銲點
240．．．封膠體
241．．．頂面
242．．．切割側面
250．．．電磁遮蔽層
260．．．完整銲線
270．．．銲球
300．．．半導體封裝構造
330A．．．銲線
332．．．打線結球銲點
333．．．殘留線段
371．．．殘留銲料
第1圖：習知電磁遮蔽層接地連接至基板半切割邊緣之半導體封裝構造之截面示意圖。
第2圖：依據本發明之第一具體實施例的一種增進電磁遮蔽層接地連接之半導體封裝構造之截面示意圖。
第3A至3G圖：依據本發明之第一具體實施例的該半導體封裝構造於製造過程中各步驟形成元件之截面示意圖。
第4圖：依據本發明之第一具體實施例的該半導體封裝構造之基板上表面示意圖。
第5圖：依據本發明之第二具體實施例的另一種增進電磁遮蔽層接地連接之半導體封裝構造之截面示意圖。
第6圖：依據本發明之第二具體實施例的該半導體封裝構造在單體化切割之前之截面示意圖。
200．．．半導體封裝構造
210．．．基板
211．．．上表面
212．．．下表面
213．．．切緣
214．．．接地墊
215．．．接指
216．．．線路
220．．．晶片
221．．．銲墊
230．．．銲線殘留部份
231．．．金屬切面
240．．．封膠體
241．．．頂面
242．．．切割側面
250．．．電磁遮蔽層
260．．．完整銲線
270．．．銲球

Claims (8)

  1. 一種增進電磁遮蔽層接地連接之半導體封裝構造，包含：一基板，係具有一上表面以及複數個切緣，於該上表面之周邊係設有一接地墊；一晶片，係設置於該基板上；一銲線殘留部份，係包含一打線結球銲點，該打線結球銲點係設置於該接地墊上；一封膠體，係形成於該基板之該上表面上，以密封該晶片與該銲線殘留部份，該封膠體係具有一頂面以及複數個切割側面，該銲線殘留部份係具有一顯露於該切割側面之金屬切面；以及一電磁遮蔽層，係形成於該封膠體之該頂面與該些切割側面，並覆蓋連接至該銲線殘留部份之該金屬切面；其中該基板之該上表面係更設有複數個接指，該基板內係具有一線路，係連接至少一之該些接指至該接地墊，該半導體封裝構造另包含複數個完整銲線，其兩端係分別連接該晶片之複數個銲墊與該些接指，並且該封膠體係更密封該些完整銲線；其中該接地墊係延伸至該基板之鄰近切緣並被該電磁遮蔽層所覆蓋連接。
  2. 根據申請專利範圍第1項所述之增進電磁遮蔽層接地連接之半導體封裝構造，其中該打線結球銲點係 為非完整，而使該金屬切面位於該打線結球銲點之外側。
  3. 根據申請專利範圍第1項所述之增進電磁遮蔽層接地連接之半導體封裝構造，其中該銲線殘留部份係更包含一殘留線段，係由該打線結球銲點拉出並截斷於與該封膠體相鄰之切割側面。
  4. 根據申請專利範圍第1、2或3項所述之增進電磁遮蔽層接地連接之半導體封裝構造，其中該電磁遮蔽層係更延伸覆蓋至該基板之該些切緣。
  5. 根據申請專利範圍第4項所述之增進電磁遮蔽層接地連接之半導體封裝構造，其中該封膠體之該些切割側面係與該些切緣垂直向切齊。
  6. 根據申請專利範圍第4項所述之增進電磁遮蔽層接地連接之半導體封裝構造，其中該封膠體之該些切割側面係與該些切緣傾斜地切齊。
  7. 根據申請專利範圍第1、2或3項所述之增進電磁遮蔽層接地連接之半導體封裝構造，另包含複數個銲球，係設於該基板之一下表面。
  8. 根據申請專利範圍第7項所述之增進電磁遮蔽層接地連接之半導體封裝構造，其中該些銲球係包含一殘留銲料，係緊鄰該些切緣之其中之一並被該電磁遮蔽層連接。
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