TWI520240B - 功率型晶片上引線之球柵陣列封裝 - Google Patents

功率型晶片上引線之球柵陣列封裝 Download PDF

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TWI520240B
TWI520240B TW097117315A TW97117315A TWI520240B TW I520240 B TWI520240 B TW I520240B TW 097117315 A TW097117315 A TW 097117315A TW 97117315 A TW97117315 A TW 97117315A TW I520240 B TWI520240 B TW I520240B
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Taiwan
Prior art keywords
lead frame
conductor
integrated circuit
reference voltage
die
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TW097117315A
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English (en)
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TW200908176A (en
Inventor
強斯頓 詹姆斯Ｐ
李助忠
安Ｎ 川恩 杜
米勒 詹姆士Ｗ
海斯 凱文Ｊ
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飛思卡爾半導體公司
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Publication of TW200908176A publication Critical patent/TW200908176A/zh
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Description

功率型晶片上引線之球柵陣列封裝
本發明一般係關於半導體器件領域。在一態樣中，本發明係關於電子組件封裝。
此申請案已於2007年5月10日在專利合作條約組織，國家工業產權機構(法國)提出申請，專利申請案號為PCT/IB2007/052711。
隨著積體電路器件的密度與複雜性提高且此等器件之大小縮小，在該等器件的設計與封裝上出現顯著挑戰。一種挑戰係，隨著電路複雜性增加，必須將越來越多的功率與信號線電連接至積體電路晶粒，而隨著器件大小縮小，允許此連接之空間越來越小。另一挑戰係，用於電連接信號及功率至積體電路晶粒(例如接合晶片上引線(LOC)或捲帶自動接合(TAB)引線框架導體至晶粒區域)之習知方法並不簡單是用於連接當今器件所需信號及功率線數量之一可行的方案，假定此等導體較晶粒大小具有相對較大且難控制的大小。此等習知方法在保護積體電路晶粒免遭結構性或機械損壞方面亦存在封裝挑戰，例如當引線框架導體延伸穿過該保護封裝以與外界電接觸時，濕氣或其他環境曝露可導致損壞。
隨著信號及功率線之數量增加，電子產業已嘗試藉由使用導線接合技術增加晶粒接觸之密度，且亦已採用新型封裝，例如球柵陣列(BGA)、平台格柵陣列(LGA)及針柵陣 列(PGA)封裝，以提供改良器件保護且減小封裝輪廓。然而，該等導線接合封裝解決方案常常不能將功率均勻地輸送至整個晶粒，此係由於該等功率線係導線接合至排列在晶粒22之作用或正表面23之所有側上的周邊接合墊，如圖1及2所解說。具體而言，圖1以一簡化示意形式描述一習知導線接合之BGA封裝器件10之一斷面圖，其中一積體電路晶粒22(具有一後表面21及作用表面23)係安裝或附著至一載體基板12且包覆在一絕緣封裝主體20中。使用一焊球安裝層8將焊球附接至載體基板12之一下表面，該焊球安裝層8實體附著且電連接每一焊球至該載體基板中的一導電電路。在封裝10中，透過導電路徑(例如VSS /熱焊球陣列5及導電跡線16)供應一第一參考電壓(例如VSS )至晶粒22之後表面21。此外，透過導電路徑(例如VDD 焊球3、導電跡線13、通道14、接觸接點15與VDD 導線接合導體24)供應一第二參考電壓(例如VDD )至晶粒22之作用表面23的一周邊邊緣。最後，透過導電路徑(例如形成於一載體基板12中的線路、接觸接點或層、導電通道、導電跡線(未顯示)以及信號導線接合導體26)將施加至信號焊球1的信號資訊2電連接至晶粒22之作用表面23的一周邊邊緣。除透過晶粒22之後表面21之電連接外，透過導電路徑，例如形成於一載體基板12中的線路、接觸接點或層、導電通道、導電跡線及VSS 導線接合導體(未顯示)，將施加至VSS 焊球5之VSS 資訊6電連接至晶粒22之作用表面23之一周邊邊緣。
由於VDD 導線接合導體24係附接至晶粒22之周邊處的接 合墊，因此功率在晶粒22之作用表面23上未能均勻地輸送。此可結合圖2加以解說，其描述圖1所述之封裝器件10的一簡化平面圖，其中相較於在周邊區域29處所供應之功率或電壓，在一中心區域27及/或內部區域28處所供應之功率或電壓縮減。內部區域27、28中的電壓降或功率下垂源於在周邊區域29中之電壓最強之事實，其中VDD 導線接合導體24係連接至晶粒22。功率損失之問題對於使用習知導線接合封裝之低功率器件尤其嚴重。例如，假設產品在5至8瓦範圍內，在一特定電源領域之區域上每毫伏電壓衰降可導致效能及/或良率損失。此等電壓降可削弱位於離一封裝層級供應端子超過大約2 mm之區域內的高速CMOS數位邏輯(例如大於600 Mhz)之效能。儘管覆晶封裝能提供良好的功率分配，但其成本通常比導線接合封裝高且會限制其應用空間。
因此，需要針對具有多個信號及功率線之一積體電路晶粒提供改良功率分配的一陣列封裝方案。此外，需要電連接信號及功率線至一積體電路晶粒但不會削弱器件效能或良率的一高成本效用的半導體器件封裝。亦需要能解決該技術中之問題(例如上文所概述)的改良封裝程序與器件。 在結合附圖及下列詳細說明檢視本申請案之剩餘部分後，熟習此項技術者將明白習知程序與技術的進一步限制與缺點。
本發明描述將一半導體晶粒囊封於一封裝中之方法及裝 置，其中將一囊封引線框架結構接合且連接至一積體電路晶體，以便分配功率及/或接地至橫跨該晶粒區域分佈的晶粒層級接合墊。除改良在晶粒區域上之功率分配外，該囊封引線框架結構亦針對導線接合之信號線在該晶粒之周邊處提供額外的接觸區域。透過形成於一載體基板中的導電路徑(例如焊球、導電跡線、通道、接觸接點)，電連接該引線框架結構至一晶片外功率及/或接地供應。此外，由一或多個圖案化導體層形成引線框架結構，該等導體層係佈置在積體電路晶粒區域上方以與該積體電路晶粒中的功率及/或接地供應端子之一陣列電接觸。為在整個晶粒區域上分配功率，圖案化引線框架結構以界定具有近端之複數個引線，其中每一近端經定位或對準以電連接至最後封裝裝配件中之積體電路晶粒中的一對應功率及/或接地供應端子。在各種具體實施例中，將圖案化引線框架結構電連接至具有橫跨該晶粒區域分佈之短的扁平化(low profile)強固導線接合之陣列的積體電路晶粒之功率及/或接地格柵。在其他具體實施例中，使用導電晶粒附著技術，例如導電黏接劑、焊料、熱壓或熱聲波接合技術，將圖案化引線框架結構之一或多層電連接至積體電路晶粒之功率及/或接地格柵。不論是否使用一或多個圖案化導體層實施，均將引線框架結構定位以完全包含在BGA基板邊緣內，使得無引線框架導電層延伸至產品組件外表面。在使用圖案化引線框架結構橫跨晶粒區域分配功率及/或接地供應後，可使用習知導線接合技術將信號線電連接至積 體電路晶粒，從而增加封裝中信號線連接的密度。
現將參考附圖詳細說明本發明之各種說明性具體實施例。雖然以下說明中提出各種細節，但應明白，沒有該等特定細節亦可實踐本發明，且可針對本文所述之本發明做出許多實施方案特定決策來實現該裝置設計者的特定目的，例如符合處理技術或相關設計限制，一實施方案與另一實施方案之目的可不同。雖然此一開發努力可能複雜且耗時，不過對於受益於此揭示內容的熟習此項技術者而言只是一例行任務。例如，結合一封裝半導體裝置之簡化斷面圖描述選定態樣，該等圖式不可縮放且不包括每一裝置特徵或幾何體以避免限制或混淆本發明。亦應注意，在整個此項具體描述中，將形成特定封裝組件(例如圖案化引線框架結構及導線接合導體)且將其組裝以製造封裝之半導體裝置。在下文未具體描述特定程序時，可使用熟習此項技術者習知的用於形成及組裝此等組件之技術。該等細節眾所周知，因此應視為不必教示熟習此項技術者如何製作或使用本發明。
如本文中所說明，在一導線接合之BGA封裝器件中定位且囊封一圖案化引線框架電源導體以輸送功率及/或接地電壓至分佈在一積體電路晶粒之整個作用表面上的多個晶粒層級電源端子。此可結合圖3加以解說，其描述一導線接合之BGA封裝裝配件30之一斷面圖，該封裝裝配件30包括一單層引線框架電源導體59用於分配功率至橫跨一積體 電路晶粒52之一作用表面分佈的複數個晶粒層級接合墊，該積體電路晶粒52係安裝或附著至一載體基板42且包覆在一絕緣封裝主體50中。可藉由使用一黏接層、一晶粒附著環氧化物或此項技術中已知的其他晶粒附著技術將積體電路晶粒52直接附著至載體基板42。
封裝裝配件30包括其中形成在載體基板42之上表面與下表面之間延伸的一或多個通道開口之一載體基板42。應明白，載體基板42可形成為任何所需形狀與厚度，且可包括任何所需特徵以用於形成一功能半導體封裝。此外，可使用一電絕緣材料(例如有機聚合物樹脂)之一相對較薄之撓性膜或使用由任何已知適當材料製造的一剛性、實質平坦部件製造載體基板42，該等已知適當的材料包括但不限於絕緣體塗布之矽、玻璃、陶瓷、環氧樹脂、雙馬來亞醯胺－三氮雜苯(BT)樹脂、或適用作一載體基板之此項技術中已知的任何其他材料。(例如)藉由使用一焊球安裝層38將複數個外部導體或導電球(例如導電焊球)附接於載體基板42之一下表面，該焊球安裝層38實體附著且電連接每一焊球至該載體基板中的一導電電路。各導電電路係由在載體基板42上且透過其形成的接觸接點、跡線、通道及封裝著陸區域之一導電圖案形成，以用於電連接(後續形成之)焊球至(隨後附著之)積體電路晶粒。例如，可透過導電路徑(例如VSS /熱焊球35及導電通道46)供應一外部參考電壓(例如VSS )至晶粒52之後表面51。應明白，儘管出於簡化說明之目的僅表示為一單一通道46，但在載體基板42中可形 成一或多個內部導電層(未顯示)。該等導電層可由任何導電材料形成，其包括但不限於導電摻雜之多晶矽、導電金屬或金屬合金、導電或導體填充之彈性體，或熟習此項技術者已知的用於電連接的任何其他導電材料。最後，使用選擇形成之介電層將在載體基板之一表面上形成的個別電路線(例如接觸接點或封裝著陸點)與另一者電分離。
在封裝裝配件30中，積體電路晶粒52具有一後表面51及形成作用電路之一作用表面53。透過耦合信號焊球31至信號導線接合導體56的載體基板42中的導電路徑(未顯示)，將信號資訊32電連接至晶粒52之作用表面53的周邊邊緣，信號導線接合導體56依次係接合至排列在晶粒52之正表面53之所有側上的周邊接合墊。習知導線接合技術之使用允許將多個信號導線接合導體56附著至作用表面53，從而增加晶粒52之信號線密度。
除信號資訊外，亦透過形成於載體基板42中的導電路徑將功率供應至晶粒52。為此目的，所述封裝裝配件30包括一單層引線框架電源導體59，其橫跨晶粒52之作用表面53而延伸且係用於供應功率至橫跨晶粒52之作用表面53分佈的複數個接合墊。使用一非導電黏接層58將所述單層引線框架電源導體59實體附著至晶粒52，該非導電黏接層58可由熱塑性聚(矽氧烷－醯亞胺)共聚物或任何所需的黏接/接合材料形成。此外，使用複數個短的扁平化強固導線接合54將單一引線框架導體59電連接至晶粒52中的複數個接合墊。為支撐此等導線接合連接，引線框架電源導體包括複 數個近端或接觸區域(例如，如圖4中作為導線接合54所附著之引線框架電源導體59之部分所示)，其終止在經組態用於附著至位於積體電路晶粒52之面上的複數個接合墊的接合端。亦使用任何製作電接觸所需的技術，例如使用焊料、導電黏接劑、熱壓接合、熱聲波接合或導線接合，將單層引線框架電源導體59電連接且實體連接至形成於載體基板42中的一或多個封裝著陸點45。依次透過通道44、導電跡線43及焊球導體33將封裝著陸點45電連接至一外部電源(例如VDD )。電源供應焊球導體33係顯示為附接在一或多個位置34中，當然可使用任何所需的位置。
一旦將引線框架電源導體59、積體電路晶粒52及導線接合導體附著至載體基板42，可藉由(例如)施加、注入或以其他方式形成一保護層來密封開口區域，以形成一囊封層或材料50用於密封且保護封裝裝配件30內的導電元件免遭濕氣、污染、腐蝕與機械衝擊。例如，可使用任何所需的技術在積體電路晶粒52上形成一傳輸模製化合物50以電絕緣、實體保護或者以其他方式保護且封裝晶粒52。藉由將引線框架電源導體59定位在BGA基板42之區域內，可藉由絕緣封裝主體50將引線框架電源導體59完全囊封，從而保護其免受潛在損害環境狀況。在選定具體實施例中，引線框架電源導體59經定位實質上位於晶粒52之區域內，使得電源導體59之部分沒有延伸穿過封裝主體50之外表面。在此位置中，藉由短的扁平化強固導線接合54將引線框架電源導體59接合且連接至晶粒52之作用表面53上的複數個晶 粒層級接觸接點。
雖然在圖3之斷面輪廓中僅顯示一單一引線框架電源導體59，但應明白，額外的引線框架電源導體亦可包括在封裝裝配件30中。例如，藉由形成具有包括一或多個開口區域之一適當圖案的單層引線框架電源導體59，可將一或多個額外的單層引線框架電源導體組裝且附著以橫跨開口區域所曝露之晶粒表面53之部分而延伸。使用該等額外電源導體，可藉由使用導線接合連接器54將各電源導體電連接至其對應接合墊，將額外功率位準供應至橫跨晶粒52之作用表面53分佈的晶粒層級接合墊。實際上，可使用兩個分離的引線框架電源導體59、159自封裝著陸接點45供應第一功率位準(例如VDD )，各引線框架電源導體均經圖案化以覆蓋晶粒52之作用表面53之一部分(包括中心或內部區域之部分)且包括曝露晶粒表面53之其他部分的開口區域。
在藉由第一引線框架電源導體59、159界定之開口區域中，使用兩個分離的引線框架電源導體55、155自封裝著陸接點47供應第二功率位準(例如VSS )，各引線框架電源導體經圖案化以覆蓋藉由引線框架電源導體59、159所曝露之晶粒52之作用表面53的一部分。此外，經由導線接合連接器54將各引線框架電源導體55、155電連接至晶粒層級接合墊。在圖4所述之封裝裝配件30之平面圖中，各引線框架電源導體55、59、155、159係可形成具有一A形圖案，該圖案經定位以佈置在晶粒表面53之一中心或內部區 域上，同時留有空間用於簡單定位另一引線框架電源導體。然而，可使用任何所需圖案以在晶粒表面53上提供引線框架電源導體之互補定位。引線框架電源導體之此種定位不僅改良在晶粒區域上的功率分配，亦釋放在積體電路晶粒53之周邊的額外晶粒層級接觸接點，使得使用習知導線接合技術即可附著額外的信號線56。為支撐此等導線接合連接，各引線框架電源導體55、59、155、159均包括終止在接合端的複數個近端或接觸區域(例如，如圖4中位於著陸接點45、47上方的引線框架電源導體之部分所示)，該等接合端經組態用於附著至位於積體電路晶粒52之面上的複數個接合墊。應明白，任何所需的組裝技術均可用於將引線框架電源導體55、59、155、159附接在一起或依序附接至載體基板42及電路晶粒52。例如，首先可將一或多個引線框架電源導體附接至個別封裝著陸接點45、47，接著將其導線接合至位於積體電路晶粒52之面上的複數個接合墊，或必要時可將順序反轉。
雖然如上文所述可使用一或多個非重疊之導電層實施引線框架電源導體，但藉由實施該引線框架電源導體為一雙層或多層引線框架導體用於橫跨該晶粒區域分配功率及/或接地，亦可獲得功率分配優點。圖5中描述一實施方案範例，其描述在組裝之一中間階段一導線接合之BGA封裝裝配件60之一斷面圖，其中一積體電路92與一多層引線框架導體之第一層76係附接至一載體基板72。使用一焊球安裝層68將複數個焊球61、63、65附接於載體基板72之一下 表面，該焊球安裝層68實體附著且電連接每一焊球至該載體基板72中的一導電電路。各導電電路可由接觸接點、跡線、通道及封裝著陸區域之一導電圖案形成，以用於將(後續形成之)焊球電連接至(後續附著之)積體電路晶粒。例如，可透過導電路徑(例如VSS /熱焊球65及導電通道73)供應一外部參考電壓(例如VSS )至晶粒92之後表面91。
為向晶粒92之作用表面93提供一額外或替代性電源供應(例如參考電壓VSS )，封裝裝配件60可包括一第一引線框架電源導體76，其橫跨晶粒92之作用表面93延伸且接觸橫跨晶粒表面93分佈的複數個接合墊98。引線框架電源導體76可由引線框架型塊金屬(例如銅、金、鍍有銀或金之銅、錫及/或引線，及類似物)的一或多個導電層形成，其藉由(例如)選擇性蝕刻一導電層、衝壓或網版印刷該引線框架電源導體以一低成本提供低損失功率分配。使用對應的複數個導電晶粒附著黏接層99將所述第一引線框架電源導體76實體且電附著至複數個晶粒接合墊98。此外，亦使用任何製作電接觸所需的技術，例如使用焊料、導電黏接劑、熱壓接合、熱聲波接合或導線接合，將第一引線框架電源導體76電連接且實體連接至形成於載體基板72中的一或多個封裝著陸點75。依次透過導電跡線74、通道73及VSS /熱焊球65將封裝著陸點75電連接至外部電源(例如VSS )。
雖然可使用導電晶粒附著技術將第一引線框架電源導體76電連接至晶粒92中的晶粒層級接合墊98，但通常使用導線接合導體將形成於第一引線框架電源導體76上方的任何 額外的引線框架電源導體層連接至其對應的晶粒層級接合墊。為此目的，第一引線框架導體76係可形成具有一適當圖案，其包括一或多個開口區域，透過該等開口區域，可將額外引線框架電源導體導線接合連接至晶粒層級接觸接點。為解說此一圖案化第一引線框架電源導體76之一範例，圖6描述圖5中所述之封裝裝配件60之一平面圖。如圖所述，第一引線框架電源導體76可形成為個別導體線之一交叉陰影圖案，其經定位以佈置在整個晶粒表面93上(特別包括中心或內部區域)，同時提供開口以曝露晶粒表面93之周邊與內部區域兩者上的複數個晶粒層級接觸接點95。當然，任何所需的圖案均可用於曝露晶粒表面93中的晶粒層級接觸接點95，只要第一引線框架電源導體76中之開口允許堆疊在第一引線框架電源導體76上方的額外的引線框架電源導體導線接合至曝露的晶粒層級接觸接點95。
不論使用何種圖案，(憑藉透過載體基板72連接至外部參考電壓的封裝著陸點75)均將自封裝著陸點75供應之功率分配貫穿第一引線框架電源導體76。當電流流經第一引線框架電源導體76且朝晶粒表面93之內部區域中的電連接之晶粒層級接合墊98流動時，電流係橫跨第一引線框架電源導體76之個別導體元件而分割。因此，圖6所示自左下部分封裝著陸點75提供之電流101係分成連續的電流路徑102，各路徑102依次係分成連續電流路徑103。不過，憑藉電連接至晶粒層級接合墊98之第一引線框架電源導體76之個別導電元件，相較於其中將功率線導線接合至位於晶 粒表面93之周邊上的晶粒層級接合墊的習知方法，減少橫跨晶粒表面93之電壓降。
圖7及8解說一堆疊引線框架電源導體之一範例，其分別描述一導線接合之BGA封裝裝配件90之斷面圖與平面圖，其中一積體電路92、第一引線框架電源導體76與第二引線框架電源導體85係附接至一載體基板72且包覆於一絕緣封裝主體100中。第二引線框架電源導體85係定位在第一引線框架電源導體76上且藉由一介電材料86與其分離。或者，可將第一及第二引線框架電源導體構造成具有經一起層壓或形成之一介電層及兩個層導電層的兩層式複合結構，以便定位該介電層於兩個導電層之間，該兩個導電層從而用作兩層引線框架電源導體。當經定位以橫跨整個晶粒92延伸時，第二引線框架電源導體85可用於向晶粒92(包括中心或內部區域)上之所有晶粒層級接合墊95均勻地提供額外功率(例如參考電壓VDD )。此可藉由連接晶粒層級接合墊95與第二引線框架電源導體85之間的複數個導線接合導體87實現。依次使用製造電接觸所需的任何技術將第二引線框架電源導體85實體且電連接至形成於載體基板72中的一或多個封裝著陸點84。依次透過導電通道及跡線81至83及VDD 焊球63將封裝著陸點84電連接至外部電源(例如VDD )。
為解說如何將第二引線框架電源導體85導線接合至晶粒層級接合墊95之一範例，圖8描述圖7所述之封裝裝配件90之一平面圖。如圖所述，第二引線框架電源導體85經圖案 化成個別導體線之一交叉陰影圖案且經定位以與第一引線框架電源導體76重疊。以此配置，第一及第二引線框架電源導體76、85可經定位佈置在整個晶粒表面93上(特別包括中心或內部區域)同時提供開口以曝露晶粒表面93之周邊與內部區域兩者上的複數個晶粒層級接觸接點95。應明白，第一與第二引線框架電源導體76、85不必精確重疊，儘管該重疊尤其在中心或內部區域應允許清晰界定曝露晶粒層級接觸接點95之開口。透過該等開口，將導線接合導體87定位且附著以電連接接觸接點95與第二引線框架電源導體85。出於簡化視覺呈現之目的，圖8僅顯示一些導線接合導體87，儘管應明白可製作額外的導線接合連接來連接接觸接點95與第二引線框架電源導體85。
透過第二引線框架電源導體85，來自封裝著陸點84之電流將朝晶粒表面93之內部區域中的導線接合之晶粒層級接合墊95流動。在其流動時，電流係橫跨第二引線框架電源導體85之個別導電元件分割，使得圖8所示的自左下部分封裝著陸點84提供之電流201將會分成連續的電流路徑202，各電流路徑202依次係分成連續電流路徑203。不過，憑藉電連接至晶粒層級接合墊95之第二引線框架電源導體85之個別導電元件，相較於其中將功率線導線接合至位於晶粒表面93之周邊上的晶粒層級接合墊的習知方法，減少橫跨晶粒表面93之電壓降。
應明白，堆疊之引線框架電源導體可包括堆疊在第一及第二引線框架電源導體上方的額外導電層，從而允許額外 功率位準供應至晶粒表面93之內部區域。不論使用多少堆疊之引線框架電源導體，此處界定之開口係用於製造至晶粒層級接合墊之絲接合觸，使得自該等電源導體可施加功率至整個晶粒表面，而不需使用周邊的晶粒接觸接點來施加功率至晶片的中心區域。此外，額外的電源導體層及形成於其中的開口允許將額外的信號線導線接合至積體電路晶粒92之周邊的晶粒層級信號接合墊94。在選定之具體實施例中，針對信號導線接合所附著之晶粒層級信號接合墊94，保留晶粒表面的周邊區域。儘管圖中未顯示，此允許晶粒外的信號導線接合導體(例如圖4中所示的線路56)附著至晶粒92之周邊區域中的晶粒層級信號接合墊94至不被板內供應線87替代之程度。
在一範例組裝序列中，例如藉由使用一晶粒附著黏接層(未顯示)或其他適合的晶粒附著技術，將積體電路晶粒92定位且附接至載體基板72。此外，例如，藉由選擇性蝕刻一導電層、衝壓或網版印刷該引線框架電源導體以形成複數個開口，由一或多個導電層形成第一引線框架電源導體76。在附接晶粒92後，將第一引線框架電源導體76定位且附接至載體基板72，以便將第一引線框架電源導體76之一或多個近端對準形成於載體基板72中的對應封裝著陸接點75。可使用製造電接觸所需的任何技術，例如使用焊料、導電黏接劑、熱壓接合、熱聲波接合或導線接合，將第一引線框架電源導體76電連接且實體連接至封裝著陸接點75。此時，亦憑藉先前與接合墊98對準形成之晶粒附著黏 接層99將第一引線框架電源導體76電連接且實體連接至晶粒層級接合墊98。在第一引線框架電源導體76之頂部，施加一介電層86，用作第一引線框架電源導體76之部分或用作一分離介電層。使附接第一引線框架電源導體76，使用任何所需的電接觸技術將第二引線框架電源導體85定位且附接至載體基板72，以便將第二引線框架電源導體85之一或多個近端與形成於載體基板72中的對應封裝著陸接點84對準。此時，亦使用延伸穿過第一及第二引線框架電源導體中界定之開口的導線接合導體87將第二引線框架電源導體85電連接至晶粒層級接合墊95。
此時，應明白，已提供製造一球柵陣列封裝裝配件之一方法。在該方法下，提供一球柵陣列載體基板，其具有複數個參考電壓端子封裝著陸接點及形成於該載體基板之一表面上的複數個信號線封裝著陸接點。此外，提供一積體電路晶粒，其具有包含一內部區域(其中定位晶粒層級參考電壓供應端子)及一周邊區域(其中定位晶粒層級信號端子)之一作用表面。在該積體電路中，該等晶粒層級參考電壓供應端子係用於向該電路提供一參考電壓(例如接地、I/O VDD 、VDD 或VSS )。例如，藉由施加一晶粒附著黏接材料至載體基板表面之一部分且接著將該積體電路晶粒附著至晶粒附著黏接材料，將該積體電路晶粒附著至載體基板表面，以便將該積體電路晶粒之作用表面與載體基板表面相對(即背對)。在附著積體電路晶粒後，將一第一引線框架電源導體附著至至少兩個參考電壓端子封裝著陸接 點，以便將第一引線框架電源導體電連接至參考電壓端子封裝著陸接點且佈置在積體電路晶粒之內部區域上。此外，例如藉由使用複數個導線接合導體將該等晶粒層級參考電壓供應端子導線接合至第一引線框架電源導體，或藉由施加一導電晶粒附著黏接材料將該等晶粒層級參考電壓供應端子電連接至第一引線框架電源導體，將第一引線框架電源導體電連接至積體電路晶粒之內部區域中的複數個晶粒層級參考電壓供應端子。在選定具體實施例中，將一第二引線框架電源導體附接至至少兩個不同參考電壓端子封裝著陸接點，以便將該第二引線框架電源導體電連接至該等不同參考電壓端子封裝著陸接點且佈置在積體電路晶粒之內部區域上。可藉由在第一引線框架電源導體上堆疊第二引線框架電源導體，或藉由在第一引線框架電源導體界定之一開口區域中附接第二引線框架電源導體來附接第二引線框架電源導體，使得其不覆蓋有第一引線框架電源導體。以此方式，可將第一引線框架電源導體電連接至一第一參考電壓且可將第二引線框架電源導體電連接至一第二參考電壓。亦將該複數個信號線封裝著陸接點導線接合至積體電路晶粒上的複數個晶粒層級信號端子。之後，將該積體電路晶粒與該等引線框架電源導體囊封以完全封閉該第一引線框架電源導體。
在另一形式中，提供用於封裝一半導體器件之球柵陣列封裝裝配件。該封裝包括具有一第一表面之一載體基板，其中形成有複數個導電接合墊用於供應一參考電壓。該封 裝亦包括具有一作用表面之一積體電路，其中形成有複數個信號接合墊及橫跨該作用表面之內部區域分佈的複數個參考電壓接合墊。積體電路之作用表面在附接時可與載體基板之第一表面相對。此外，該封裝包括一圖案化引線框架導體，其係佈置在積體電路之作用表面上且電連接(例如接合)至複數個參考電壓接合墊及複數個導電接合墊，從而將該積體電路電耦合至載體基板。在選定具體實施例中，使用兩個圖案化引線框架導體實施該圖案化引線框架導體，其中一第一圖案化引線框架電源導體係佈置在積體電路之作用表面上且電連接(例如接合)至一第一複數個參考電壓接合墊及一第一複數個導電接合墊，且其中一第二圖案化引線框架導體係佈置在積體電路之作用表面上且電連接(例如接合)至一第二複數個參考電壓接合墊及一第二複數個導電接合墊。如文中所述，該第二圖案化引線框架導體可經定位以與第一圖案化引線框架導體至少部分重疊，或可經定位以與第一圖案化引線框架導體相鄰，使得在第一與第二圖案化引線框架導體之間無重疊。在其他具體實施例中，將該圖案化引線框架導體實施成具有一起形成之一介電層及兩個導電層之兩層式複合結構，以便將該介電層定位在兩個導電層之間，藉此各導電層係一圖案化引線框架導體。球柵陣列封裝亦可包括複數個導線接合連接器用於將形成於載體基板之第一表面上的複數個信號線封裝著陸接點電連接至形成於積體電路之作用表面上的複數個信號接合墊。在最後組裝中，該封裝可包括一絕緣封 裝主體，其係附接至載體基板且完全囊封該封裝裝配件中的圖案化引線框架導體與積體電路。
在另一形式中，提供具有包含一作用表面之一積體電路的一積體電路器件，其中形成有橫跨該作用表面之內部區域上分佈的複數個參考電壓接合墊。該積體電路器件包括用於安裝且囊封積體電路的一封裝結構，其中該封裝結構包括一囊封引線框架導體，其係佈置在積體電路之作用表面上且電連接至橫跨該作用表面之內部區域的複數個參考電壓接合墊。
儘管本文所述示範性具體實施例係針對各種封裝裝配件及其製造方法，但不必將本發明限制於解說本發明之發明態樣的具體實施例範例，其可應用於各種封裝程序及/或器件。因此，上述特定具體實施例僅為說明性的且不應視為限制本發明，獲益於本文教導內容之熟習此項技術者應明白，可以不同但等效的方式修改且實踐本發明。因此，上述說明未意欲將本發明限制於所提出的特定形式，相反，其意欲涵蓋可包括在藉由所附專利申請範圍所定義之本發明之精神與範疇內的此等替代、修改及等效，使得熟習此項技術者應瞭解，其可進行各種變更、替換與更改而不脫離以最廣泛形式的本發明之精神及範疇。
優勢、其他優點及問題解決方案已在前面參考特定具體實施例描述。然而，優勢、優點、問題解決方案及產生或彰顯任何優勢、優點或解決方案的任何元件，均不應視為任何或所有申請專利範圍的關鍵、必要或基本特徵或元 件。如本文中所使用的術語"包括"、"包含"或其任何其他變化，都是用來涵蓋非專有內含項，使得包括元件清單的程序、方法、物品或裝置，不僅包括這些元件，而且還包括未明確列出或此類程序、方法、物品或裝置原有的其他元件。
1‧‧‧信號焊球
3‧‧‧VDD 焊球
5‧‧‧VSS /熱焊球陣列
8‧‧‧焊球安裝層
10‧‧‧BGA封裝器件
12‧‧‧載體基板
13‧‧‧導電跡線
14‧‧‧通道
15‧‧‧接觸接點
16‧‧‧導電跡線
20‧‧‧絕緣封裝主體
21‧‧‧後表面
22‧‧‧積體電路晶粒
23‧‧‧作用表面
24‧‧‧VDD 導線接合導體
26‧‧‧信號導線接合導體
27‧‧‧中心區域
28‧‧‧內部區域
29‧‧‧周邊區域
30‧‧‧封裝裝配件
31‧‧‧信號焊球
33‧‧‧焊球導體
35‧‧‧VSS /熱焊球
38‧‧‧焊球安裝層
42‧‧‧載體基板
43‧‧‧導電跡線
44‧‧‧通道
45‧‧‧接合墊/封裝著陸點/著陸接點
46‧‧‧導電通道
47‧‧‧封裝著陸接點
50‧‧‧絕緣封裝主體/模製化合物
51‧‧‧後表面
52‧‧‧積體電路晶粒
53‧‧‧作用表面
54‧‧‧導線接合連接器
55‧‧‧引線框架電源導體
56‧‧‧信號導線接合導體/信號線
58‧‧‧非導電黏接層
59‧‧‧單層引線框架電源導體
60‧‧‧封裝裝配件
61‧‧‧焊球
63‧‧‧焊球
65‧‧‧焊球
68‧‧‧焊球安裝層
72‧‧‧載體基板
73‧‧‧通道
74‧‧‧導電跡線
75‧‧‧封裝著陸點/封裝著陸接點/導電接合墊
76‧‧‧引線框架電源導體
81至83‧‧‧導電通道及跡線
84‧‧‧封裝著陸點/封裝著陸接點/導電接合墊
85‧‧‧第二引線框架電源導體
86‧‧‧介電材料/介電層
87‧‧‧導線接合導體/板內供應線
91‧‧‧後表面/第一表面
92‧‧‧積體電路/晶粒
93‧‧‧作用表面/晶粒表面
95‧‧‧晶粒層級接觸接點/接合墊
98‧‧‧接合墊/位準參考電壓供應端子
99‧‧‧導電晶粒附著黏接層/黏接材料
100‧‧‧絕緣封裝主體
155‧‧‧引線框架電源導體
159‧‧‧引線框架電源導體
201‧‧‧電流
202‧‧‧電流路徑
203‧‧‧電流路徑
當結合下列圖式考慮上述較佳具體實施例的詳細說明，可理解本發明並且獲得其許多目標、特徵及優點，其中：圖1以簡化示意形式解說一習知導線接合之BGA封裝器件的一斷面圖；圖2解說圖1中所述封裝器件之一簡化平面圖；圖3解說一導線接合之BGA封裝器件之一斷面圖，其中一單層引線框架提供功率至橫跨晶粒區域分佈的晶粒層級接合墊；圖4解說圖3中所述封裝器件之一平面圖；圖5解說一導線接合之BGA封裝器件之一斷面圖，其中一多層引線框架之第一層係附接至一載體基板；圖6解說圖5所述封裝器件之一平面圖；圖7解說一導線接合之BGA封裝器件之一斷面圖，其中一多層引線框架之第二層係附接至一載體基板以提供功率至橫跨晶粒區域分佈的晶粒層級接合墊；以及圖8解說圖7所述封裝器件之一平面圖。
應瞭解，為說明之簡化及清楚起見，並無必要依比例繪製圖中所示元件。例如，為促進且改良清晰度且便於理解 起見，某些元件的尺寸相對於其他元件而誇大。另外，視情況，圖式中會重複參考數字，以表示對應或類似的元件。
30‧‧‧封裝裝配件
42‧‧‧載體基板
45‧‧‧接合墊/封裝著陸點/著陸接點
47‧‧‧封裝著陸接點
52‧‧‧積體電路晶粒
53‧‧‧作用表面
54‧‧‧導線接合連接器
55‧‧‧引線框架電源導體/信號線
56‧‧‧信號導線接合導體
155‧‧‧引線框架電源導體
159‧‧‧引線框架電源導體

Claims (17)

  1. 一種用於製造一封裝裝配件的方法，其包括：提供一載體基板，其具有形成於該載體基板之一第一表面上的複數個參考電壓端子封裝著陸接點及複數個信號線封裝著陸接點；將一積體電路晶粒附著至該載體基板之該第一表面，其中該積體電路晶粒包括一作用表面，其具有複數個晶粒層級參考電壓供應端子及複數個晶粒層級信號端子；將一第一引線框架電源導體之一導電結構附接至該等參考電壓端子封裝著陸接點之至少兩者，以便將該第一引線框架電源導體之該導電結構電連接至該等參考電壓端子封裝著陸接點且佈置在該積體電路晶粒之一內部區域上；電連接該第一引線框架電源導體之該導電結構至該積體電路晶粒之該內部區域中的該複數個晶粒層級參考電壓供應端子；囊封該積體電路晶粒與第一引線框架電源導體以完全封閉該第一引線框架電源導體；其中電連接該第一引線框架電源導體之該導電結構至該複數個晶粒層級參考電壓供應端子包括在囊封該積體電路晶粒前，以複數個導線接合導體將該複數個晶粒層級參考電壓供應端子導線接合至該第一引線框架電源導體之該導電結構。
  2. 如請求項1之方法，其中將該積體電路晶粒附著至該載 體基板之該第一表面包括：附著該積體電路晶粒，使得該積體電路晶粒之該作用表面背對該載體基板之該第一表面。
  3. 如請求項1之方法，其進一步包括在囊封該積體電路晶粒前，導線接合該複數個信號線封裝著陸接點至該積體電路晶粒上的該複數個晶粒層級信號端子。
  4. 如請求項1之方法，其進一步包括將一第二引線框架電源導體附接至至少兩個不同參考電壓端子封裝著陸接點，以便將該第二引線框架電源導體電連接至該至少兩個不同參考電壓端子封裝著陸接點且佈置在該積體電路晶粒之該內部區域上。
  5. 如請求項4之方法，其中將該第一引線框架電源導體之該導電結構電連接至一第一參考電壓，且將該第二引線框架電源導體電連接至一第二參考電壓。
  6. 如請求項4之方法，其中附接該第二引線框架電源導體包括在該第一引線框架電源導體上堆疊該第二引線框架電源導體。
  7. 如請求項4之方法，其中附接該第二引線框架電源導體包括在藉由該第一引線框架電源導體界定之一開口區域中附接該第二引線框架電源導體。
  8. 如請求項1之方法，其中電連接該第一引線框架電源導體之該導電結構包括電連接該第一引線框架電源導體至該積體電路晶粒之該內部區域中的複數個晶粒層級接地供應端子。
  9. 如請求項1之方法，其中電連接該第一引線框架電源導體之該導電結構包括電連接該第一引線框架電源導體之該導電結構至該積體電路晶粒之該內部區域中的複數個晶粒層級VDD供應端子。
  10. 如請求項1之方法，其中電連接該第一引線框架電源導體之該導電結構包括電連接該第一引線框架電源導體之該導電結構至該積體電路晶粒之該內部區域中的複數個晶粒層級VSS供應端子。
  11. 一種封裝裝配件，其包括：一載體基板，其包括一第一表面及位於該第一表面處用於供應一參考電壓之複數個導電接合墊；一積體電路，其包括一作用表面，該作用表面具有橫跨該作用表面分佈之複數個信號接合墊及複數個參考電壓接合墊；一圖案化引線框架導體，其係佈置在該積體電路之該作用表面上且電連接至該複數個參考電壓接合墊及該複數個導電接合墊，從而將該積體電路電耦合至該載體基板；以及一絕緣封裝主體，其係附接至該載體基板，以便將該圖案化引線框架導體完全囊封在該封裝裝配件中；其中該圖案化引線框架導體包括佈置在該積體電路之該作用表面上之一鄰接導電材料之一導電結構，其從該積體電路向外並朝該載體基板向下延伸，且電連接至一第一複數個導電接合墊； 複數個導線接合，每個導線接合電連接至一第一複數個參考電壓接合墊之一參考電壓接合墊且至該圖案化引線框架導體之該導電結構。
  12. 如請求項11之封裝裝配件，其中該圖案化引線框架導體包括：一第一圖案化引線框架導體，其係佈置在該積體電路之該作用表面上且電連接至第一複數個參考電壓接合墊及一第一複數個導電接合墊，及一第二圖案化引線框架導體，其係佈置在該積體電路之該作用表面上且電連接至一第二複數個參考電壓接合墊及一第二複數個導電接合墊。
  13. 如請求項12之封裝裝配件，其中該第二圖案化引線框架導體經定位以至少部分重疊於該第一圖案化引線框架導體。
  14. 如請求項11之封裝裝配件，其中該積體電路之該作用表面與該載體基板之該第一表面相對。
  15. 如請求項11之封裝裝配件，其進一步包括複數個導線接合導體，其用於將形成於該載體基板之該第一表面上的複數個信號線封裝著陸接點電連接至形成於該積體電路之該作用表面上的該複數個信號接合墊。
  16. 一種封裝裝配件，其包括：一載體基板，其包括一第一表面及位於該第一表面處用於供應一參考電壓之複數個導電接合墊；一積體電路，其包括一作用表面，該作用表面具有橫 跨該作用表面分佈之複數個信號接合墊及複數個參考電壓接合墊；一圖案化引線框架導體，其係佈置在該積體電路之該作用表面上且電連接至該複數個參考電壓接合墊及該複數個導電接合墊，從而將該積體電路電耦合至該載體基板；以及一絕緣封裝主體，其係附接至該載體基板，以便將該圖案化引線框架導體完全囊封在該封裝裝配件中；其中該圖案化引線框架導體包括：佈置在該積體電路之該作用表面上且電連接至一第一複數個參考電壓接合墊及一第一複數個導電接合墊之一第一圖案化引線框架導體，以及佈置在該積體電路之該作用表面上且電連接至一第二複數個參考電壓接合墊及一第二複數個導電接合墊之一第二圖案化引線框架導體；其中該第二圖案化引線框架導體經定位相鄰於該第一圖案化引線框架導體，使得在該等第一與第二圖案化引線框架導體之間無重疊。
  17. 一種封裝裝配件，其包括：一載體基板，其包括一第一表面及位於該第一表面處用於供應一參考電壓之複數個導電接合墊；一積體電路，其包括一作用表面，該作用表面具有橫跨該作用表面分佈之複數個信號接合墊及複數個參考電壓接合墊； 一圖案化引線框架導體，其係佈置在該積體電路之該作用表面上且電連接至該複數個參考電壓接合墊及該複數個導電接合墊，從而將該積體電路電耦合至該載體基板；以及一絕緣封裝主體，其係附接至該載體基板，以便將該圖案化引線框架導體完全囊封在該封裝裝配件中；其中該至少一圖案化引線框架導體包括具有一起形成之一介電層及兩個導電層之兩層式複合結構，以便將該介電層定位在該兩個導電層之間，藉此該等導電層之每一者係一圖案化引線框架導體。
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