TWI447878B - 增加通路及降低電阻之電晶體連接結構 - Google Patents

增加通路及降低電阻之電晶體連接結構 Download PDF

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Publication number
TWI447878B
TWI447878B TW099116458A TW99116458A TWI447878B TW I447878 B TWI447878 B TW I447878B TW 099116458 A TW099116458 A TW 099116458A TW 99116458 A TW99116458 A TW 99116458A TW I447878 B TWI447878 B TW I447878B
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Taiwan
Prior art keywords
soldering
medium
wafer
lead frame
area
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TW099116458A
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English (en)
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TW201133751A (en
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Chung Hsing Tzu
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Great Team Backend Foundry Inc
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Description

增加通路及降低電阻之電晶體連接結構
本發明係有關一種電晶體連接結構，尤指一種能明顯增加電訊連通通路、降低電阻及提高電訊傳輸速率之電晶體連接結構。
按，習用電晶體連接結構，請參閱第1圖、第2圖及第3圖所示，係利用一連通介物(3)連接一個或數個晶片(1)與導線架(2)以達到電訊之連通，其中業界使用來做為連通介物(3)的原料包括有金、銅及鋁，依其製造形狀而稱包括有金線、銅線、鋁線、鋁帶或沖壓銅片等；然而在連接過程中，由於必需顧及後續封裝的巨大衝力、避免暇疵品產生及方便加工作業，在將連通介物(3)焊設於晶片(1)及導線架(2)上時，往往需要有較寬的可焊設區域(11)，相對的也能使電訊的連通較多且較快，然而，一般用於連通介物(3)之金線、銅線、鋁線、鋁帶或沖壓銅片的體積都非常的細薄；換言之，電訊藉以通過的通路面積(31)也會非常的窄且不及於連通介物(3)與晶片(1)及導線架(2)的焊設區域(12、21)面積，在此情況下，往往造成電訊在連通的過程中產生巨大的電阻而減緩電訊傳輸速率，如此成為業界相當棘手的問題。
因此為有效解決上述電阻過高及傳輸速率過慢等缺失，本案發明人乃研發出此一利用藉由增加連通再介物的結構，除能有效增加電訊連通的通路及擴大電訊通過之介面外，相對更能降低電阻及提高電訊傳輸速率。
本發明可增加通路及降低電阻之電晶體連接結構，主要係利用於連通介物上增加至少一層之連通再介物的結構特徵，藉以有效增加電訊連通之通路及擴大電訊通過之介面外，進而有效降低電阻及提高電訊傳輸速率等效果為其主要發明者。
茲依附圖實施例將本發明之結構特徵及其他之作用、目的詳細說明如下：請參閱第4圖所示，係包括至少一晶片(4)，至少一導線架(5)及至少一連通介物(6)與至少一連通再介物(7)，其中：在該晶片(4)之可選擇面上設有可焊設區域(41)，主要係提供連通介物(6)之第一焊接點(61)焊設於晶片(4)上做為電訊導通之用，而晶片(1)上與連通介物(6)之第一焊接點(61)實際焊設之區塊我們稱之為第一焊設區域(42)；在該導線架(5)之可選擇面上亦可供連通介物(6)之第二焊接點(62)焊設之，以做為電訊導通之用，而導線架(5)上與連通介物(6)之第二焊接點(62)實際焊接之區塊我們稱之第二焊設區域(51)；該連通介物(6)之材質係可為金、銅及鋁等導通性佳的金屬，其形態可為線狀、帶狀、片狀等，依其材質及形態可概分為金線、銅線、鋁線、鋁帶及沖壓銅片等，主要係於連通介物(6)之兩端分別設有第一焊接點(61)與第二焊接點(62)，該第一焊接點(61)係與晶片(1)之第一焊設區域(42)焊接之，該第二焊接點(62)係與導線架(5)之第二焊設區域(51)焊接之，如此能達到晶片(4)與導線架(5)間電訊的連通，而連通介物(6)上可供電訊通過之區域我們稱之為通路面積(63)；該連通再介物(7)之材質亦可為金、銅及鋁等導通性佳的金屬，其形態亦可為線狀、帶狀、片狀等，依其材質及形態可概分為金線、銅線、鋁線、鋁帶及沖壓銅片等，該連通再介物(7)之兩端亦分別設有第一焊接點(71)與第二焊接點(72)，該第一焊接點(72)係焊設於連通介物(6)上非與晶片(4)相焊設之一面，該第二焊接點(72)係焊設於連通介物(6)上非與導線架(5)相焊設之一面，藉此而能增加晶片(4)與導線架(5)間電訊連通的通路面積(73)，如此除能有效降低晶片(4)與導線架(5)間電訊連通的電阻外，更能提高電訊傳輸速率(因為電阻降低，通路增加了)；請參閱第5圖至第10圖所示，其主要係為藉由本發明主要概念加以配合不同材質及形態之連通介物(6)與連通再介物(7)加以組合成之應用實施例設計，第五圖係為沖壓銅片之連通介物(6)再加上沖壓銅片的連通再介物(7)的設計組合，第六圖則帶狀之連通介物(6)再加上鋁線狀之連通再介物(7)的設計組合，第七圖則為帶狀之連通介物(6)再加上金線或銅線之連通再介物(7)的設計組合，第八圖則為沖壓銅片的連通介物(6)再加上帶狀之連通再介物(7)的設計組合，第九圖則為沖壓銅片的連通介物(6)再加上鋁線的連通再介物(7)的設計組合，第十圖則為沖壓銅片的連通介物(6)再加上金線或銅線之連通再介物(7)的設計組合；上述所列舉之實施例僅為本發明內容可供變化設計組合之部份，其藉由金線、銅線、鋁線、鋁帶、沖壓銅片交互組合所形成之設計皆為本發明範圍之中，且連通再介物(7)之組合亦不限於一層，即為連通介物上所層疊之連通再介物可依封裝面積及實際需求多層層疊；綜上所述，本發明所為增加通路及降低電阻之電晶體連接結構，已確實具有新實用性與創作性，其手段之運用亦出於新穎無疑，且功效與設計目的誠然符合，完全符合專利要件，為此，依法提出發明專利申請。
 習用技術
1．．．晶片
2．．．導線架
3．．．連通介物
11．．．可焊設區域
31．．．通路面積
12、21．．．焊設區域
本發明
4．．．晶片
5．．．導線架
6．．．連通介物
7．．．連通再介物
41．．．晶片可焊設區域
61．．．連通介物第一焊接點
42．．．第一焊設區域
62．．．連通介物第二焊接點
51．．．第二焊設區域
63．．．連通介物之通路面積
71．．．連通再介物第一焊接點
72．．．連通再介物第二焊接點
73．．．連通再介物之通路面積
第1圖：係為習用僅有一層線狀連通介物之立體組合示圖。
第2圖：係為習用僅有一層帶狀連通介物之立體組合示圖。
第3圖：係為習用僅有一層沖壓銅片連通介物之立體組合示圖。
第4圖：係為本發明之立體組合示圖。
第5圖：係為本發明第一較佳實施例立體組合示圖。
第6圖：係為本發明第二較佳實施例立體組合示圖。
第7圖：係為本發明第三較佳實施例立體組合示圖。
第8圖：係為本發明第四較佳實施例立體組合示圖。
第9圖：係為本發明第五較佳實施例立體組合示圖。
第10圖：係為本發明第六較佳實施例立體組合示圖。
4．．．晶片
5．．．導線架
6．．．連通介物
7．．．連通再介物
41．．．晶片可焊設區域
61．．．連通介物第一焊接點
42．．．第一焊設區域
62．．．連通介物第二焊接點
51．．．第二焊設區域
63．．．連通介物之通路面積
71．．．連通再介物第一焊接點
72．．．連通再介物第二焊接點
73．．．連通再介物之通路面積

Claims (2)

  1. 一種增加通路及降低電阻之電晶體連接結構，包含：至少一晶片，其上設有第一焊設區域，以供連通介物之第一焊接點焊設之；至少一導線架，其上設有第二焊設區域，以供連通介物之第二焊接點焊設之；至少一連通介物，兩端設有第一焊接點與第二焊接點，分別與晶片之第一焊設區域及導線架之第二焊設區域焊接連通之，其中，該連通介物可為帶狀或沖壓片狀之形狀者，其材質可為金或銅等導通性較佳之金屬；至少一連通再介物，兩端設有第一焊接點與第二焊接點，分別焊接於連通介物上非與晶片及導線架相焊設之一面，其中，該連通再介物可為帶狀或沖壓片狀之形狀者，其材質可為金或銅等導通性較佳之金屬；
  2. 如申請專利範圍第1項所述增加通路及降低電阻之電晶體連接結構，其中連通介物與連通再介物之層疊型態可為沖壓片層疊沖壓片、沖壓片層疊帶狀、沖壓片層疊線狀及帶狀層疊帶狀等。
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TW200714732A (en) * 2005-09-07 2007-04-16 Rohm & Haas Elect Mat Metal duplex and method
CN100423250C (zh) * 2006-10-17 2008-10-01 晶方半导体科技（苏州）有限公司 双层引线封装结构及其制造方法
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