JP6610590B2 - 半導体装置とその製造方法 - Google Patents
半導体装置とその製造方法 Download PDFInfo
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- JP6610590B2 JP6610590B2 JP2017054815A JP2017054815A JP6610590B2 JP 6610590 B2 JP6610590 B2 JP 6610590B2 JP 2017054815 A JP2017054815 A JP 2017054815A JP 2017054815 A JP2017054815 A JP 2017054815A JP 6610590 B2 JP6610590 B2 JP 6610590B2
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- groove
- solder
- grooves
- electrode plate
- metal member
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- 239000004065 semiconductor Substances 0.000 title claims description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 127
- 239000002184 metal Substances 0.000 claims description 126
- 229910052751 metal Inorganic materials 0.000 claims description 126
- 230000002093 peripheral effect Effects 0.000 claims description 39
- 239000011347 resin Substances 0.000 claims description 26
- 229920005989 resin Polymers 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 9
- 238000003892 spreading Methods 0.000 description 11
- 239000000758 substrate Substances 0.000 description 5
- 238000009736 wetting Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
12:リードフレーム
14a、14b:放熱板
16:主端子
18:信号端子
19:ボンディングワイヤー
20a、20b:IGBT
22a、22b:ダイオード
30a、30b、32a、32b:金属ブロック
40a、40b:電極板
41:第1溝
41a〜41d:直線部
42:第2溝
44:平坦面
60:樹脂層
70:信号電極
72:エミッタ電極
74:半導体基板
76:コレクタ電極
80、82、84:はんだ
Claims (7)
- 半導体装置であって、
電極板と、
金属部材と、
前記金属部材を前記電極板に接続しているはんだ、
を有しており、
前記電極板の表面に、
矩形の各辺に沿って伸びる第1直線部分、第2直線部分、第3直線部分及び第4直線部分を有するとともに環状に伸びる第1溝と、
前記第1溝に囲まれた範囲内に配置されており、外周側の端部が前記第1溝に接続されている第2溝群、
が設けられており、
前記第2溝群が、
前記第1直線部分に接続されている複数の前記第2溝を備える第1セットと、
前記第2直線部分に接続されている複数の前記第2溝を備える第2セットと、
前記第3直線部分に接続されている複数の前記第2溝を備える第3セットと、
前記第4直線部分に接続されている複数の前記第2溝を備える第4セット、
を有しており、
前記はんだが、前記範囲と、前記範囲に対向する前記金属部材の表面とを接続しており、
前記電極板と前記金属部材の積層方向に沿って見たときに、前記金属部材の前記はんだに接続されている領域の外周縁が、前記第1セットが備える複数の前記第2溝のそれぞれ、前記第2セットが備える複数の前記第2溝のそれぞれ、前記第3セットが備える複数の前記第2溝のそれぞれ、及び、前記第4セットが備える複数の前記第2溝のそれぞれを横切るように配置されている半導体装置。 - 前記電極板が、前記範囲の中央に、前記第2溝群が存在しない平坦面を備える請求項1の半導体装置。
- 前記第2溝の各々が、前記第1溝を除いて、他の前記第2溝に繋がっておらず、
前記はんだが樹脂に覆われている、
請求項1または2の半導体装置。 - 前記第2溝の各々が、前記第1溝に対して垂直に接続されている請求項1〜3のいずれか一項の半導体装置。
- 前記電極板と反対側の前記金属部材の表面に、はんだを介して半導体チップが接続されている請求項1〜4のいずれか一項の半導体装置。
- 前記金属部材が、半導体チップの表面電極である請求項1〜4のいずれか一項の半導体装置。
- 半導体装置の製造方法であって、
はんだを介して金属部材を電極板に接続する工程を有しており、
前記電極板の表面に、
矩形の各辺に沿って伸びる第1直線部分、第2直線部分、第3直線部分及び第4直線部分を有するとともに環状に伸びる第1溝と、
前記第1溝に囲まれた範囲内に配置されており、外周側の端部が前記第1溝に接続されている第2溝群、
が設けられており、
前記第2溝群が、
前記第1直線部分に接続されている複数の第2溝を備える第1セットと、
前記第2直線部分に接続されている複数の第2溝を備える第2セットと、
前記第3直線部分に接続されている複数の第2溝を備える第3セットと、
前記第4直線部分に接続されている複数の第2溝を備える第4セット、
を有しており、
前記工程では、前記範囲と前記金属部材とを対向させ、前記電極板と前記金属部材の積層方向に沿って見たときに前記金属部材の前記はんだに接続される領域の外周縁が前記第1セットが備える複数の前記第2溝のそれぞれ、前記第2セットが備える複数の前記第2溝のそれぞれ、前記第3セットが備える複数の前記第2溝のそれぞれ、及び、前記第4セットが備える複数の前記第2溝のそれぞれを横切るように配置した状態で、前記範囲と前記領域とをはんだで接続する、製造方法。
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JP2017054815A JP6610590B2 (ja) | 2017-03-21 | 2017-03-21 | 半導体装置とその製造方法 |
KR1020180030630A KR102073579B1 (ko) | 2017-03-21 | 2018-03-16 | 반도체 장치와 그 제조 방법 및 전극판 |
US15/923,018 US10475727B2 (en) | 2017-03-21 | 2018-03-16 | Semiconductor device, manufacturing method for semiconductor device, and electrode plate |
TW107109216A TWI676251B (zh) | 2017-03-21 | 2018-03-19 | 半導體裝置、半導體裝置的製造方法及電極板 |
CN201810224113.8A CN108630652B (zh) | 2017-03-21 | 2018-03-19 | 半导体装置、用于半导体装置的制造方法以及电极板 |
EP18162560.9A EP3379572B1 (en) | 2017-03-21 | 2018-03-19 | Semiconductor device, manufacturing method for semiconductor device, and electrode plate |
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JP6834815B2 (ja) * | 2017-07-06 | 2021-02-24 | 株式会社デンソー | 半導体モジュール |
WO2019116457A1 (ja) * | 2017-12-13 | 2019-06-20 | 三菱電機株式会社 | 半導体装置及び電力変換装置 |
US20220415745A1 (en) * | 2021-06-29 | 2022-12-29 | Infineon Technologies Ag | Semiconductor packages including recesses to contain solder |
JP2023041490A (ja) * | 2021-09-13 | 2023-03-24 | 株式会社東芝 | 半導体装置 |
JP7292352B2 (ja) * | 2021-11-02 | 2023-06-16 | 三菱電機株式会社 | 樹脂封止型半導体装置及び樹脂封止型半導体装置の製造方法 |
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TWI247642B (en) * | 2005-03-15 | 2006-01-21 | Jian-Shian Li | Position-actuating and controlling device for direct movement of electrode of electro-discharge machine |
JP4702196B2 (ja) * | 2005-09-12 | 2011-06-15 | 株式会社デンソー | 半導体装置 |
US7661954B2 (en) * | 2005-09-13 | 2010-02-16 | Uwe Harneit | Gas burner |
JP5002148B2 (ja) * | 2005-11-24 | 2012-08-15 | 株式会社東芝 | 半導体装置 |
JP4893303B2 (ja) * | 2006-12-29 | 2012-03-07 | 株式会社デンソー | 半導体装置 |
US8481368B2 (en) * | 2008-03-31 | 2013-07-09 | Alpha & Omega Semiconductor, Inc. | Semiconductor package of a flipped MOSFET and its manufacturing method |
JP2013123016A (ja) * | 2011-12-12 | 2013-06-20 | Denso Corp | 半導体装置 |
JP2014029967A (ja) * | 2012-07-31 | 2014-02-13 | Toshiba Lighting & Technology Corp | 半導体装置及びその製造方法 |
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US10475727B2 (en) | 2019-11-12 |
TW201838122A (zh) | 2018-10-16 |
JP2018157157A (ja) | 2018-10-04 |
EP3379572A1 (en) | 2018-09-26 |
US20180277462A1 (en) | 2018-09-27 |
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