JP7156172B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP7156172B2 JP7156172B2 JP2019097019A JP2019097019A JP7156172B2 JP 7156172 B2 JP7156172 B2 JP 7156172B2 JP 2019097019 A JP2019097019 A JP 2019097019A JP 2019097019 A JP2019097019 A JP 2019097019A JP 7156172 B2 JP7156172 B2 JP 7156172B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- heat sink
- groove
- solder
- bonding material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
12、112:半導体素子
12a、12b、112a、112b:主電極
12c:信号電極
14、114:下側放熱板
16、116:上側放熱板
16c、116c:スペーサ部
18、118:封止体
20、22、120、122:はんだ
114d、116d:第1溝
114e、116e:第2溝
A1:第1領域
A2:第2領域
BL:第1領域と第2領域との間の境界
PE:半導体素子の周縁
W:半導体素子の周縁と境界との間隔
Claims (1)
- 半導体素子と、
前記半導体素子に第1接合材を介して接合された第1導体板と、
前記第1導体板と前記半導体素子を挟んで対向するとともに、第2接合材を介して前記半導体素子に接合された第2導体板と、を備え、
前記第1導体板と前記第2導体板の少なくとも一方の一表面には、前記第1接合材又は前記第2接合材に接触しているとともに、前記第1接合材又は前記第2接合材の周縁に沿って延びる第1溝が設けられており、
前記第1溝の内面には、前記第1溝の長手方向に沿って延びるとともに前記第1溝よりも断面積の小さい第2溝が設けられている、
半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019097019A JP7156172B2 (ja) | 2019-05-23 | 2019-05-23 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019097019A JP7156172B2 (ja) | 2019-05-23 | 2019-05-23 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020191417A JP2020191417A (ja) | 2020-11-26 |
JP7156172B2 true JP7156172B2 (ja) | 2022-10-19 |
Family
ID=73454744
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019097019A Active JP7156172B2 (ja) | 2019-05-23 | 2019-05-23 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP7156172B2 (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3008242U (ja) | 1994-08-25 | 1995-03-07 | 日本インター株式会社 | 半導体ペレット搭載基板 |
JP2007103909A (ja) | 2005-09-12 | 2007-04-19 | Denso Corp | 半導体装置 |
JP2008207207A (ja) | 2007-02-26 | 2008-09-11 | Fuji Electric Device Technology Co Ltd | 半田接合方法およびそれを用いた半導体装置の製造方法 |
JP2012084686A (ja) | 2010-10-12 | 2012-04-26 | Toyota Industries Corp | 配線部材間の接続構造 |
-
2019
- 2019-05-23 JP JP2019097019A patent/JP7156172B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3008242U (ja) | 1994-08-25 | 1995-03-07 | 日本インター株式会社 | 半導体ペレット搭載基板 |
JP2007103909A (ja) | 2005-09-12 | 2007-04-19 | Denso Corp | 半導体装置 |
JP2008207207A (ja) | 2007-02-26 | 2008-09-11 | Fuji Electric Device Technology Co Ltd | 半田接合方法およびそれを用いた半導体装置の製造方法 |
JP2012084686A (ja) | 2010-10-12 | 2012-04-26 | Toyota Industries Corp | 配線部材間の接続構造 |
Also Published As
Publication number | Publication date |
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JP2020191417A (ja) | 2020-11-26 |
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