JP2019079891A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2019079891A JP2019079891A JP2017204796A JP2017204796A JP2019079891A JP 2019079891 A JP2019079891 A JP 2019079891A JP 2017204796 A JP2017204796 A JP 2017204796A JP 2017204796 A JP2017204796 A JP 2017204796A JP 2019079891 A JP2019079891 A JP 2019079891A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- heat sink
- solder
- signal
- signal terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
12:リードフレーム
14、15、114、214、314、315:信号端子
14a、15a、114a、214a、314a、315a:凹部
14b、15b、114b、214b、314b、315b:接合部
14c、314c、315c:エッジ
16、17、18、116、216、316、317、318:電力用端子
20、40、120、220、320、340:半導体素子
20a、40a、120a、220a、320a、340a:上面電極
20b、40b、120b、220b、320b、340b:下面電極
20c、40c、120c、220c、320c、340c:信号パッド
22、42、122、222、322、342:上側ヒートシンク
22c、42c、322c、342c:スペーサ部
24、44、124、224、324、:下側ヒートシンク
30、130、230、330:モールド樹脂
52、54、56、152、154、156、252、254、256、258、352、353、354、355、356、357:はんだ
56':予備はんだ
70、80:位置決め治具
82:ガイドピン
128:導体板
226:導体スペーサ
Claims (1)
- 信号端子と
前記信号端子にはんだ層を介して接合される信号パッドを有する半導体素子と、
を備え、
前記信号端子には、凹部が設けられており、
前記凹部は、前記信号端子と前記はんだ層との接合部に隣接するとともに、前記半導体素子に対向する範囲に位置している、
半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017204796A JP2019079891A (ja) | 2017-10-23 | 2017-10-23 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017204796A JP2019079891A (ja) | 2017-10-23 | 2017-10-23 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2019079891A true JP2019079891A (ja) | 2019-05-23 |
Family
ID=66628005
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017204796A Pending JP2019079891A (ja) | 2017-10-23 | 2017-10-23 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2019079891A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021097113A (ja) * | 2019-12-16 | 2021-06-24 | 株式会社デンソー | 半導体装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55117859U (ja) * | 1979-02-14 | 1980-08-20 | ||
US20080237814A1 (en) * | 2007-03-26 | 2008-10-02 | National Semiconductor Corporation | Isolated solder pads |
KR20150002420U (ko) * | 2015-04-23 | 2015-06-22 | 제엠제코(주) | 반도체 패키지 |
-
2017
- 2017-10-23 JP JP2017204796A patent/JP2019079891A/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55117859U (ja) * | 1979-02-14 | 1980-08-20 | ||
US20080237814A1 (en) * | 2007-03-26 | 2008-10-02 | National Semiconductor Corporation | Isolated solder pads |
KR20150002420U (ko) * | 2015-04-23 | 2015-06-22 | 제엠제코(주) | 반도체 패키지 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021097113A (ja) * | 2019-12-16 | 2021-06-24 | 株式会社デンソー | 半導体装置 |
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