JP2020191417A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2020191417A JP2020191417A JP2019097019A JP2019097019A JP2020191417A JP 2020191417 A JP2020191417 A JP 2020191417A JP 2019097019 A JP2019097019 A JP 2019097019A JP 2019097019 A JP2019097019 A JP 2019097019A JP 2020191417 A JP2020191417 A JP 2020191417A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- heat radiating
- region
- radiating plate
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
12、112:半導体素子
12a、12b、112a、112b:主電極
12c:信号電極
14、114:下側放熱板
16、116:上側放熱板
16c、116c:スペーサ部
18、118:封止体
20、22、120、122:はんだ
114d、116d:第1溝
114e、116e:第2溝
A1:第1領域
A2:第2領域
BL:第1領域と第2領域との間の境界
PE:半導体素子の周縁
W:半導体素子の周縁と境界との間隔
Claims (2)
- 半導体素子と、
前記半導体素子に第1接合材を介して接合された第1導体板と、
前記第1導体板と前記半導体素子を挟んで対向するとともに、前記第2接合材を介して前記半導体素子に接合された第2導体板と、を備え、
前記第1導体板の一表面は、その少なくとも一部が前記第1接合材と接触する第1領域と、前記第1領域を取り囲むとともに前記第1領域よりも前記第1接合材に対する親和性が低い第2領域とを有し、
前記半導体素子が接合された前記第1導体板の前記一表面を平面視したときに、前記第1領域と前記第2領域との間の境界は、前記半導体素子の周縁を取り囲むとともに、前記半導体素子の前記周縁と前記境界との間の間隔は、前記半導体素子の前記周縁に沿って部分的に拡大されている、
半導体装置。 - 半導体素子と、
前記半導体素子に第1接合材を介して接合された第1導体板と、
前記第1導体板と前記半導体素子を挟んで対向するとともに、前記第2接合材を介して前記半導体素子に接合された第2導体板と、を備え、
前記第1導体板と前記第2導体板の少なくとも一方の一表面には、前記第1接合材又は前記第2接合材に接触しているとともに、前記第1接合材又は前記第2接合材の周縁に沿って延びる第1溝が設けられており、
前記第1溝の内面には、前記第1溝の長手方向に沿って延びるとともに前記第1溝よりも断面積の小さい第2溝が設けられている、
半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019097019A JP7156172B2 (ja) | 2019-05-23 | 2019-05-23 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019097019A JP7156172B2 (ja) | 2019-05-23 | 2019-05-23 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020191417A true JP2020191417A (ja) | 2020-11-26 |
JP7156172B2 JP7156172B2 (ja) | 2022-10-19 |
Family
ID=73454744
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019097019A Active JP7156172B2 (ja) | 2019-05-23 | 2019-05-23 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP7156172B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7489181B2 (ja) | 2019-11-11 | 2024-05-23 | 株式会社 日立パワーデバイス | 半導体装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3008242U (ja) * | 1994-08-25 | 1995-03-07 | 日本インター株式会社 | 半導体ペレット搭載基板 |
JP2007103909A (ja) * | 2005-09-12 | 2007-04-19 | Denso Corp | 半導体装置 |
JP2008207207A (ja) * | 2007-02-26 | 2008-09-11 | Fuji Electric Device Technology Co Ltd | 半田接合方法およびそれを用いた半導体装置の製造方法 |
JP2012084686A (ja) * | 2010-10-12 | 2012-04-26 | Toyota Industries Corp | 配線部材間の接続構造 |
-
2019
- 2019-05-23 JP JP2019097019A patent/JP7156172B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3008242U (ja) * | 1994-08-25 | 1995-03-07 | 日本インター株式会社 | 半導体ペレット搭載基板 |
JP2007103909A (ja) * | 2005-09-12 | 2007-04-19 | Denso Corp | 半導体装置 |
JP2008207207A (ja) * | 2007-02-26 | 2008-09-11 | Fuji Electric Device Technology Co Ltd | 半田接合方法およびそれを用いた半導体装置の製造方法 |
JP2012084686A (ja) * | 2010-10-12 | 2012-04-26 | Toyota Industries Corp | 配線部材間の接続構造 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7489181B2 (ja) | 2019-11-11 | 2024-05-23 | 株式会社 日立パワーデバイス | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP7156172B2 (ja) | 2022-10-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101922783B1 (ko) | 베이스판, 및 베이스판을 구비한 반도체 장치 | |
WO2015111691A1 (ja) | 電極端子、電力用半導体装置、および電力用半導体装置の製造方法 | |
JP4893303B2 (ja) | 半導体装置 | |
WO2017195625A1 (ja) | 半導体装置および半導体装置の製造方法 | |
WO2018179981A1 (ja) | 半導体装置 | |
US9415455B2 (en) | Semiconductor device and semiconductor device manufacturing method | |
JP6610590B2 (ja) | 半導体装置とその製造方法 | |
WO2015107879A1 (ja) | 半導体装置及びその製造方法 | |
JP2015188026A (ja) | 電力用半導体装置、および電力用半導体装置の製造方法 | |
CN111952270A (zh) | 半导体装置 | |
JP5869285B2 (ja) | 半導体装置 | |
JP7156172B2 (ja) | 半導体装置 | |
JP7271381B2 (ja) | 半導体装置 | |
JP2019083294A (ja) | 半導体装置とその製造方法 | |
JP2019212808A (ja) | 半導体装置の製造方法 | |
US10847448B2 (en) | Semiconductor device and method of manufacturing the same | |
JP6311568B2 (ja) | 電子装置 | |
US9620442B2 (en) | Semiconductor device | |
JP7095641B2 (ja) | 半導体装置 | |
JP6063835B2 (ja) | 半導体チップの実装方法、半導体装置、及び実装治具 | |
JP7322467B2 (ja) | 半導体装置 | |
JP2019016658A (ja) | 光モジュールおよび光モジュールの製造方法 | |
JP7106891B2 (ja) | 半導体装置 | |
TW202238888A (zh) | 半導體裝置 | |
JP2022085083A (ja) | 半導体装置および半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20200720 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210823 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20220613 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20220621 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220817 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20220906 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20220919 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 7156172 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |