JP2020191417A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2020191417A
JP2020191417A JP2019097019A JP2019097019A JP2020191417A JP 2020191417 A JP2020191417 A JP 2020191417A JP 2019097019 A JP2019097019 A JP 2019097019A JP 2019097019 A JP2019097019 A JP 2019097019A JP 2020191417 A JP2020191417 A JP 2020191417A
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semiconductor element
heat radiating
region
radiating plate
groove
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JP7156172B2 (en
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崇功 川島
Takayoshi Kawashima
崇功 川島
温子 山中
Atsuko Yamanaka
温子 山中
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

To disclose a technology for taking countermeasures for an excess bonding material.SOLUTION: A semiconductor device according to the present disclosure comprises: a semiconductor element; a first conductor plate that is bonded to the semiconductor element through a first bonding material; and a second conductor plate that is bonded to the semiconductor element through a second bonding material. According to an aspect of the present disclosure, a surface of the first conductor plate has a first region that contacts with the first bonding material, and a second region that surrounds the first region and that has lower affinity to the first bonding material than the first region. In a plan view, a boundary between the first region and the second region surrounds a circumference of the semiconductor element, and a space between the circumference of the semiconductor element and the boundary is partially expanded along the circumference of the semiconductor element.SELECTED DRAWING: Figure 2

Description

本明細書が開示する技術は、半導体装置に関する。 The techniques disclosed herein relate to semiconductor devices.

特許文献１に、半導体装置が開示されている。この半導体装置は、半導体素子と、半導体素子に接合材を介して接合された第１導体板と、第１導体板と半導体素子を挟んで対向するとともに、接合材を介して半導体素子に接合された第２導体板とを備える。 Patent Document 1 discloses a semiconductor device. This semiconductor device faces the semiconductor element, the first conductor plate bonded to the semiconductor element via the bonding material, the first conductor plate and the semiconductor element with the semiconductor element sandwiched between them, and is bonded to the semiconductor element via the bonding material. A second conductor plate is provided.

特開２００９−１４６９５０号公報JP-A-2009-146950

上記のような半導体装置の製造工程では、接合材（例えば、はんだ）によって半導体素子と導体板との間を接合するときに、半導体素子と導体板との間から余剰なはんだが溢れ出ることがある。そのことから、そのような余剰な接合材を受け入れるために、第１導体板又は第２導体板に溝が設けられることがある。この場合、余剰な接合材の量に対して、それを受け入れる溝のサイズが不十分であると、余剰な接合材が溝を越えて過剰に濡れ広がってしまう。しかしながら、余剰な接合材の量に対して、溝のサイズが大きすぎると、溝の一部に偏って余剰な接合材が流れ込み、それに伴って第１導体板又は第２導体板に対する半導体素子の位置が、意図せず変化するおそれがある。工業製品である半導体装置には、製造誤差その他の個体差が必ず存在し、余剰な接合材の量や挙動も様々に変化し得る。本明細書では、そのような余剰な接合材に対策を講じるための技術が開示される。 In the manufacturing process of the semiconductor device as described above, when the semiconductor element and the conductor plate are joined by a bonding material (for example, solder), excess solder may overflow between the semiconductor element and the conductor plate. is there. Therefore, in order to receive such a surplus bonding material, a groove may be provided in the first conductor plate or the second conductor plate. In this case, if the size of the groove that receives the excess bonding material is insufficient with respect to the amount of the excess bonding material, the excess bonding material will be excessively wet and spread over the groove. However, if the size of the groove is too large with respect to the amount of the excess bonding material, the excess bonding material will flow into a part of the groove, and the semiconductor element with respect to the first conductor plate or the second conductor plate will be accompanied by the excess bonding material. The position may change unintentionally. Semiconductor devices, which are industrial products, always have manufacturing errors and other individual differences, and the amount and behavior of excess bonding material can change in various ways. The present specification discloses techniques for taking measures against such surplus bonding materials.

本開示の第１の側面により、半導体装置が具現化される。この半導体装置は、半導体素子と、半導体素子に第１接合材を介して接合された第１導体板と、第１導体板と半導体素子を挟んで対向するとともに、第２接合材を介して半導体素子に接合された第２導体板とを備える。第１導体板の一表面は、その少なくとも一部が第１接合材と接触する第１領域と、第１領域を取り囲むとともに第１領域よりも第１接合材に対する親和性が低い第２領域とを有する。半導体素子が接合された第１導体板の一表面を平面視したときに、第１領域と第２領域との間の境界は、半導体素子の周縁を取り囲むとともに、半導体素子の周縁と境界との間の間隔は、半導体素子の周縁に沿って部分的に拡大されている。 A semiconductor device is embodied by the first aspect of the present disclosure. This semiconductor device faces the semiconductor element, the first conductor plate bonded to the semiconductor element via the first bonding material, the first conductor plate and the semiconductor element with the semiconductor element interposed therebetween, and the semiconductor via the second bonding material. It includes a second conductor plate joined to the element. One surface of the first conductor plate includes a first region in which at least a part thereof contacts the first bonding material, and a second region that surrounds the first region and has a lower affinity for the first bonding material than the first region. Has. When one surface of the first conductor plate to which the semiconductor element is bonded is viewed in a plan view, the boundary between the first region and the second region surrounds the peripheral edge of the semiconductor element and is connected to the peripheral edge and the boundary of the semiconductor element. The spacing between them is partially extended along the periphery of the semiconductor device.

上記した半導体装置では、第１導体板の一表面が、第１接合材と接触する第１領域と、第１領域を取り囲むとともに第１領域よりも第１接合材に対する親和性が低い第２領域とを有する。このような構成によると、第１導体板と半導体素子との間から溢れ出た余剰な接合材は、主に第１領域において濡れ広がり、第２領域へ濡れ広がることが抑制される。即ち、余剰な接合材の濡れ広がりは、第１領域と第２領域との間の境界によって制限又は抑制される。このとき、第１領域と第２領域との間の境界が、半導体素子の周縁に近接して設けられていると、余剰な接合材の量に対して、第１領域の面積が不足するおそれがある。この場合、余剰な接合材が当該領域を越えてしまい、意図しない範囲へ濡れ広がるおそれがある。それに対して、第１領域と第２領域との間の境界が、半導体素子の周縁から離れて設けられていると、第１領域の一部に偏って余剰な接合材が流れ込むことによって、第１導体板に対する半導体素子の位置が意図せず変化するおそれがある。この点に関して、上記した半導体装置では、第１領域と第２領域との間の境界が、半導体素子の周縁を取り囲むとともに、半導体素子の周縁と当該境界との間の間隔は、半導体素子の周縁に沿って部分的に拡大されている。このような構成によると、第１導体板に対する半導体素子の位置ずれを抑制しつつ、半導体素子の周縁と境界との間の間隔が拡大された領域に、余剰な接合材を受け入れることができる。 In the above-mentioned semiconductor device, one surface of the first conductor plate surrounds the first region in contact with the first bonding material and the second region having a lower affinity for the first bonding material than the first region. And have. According to such a configuration, the excess bonding material overflowing between the first conductor plate and the semiconductor element is prevented from spreading wet and spreading mainly in the first region and spreading to the second region. That is, the wet spread of the excess bonding material is limited or suppressed by the boundary between the first region and the second region. At this time, if the boundary between the first region and the second region is provided close to the peripheral edge of the semiconductor element, the area of the first region may be insufficient with respect to the amount of excess bonding material. There is. In this case, the excess bonding material may exceed the region and wet and spread to an unintended range. On the other hand, if the boundary between the first region and the second region is provided apart from the peripheral edge of the semiconductor element, the excess bonding material flows into a part of the first region, so that the first region becomes the first. 1 The position of the semiconductor element with respect to the conductor plate may change unintentionally. In this regard, in the above-mentioned semiconductor device, the boundary between the first region and the second region surrounds the peripheral edge of the semiconductor element, and the distance between the peripheral edge of the semiconductor element and the boundary is the peripheral edge of the semiconductor element. Partially enlarged along. According to such a configuration, the surplus bonding material can be accepted in the region where the distance between the peripheral edge and the boundary of the semiconductor element is expanded while suppressing the displacement of the semiconductor element with respect to the first conductor plate.

本開示の第２の側面により、次の半導体装置も具現化される。この半導体装置は、半導体素子と、半導体素子に第１接合材を介して接合された第１導体板と、第１導体板と半導体素子を挟んで対向するとともに、第２接合材を介して半導体素子に接合された第２導体板とを備える。第１導体板と第２導体板の少なくとも一方の一表面は、第１接合材又は第２接合材に接触しているとともに、第１接合材又は第２接合材の周縁に沿って延びる第１溝が設けられている。第１溝の内面には、第１溝の長手方向に沿って延びるとともに第１溝よりも断面積の小さい第２溝が設けられている。 The following semiconductor devices are also embodied by the second aspect of the present disclosure. This semiconductor device faces the semiconductor element, the first conductor plate bonded to the semiconductor element via the first bonding material, the first conductor plate and the semiconductor element with the semiconductor element interposed therebetween, and the semiconductor via the second bonding material. It includes a second conductor plate joined to the element. A first surface of at least one of the first conductor plate and the second conductor plate is in contact with the first joint material or the second joint material and extends along the peripheral edge of the first joint material or the second joint material. A groove is provided. The inner surface of the first groove is provided with a second groove extending along the longitudinal direction of the first groove and having a cross-sectional area smaller than that of the first groove.

上記した半導体装置では、第１導体板と第２導体板の少なくとも一方に、第１溝が設けられている。この第１溝は、第１接合材又は第２接合材に接触する一表面に設けられているとともに、第１接合材又は第２接合材の周縁に沿って延びている。このような構成によると、半導体素子と第１導体板又は第２導体板とが接合されるときに、余剰な第１接合材又は第２接合材を第１溝に収容することができる。さらに、第１溝の内面には、第１溝の長手方向に沿って延びるとともに第１溝よりも断面積の小さい第２溝が設けられている。これにより、第１溝に収容された第１接合材又は第２接合材は、第２溝における表面張力によって誘導されることで、第１溝の全体に亘って濡れ広がることができる。従って、第１溝が比較的に小さい場合でも、余剰な第１接合材又は第２接合材を第１溝の全体で速やかに収容することができ、余剰な第１接合材又は第２接合材が第１溝を越えて過剰に濡れ広がることが防止される。 In the above-mentioned semiconductor device, a first groove is provided on at least one of the first conductor plate and the second conductor plate. The first groove is provided on one surface in contact with the first joint material or the second joint material, and extends along the peripheral edge of the first joint material or the second joint material. According to such a configuration, when the semiconductor element and the first conductor plate or the second conductor plate are joined, the surplus first joining material or the second joining material can be accommodated in the first groove. Further, the inner surface of the first groove is provided with a second groove extending along the longitudinal direction of the first groove and having a cross-sectional area smaller than that of the first groove. As a result, the first joint material or the second joint material housed in the first groove can be wetted and spread over the entire first groove by being guided by the surface tension in the second groove. Therefore, even when the first groove is relatively small, the surplus first joint material or the second joint material can be quickly accommodated in the entire first groove, and the surplus first joint material or the second joint material can be accommodated. Is prevented from being excessively wet and spread beyond the first groove.

実施例１の半導体装置１０の内部構造を示す断面図。FIG. 5 is a cross-sectional view showing the internal structure of the semiconductor device 10 of the first embodiment. 下側放熱板１４上に半導体素子１２が配置されている状態を示す平面図。The plan view which shows the state which the semiconductor element 12 is arranged on the lower heat radiation plate 14. 実施例１の製造方法における第１リフロー工程を説明する断面図。The cross-sectional view explaining the 1st reflow process in the manufacturing method of Example 1. FIG. 実施例１の製造方法における第２リフロー工程を説明する断面図。The cross-sectional view explaining the 2nd reflow process in the manufacturing method of Example 1. FIG. 下側放熱板１４のいくつかの変形例を示す平面図。実施例１と変形例の下側放熱板１４のサイズ比較のために、実施例１の下側放熱板１４の周縁を破線で示している。The plan view which shows some modification of the lower heat dissipation plate 14. In order to compare the sizes of the lower heat radiating plate 14 of the first embodiment and the modified example, the peripheral edge of the lower heat radiating plate 14 of the first embodiment is shown by a broken line. 実施例２の半導体装置１００の内部構造を示す断面図。FIG. 5 is a cross-sectional view showing the internal structure of the semiconductor device 100 of the second embodiment. 上側放熱板１１６の第２主表面側１１６ｂの詳細を説明する平面図。説明を明確にするために、上側放熱板１１６に濡れ広がったはんだをドットで図示している。The plan view explaining the details of the 2nd main surface side 116b of the upper heat dissipation plate 116. For clarity of explanation, the solder that has spread on the upper heat radiating plate 116 is shown by dots. 実施例２の製造方法における第１リフロー工程を説明する断面図。The cross-sectional view explaining the 1st reflow process in the manufacturing method of Example 2. FIG. 実施例２の製造方法における第２リフロー工程を説明する断面図。The cross-sectional view explaining the 2nd reflow process in the manufacturing method of Example 2. FIG. 上側放熱板１１６のいくつかの変形例を示す断面図。FIG. 5 is a cross-sectional view showing some modifications of the upper heat radiating plate 116. 半導体装置１００の一変形例を示す断面図。FIG. 5 is a cross-sectional view showing a modification of the semiconductor device 100. 半導体装置１００の他の一変形例を示す断面図。FIG. 5 is a cross-sectional view showing another modification of the semiconductor device 100.

（実施例１）図１−５を参照して、実施例１の半導体装置１０及びその製造方法について説明する。図１に示すように、半導体装置１０は、半導体素子１２と、下側放熱板１４と、上側放熱板１６と、封止体１８とを備える。半導体素子１２は、封止体１８の内部に封止されている。封止体１８は、例えばエポキシ樹脂といった絶縁性を有する材料を用いて構成されている。封止体１８は、概して板形状を有しており、互いに反対側に位置する二つの主表面を有する。一方の主表面には下側放熱板１４が露出しており、他方の主表面には上側放熱板１６が露出している。下側放熱板１４及び上側放熱板１６は、封止体１８の内部において半導体素子１２と電気的及び熱的に接続されている。これにより、下側放熱板１４及び上側放熱板１６は、半導体素子１２に接続された電気回路の一部を構成するとともに、半導体素子１２の熱を外部へ放熱する放熱板として機能する。ここで、下側放熱板１４は、本開示の第１の側面における第１導体板の一例であり、上側放熱板１６は、本開示の第１の側面における第２導体板の一例である。 (Example 1) The semiconductor device 10 of the first embodiment and a method for manufacturing the same will be described with reference to FIGS. 1-5. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor element 12, a lower heat radiating plate 14, an upper heat radiating plate 16, and a sealing body 18. The semiconductor element 12 is sealed inside the sealing body 18. The sealing body 18 is constructed by using a material having an insulating property such as an epoxy resin. The sealant 18 has a generally plate shape and has two main surfaces located on opposite sides of each other. The lower heat radiating plate 14 is exposed on one main surface, and the upper heat radiating plate 16 is exposed on the other main surface. The lower heat radiating plate 14 and the upper heat radiating plate 16 are electrically and thermally connected to the semiconductor element 12 inside the sealing body 18. As a result, the lower heat radiating plate 14 and the upper heat radiating plate 16 form a part of the electric circuit connected to the semiconductor element 12, and also function as a heat radiating plate that radiates the heat of the semiconductor element 12 to the outside. Here, the lower heat radiating plate 14 is an example of the first conductor plate on the first side surface of the present disclosure, and the upper heat radiating plate 16 is an example of the second conductor plate on the first side surface of the present disclosure.

図１、２に示すように、半導体素子１２は、主に半導体基板で構成されているとともに、一対の主電極１２ａ、１２ｂと、複数の信号電極１２ｃをさらに有する。一対の主電極１２ａ、１２ｂには、第１主電極１２ａと第２主電極１２ｂが含まれている。第１主電極１２ａ及び複数の信号電極１２ｃは、半導体素子１２の一方の表面に位置しており、第２主電極１２ｂは、半導体素子１２の他方の表面に位置している。一対の主電極１２ａ、１２ｂは、半導体基板を介して電気的に接続される。信号電極１２ｃは、不図示の信号端子に電気的に接続される。 As shown in FIGS. 1 and 2, the semiconductor element 12 is mainly composed of a semiconductor substrate, and further has a pair of main electrodes 12a and 12b and a plurality of signal electrodes 12c. The pair of main electrodes 12a and 12b includes a first main electrode 12a and a second main electrode 12b. The first main electrode 12a and the plurality of signal electrodes 12c are located on one surface of the semiconductor element 12, and the second main electrode 12b is located on the other surface of the semiconductor element 12. The pair of main electrodes 12a and 12b are electrically connected via a semiconductor substrate. The signal electrode 12c is electrically connected to a signal terminal (not shown).

半導体素子１２は、パワー半導体素子であって、例えば、ＩＧＢＴ（Insulated Gate Bipolar Transistor）である。但し、半導体素子１２はＩＧＢＴに限られず、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）又はダイオードであってもよい。なお、半導体素子の数や種類については、特に限定されない。半導体素子１２を構成する半導体材料には、例えばケイ素（Ｓｉ）、炭化ケイ素（ＳｉＣ）、窒化ガリウム（ＧａＮ）又は他の種類の半導体材料を採用することができる。 The semiconductor element 12 is a power semiconductor element, for example, an IGBT (Insulated Gate Bipolar Transistor). However, the semiconductor element 12 is not limited to the IGBT, and may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or a diode. The number and types of semiconductor elements are not particularly limited. As the semiconductor material constituting the semiconductor element 12, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN) or other types of semiconductor materials can be adopted.

下側放熱板１４及び上側放熱板１６は、半導体素子１２を挟んで対向している。下側放熱板１４は、概して板形状又は直方体形状を有しており、例えば銅又は他の金属といった導体材料を用いて形成されている。下側放熱板１４は、第１主表面１４ａと、その反対側に位置する第２主表面１４ｂを有している。下側放熱板１４の第１主表面１４ａは、半導体素子１２の第２主電極１２ｂにはんだ２０を介して接合される。これにより、下側放熱板１４は、半導体素子１２と電気的及び熱的に接続されている。一方、下側放熱板１４の第２主表面１４ｂは、封止体１８の一方の表面において露出されている。 The lower heat radiating plate 14 and the upper heat radiating plate 16 face each other with the semiconductor element 12 interposed therebetween. The lower heat radiating plate 14 generally has a plate shape or a rectangular parallelepiped shape, and is formed by using a conductor material such as copper or other metal. The lower heat radiating plate 14 has a first main surface 14a and a second main surface 14b located on the opposite side thereof. The first main surface 14a of the lower heat radiating plate 14 is bonded to the second main electrode 12b of the semiconductor element 12 via the solder 20. As a result, the lower heat radiating plate 14 is electrically and thermally connected to the semiconductor element 12. On the other hand, the second main surface 14b of the lower heat radiating plate 14 is exposed on one surface of the sealing body 18.

上側放熱板１６も、下側放熱板１４と同様に、概して板形状又は直方体形状を有しており、例えば銅又は他の金属といった導体材料を用いて形成されている。上側放熱板１６は、第１主表面１６ａと、その反対側に位置する第２主表面１６ｂとを有している。上側放熱板１６には、半導体素子１２と向かい合う範囲において、第２主表面１６ｂから半導体素子１２に向かって突出するスペーサ部１６ｃが設けられている。このスペーサ部１６ｃにおいて、上側放熱板１６は、下側放熱板１４とは異なっている。このスペーサ部１６ｃによって、半導体装置１０の製造工程における組付け作業を一部簡素化することもできる。上側放熱板１６の第１主表面１６ａは、封止体１８の他方の表面において露出されている。上側放熱板１６は、第２主表面１６ｂのスペーサ部１６ｃにおける頂面部分において半導体素子１２の第１主電極１２ａにはんだ２２を介して接合されている。これにより、上側放熱板１６は、半導体素子１２と電気的及び熱的に接続されている。 The upper heat radiating plate 16 also generally has a plate shape or a rectangular parallelepiped shape like the lower heat radiating plate 14, and is formed by using a conductor material such as copper or other metal. The upper heat radiating plate 16 has a first main surface 16a and a second main surface 16b located on the opposite side thereof. The upper heat radiating plate 16 is provided with a spacer portion 16c that projects from the second main surface 16b toward the semiconductor element 12 in a range facing the semiconductor element 12. In the spacer portion 16c, the upper heat radiating plate 16 is different from the lower heat radiating plate 14. The spacer portion 16c can also partially simplify the assembly work in the manufacturing process of the semiconductor device 10. The first main surface 16a of the upper heat radiating plate 16 is exposed on the other surface of the sealing body 18. The upper heat radiating plate 16 is bonded to the first main electrode 12a of the semiconductor element 12 via solder 22 at the top surface portion of the spacer portion 16c of the second main surface 16b. As a result, the upper heat radiating plate 16 is electrically and thermally connected to the semiconductor element 12.

はんだ２０及びはんだ２２は、本開示の第１の側面における第１接合材及び第２接合材のそれぞれ一例である。第１接合材及び第２接合材は、はんだに限定されず、導電性及び流動性を有する接合材であればよい。 The solder 20 and the solder 22 are examples of the first bonding material and the second bonding material in the first aspect of the present disclosure, respectively. The first bonding material and the second bonding material are not limited to solder, and may be any bonding material having conductivity and fluidity.

図２を参照して、下側放熱板１４について詳細に説明する。下側放熱板１４の第１主表面１４ａは、第１領域Ａ１と、第１領域Ａ１を取り囲む第２領域Ａ２を有する。第１領域Ａ１の少なくとも一部がはんだ２０と接触する。従って、下側放熱板１４の第１主表面１４ａは、第１領域Ａ１において、半導体素子１２の第２主電極１２ｂにはんだ２０を介して接合される。一方、第２領域Ａ２は、第１領域Ａ１よりも表面粗さが大きく、第１はんだ２０に対する親和性が低い。言い換えると、第２領域Ａ２は第１領域Ａ１よりも粗面化されている。一例ではあるが、この第２領域Ａ２の粗面は、下側放熱板１４の第１主表面１４ａをレーザ照射することによって形成される。第２領域Ａ２の粗面化手法は、レーザ照射に限定されず、他の粗面化手法であってもよい。 The lower heat radiating plate 14 will be described in detail with reference to FIG. The first main surface 14a of the lower heat radiating plate 14 has a first region A1 and a second region A2 surrounding the first region A1. At least a part of the first region A1 comes into contact with the solder 20. Therefore, the first main surface 14a of the lower heat radiating plate 14 is bonded to the second main electrode 12b of the semiconductor element 12 via the solder 20 in the first region A1. On the other hand, the second region A2 has a larger surface roughness than the first region A1 and has a lower affinity for the first solder 20. In other words, the second region A2 is rougher than the first region A1. As an example, the rough surface of the second region A2 is formed by irradiating the first main surface 14a of the lower heat radiating plate 14 with a laser. The roughening method of the second region A2 is not limited to laser irradiation, and may be another roughening method.

半導体素子１２が接合された下側放熱板１４の第１主表面１４ａを平面視すると、第１領域Ａ１と第２領域Ａ２との間の境界ＢＬは、半導体素子１２の周縁ＰＥを取り囲む。また、半導体素子１２の周縁ＰＥと境界ＢＬとの間の間隔Ｗは、半導体素子１２の周縁ＰＥに沿って部分的に拡大されている。 When the first main surface 14a of the lower heat radiating plate 14 to which the semiconductor element 12 is bonded is viewed in a plan view, the boundary BL between the first region A1 and the second region A2 surrounds the peripheral PE of the semiconductor element 12. Further, the distance W between the peripheral PE of the semiconductor element 12 and the boundary BL is partially expanded along the peripheral PE of the semiconductor element 12.

上記した半導体装置１０では、下側放熱板１４の第１主表面１４ａが、はんだ２０と接触する第１領域Ａ１と、第１領域Ａ１を取り囲むとともに第１領域Ａ１よりもはんだ２０に対する親和性が低い第２領域Ａ２とを有する。このような構成によると、下側放熱板１４と半導体素子１２との間から溢れ出た余剰なはんだは、主に第１領域Ａ１において濡れ広がり、第２領域Ａ２へ濡れ広がることが抑制される。即ち、余剰なはんだの濡れ広がりは、第１領域Ａ１と第２領域Ａ２との間の境界ＢＬによって制限又は抑制される。このとき、第１領域Ａ１と第２領域Ａ２との間の境界ＢＬが、半導体素子１２の周縁ＰＥに近接して設けられていると、余剰なはんだの量に対して、第１領域Ａ１の面積が不足するおそれがある。この場合、余剰なはんだが第１領域Ａ１を越えてしまい、意図しない範囲へ濡れ広がるおそれがある。それに対して、第１領域Ａ１と第２領域Ａ２との間の境界ＢＬが、半導体素子１２の周縁ＰＥから離れて設けられていると、第１領域Ａ１の一部に偏って余剰なはんだが流れ込むことによって、下側放熱板１４に対する半導体素子１２の位置が意図せず変化するおそれがある。この点に関して、上記した半導体装置１０では、第１領域Ａ１と第２領域Ａ２との間の境界ＢＬが、半導体素子１２の周縁ＰＥを取り囲むとともに、半導体素子１２の周縁ＰＥと当該境界ＢＬとの間の間隔Ｗは、半導体素子１２の周縁ＰＥに沿って部分的に拡大されている。このような構成によると、下側放熱板１４に対する半導体素子１２の位置ずれを抑制しつつ、半導体素子１２の周縁ＰＥと境界ＢＬとの間の間隔Ｗが拡大された領域に、余剰なはんだを受け入れることができる。 In the semiconductor device 10 described above, the first main surface 14a of the lower heat radiating plate 14 surrounds the first region A1 and the first region A1 in contact with the solder 20, and has a higher affinity for the solder 20 than the first region A1. It has a low second region A2. According to such a configuration, the excess solder that overflows between the lower heat radiating plate 14 and the semiconductor element 12 is prevented from spreading wet mainly in the first region A1 and spreading to the second region A2. .. That is, the wet spread of excess solder is limited or suppressed by the boundary BL between the first region A1 and the second region A2. At this time, if the boundary BL between the first region A1 and the second region A2 is provided close to the peripheral PE of the semiconductor element 12, the first region A1 has a relative amount of excess solder. The area may be insufficient. In this case, the excess solder may exceed the first region A1 and spread to an unintended range. On the other hand, if the boundary BL between the first region A1 and the second region A2 is provided away from the peripheral PE of the semiconductor element 12, excess solder is biased to a part of the first region A1. The flow may cause the position of the semiconductor element 12 with respect to the lower heat radiation plate 14 to change unintentionally. In this regard, in the semiconductor device 10 described above, the boundary BL between the first region A1 and the second region A2 surrounds the peripheral PE of the semiconductor element 12, and the peripheral PE of the semiconductor element 12 and the boundary BL are in contact with each other. The interval W between them is partially expanded along the peripheral PE of the semiconductor element 12. According to such a configuration, while suppressing the displacement of the semiconductor element 12 with respect to the lower heat radiating plate 14, excess solder is applied to the region where the distance W between the peripheral PE and the boundary BL of the semiconductor element 12 is expanded. Can be accepted.

図３、４を参照して、実施例１の半導体装置１０の製造方法について説明する。先ず、上側放熱板１６と半導体素子１２を用意し、各々の接合部に予備はんだを配置する。次いで、上側放熱板１６は、不図示の信号端子等と一体に形成された一つの部品（リードフレーム）として用意されてもよい。次いで、図３に示すように、上側放熱板１６上に半導体素子１２をはんだ付けする（第１リフロー工程）。具体的には、上側放熱板１６の第２主表面１６ｂにおけるスペーサ部１６ｃの頂面部分に、半導体素子１２の第１主電極１２ａがはんだ２２を介して接合される。このとき、上側放熱板１６と半導体素子１２との間にはシート形状のはんだが介挿されており、リフロー炉等でそのはんだを加熱し溶融することで、上側放熱板１６と半導体素子１２は接合される。なお、第１リフロー工程時に、半導体素子１２の第２主電極１２ｂ上にも予備はんだを配置しておく。 The manufacturing method of the semiconductor device 10 of the first embodiment will be described with reference to FIGS. 3 and 4. First, the upper heat radiating plate 16 and the semiconductor element 12 are prepared, and preliminary solder is arranged at each joint. Next, the upper heat radiating plate 16 may be prepared as one component (lead frame) integrally formed with a signal terminal or the like (not shown). Next, as shown in FIG. 3, the semiconductor element 12 is soldered onto the upper heat radiating plate 16 (first reflow step). Specifically, the first main electrode 12a of the semiconductor element 12 is joined to the top surface portion of the spacer portion 16c on the second main surface 16b of the upper heat radiating plate 16 via the solder 22. At this time, a sheet-shaped solder is inserted between the upper heat radiating plate 16 and the semiconductor element 12, and the upper heat radiating plate 16 and the semiconductor element 12 are formed by heating and melting the solder in a reflow furnace or the like. Be joined. At the time of the first reflow step, the preliminary solder is also arranged on the second main electrode 12b of the semiconductor element 12.

第１リフロー工程後、レーザ照射により第１主表面１４ａの一部（即ち第２領域Ａ２）が粗面化された下側放熱板１４を用意する。次いで、図４に示すように、半導体素子１２上に下側放熱板１４をはんだ付けする（第２リフロー工程）。具体的には、半導体素子１２の第２主電極１２ｂに、下側放熱板１４の第１主表面１４ａがはんだ２０を介して接合される。このとき、半導体素子１２と下側放熱板１４との間にはシート形状のはんだが介挿されており、リフロー炉等でそのはんだを加熱し溶融することで、半導体素子１２と下側放熱板１４は接合される。ここで、一例ではあるが、第２リフロー工程において、高さ合わせのための治具を用いてはんだ付けを行ってよい。高さ合わせの治具を用いることで下側放熱板１４に対する上側放熱板１６の高さ位置が決定し、下側放熱板１４上に半導体素子１２を精度よく配置することができる。なお、下側放熱板１４の第１主表面１４ａには、予め予備はんだが配置されていてもよい。 After the first reflow step, a lower heat radiating plate 14 is prepared in which a part of the first main surface 14a (that is, the second region A2) is roughened by laser irradiation. Next, as shown in FIG. 4, the lower heat radiating plate 14 is soldered onto the semiconductor element 12 (second reflow step). Specifically, the first main surface 14a of the lower heat radiating plate 14 is bonded to the second main electrode 12b of the semiconductor element 12 via the solder 20. At this time, sheet-shaped solder is inserted between the semiconductor element 12 and the lower heat radiating plate 14, and the solder is heated and melted in a reflow furnace or the like to melt the solder, thereby causing the semiconductor element 12 and the lower heat radiating plate 14 to be inserted. 14 is joined. Here, although it is an example, in the second reflow step, soldering may be performed using a jig for height adjustment. By using the height matching jig, the height position of the upper heat radiating plate 16 with respect to the lower heat radiating plate 14 is determined, and the semiconductor element 12 can be accurately arranged on the lower heat radiating plate 14. Preliminary solder may be arranged in advance on the first main surface 14a of the lower heat radiating plate 14.

以上の工程により、半導体装置１０は組み付けされる。上記の製造方法により、下側放熱板１４に対する半導体素子１２の位置ずれを抑制しつつ、半導体素子１２の周縁ＰＥと境界ＢＬとの間の間隔Ｗが拡大された領域に、余剰なはんだを受け入れることができる。但し、この製造方法は一例であり、特別に限定されるものではない。なお、他の製造工程については、従来の技術を用いて製造することができる。 The semiconductor device 10 is assembled by the above steps. By the above manufacturing method, the excess solder is accepted in the region where the distance W between the peripheral PE and the boundary BL of the semiconductor element 12 is expanded while suppressing the displacement of the semiconductor element 12 with respect to the lower heat radiation plate 14. be able to. However, this manufacturing method is an example and is not particularly limited. The other manufacturing processes can be manufactured by using the conventional technique.

実施例１の半導体装置１０では、半導体素子１２の周縁ＰＥは略矩形状であり、四つの辺で構成されている。下側放熱板１４について、半導体素子１２の周縁ＰＥと境界ＢＬとの間の間隔Ｗは、半導体素子１２の周縁ＰＥに沿って、特に半導体素子１２の周縁ＰＥを構成する四つの辺の各辺においてそれぞれ部分的に拡大されている。このような構成によると、周縁ＰＥを構成する四辺すべてにおいて余剰はんだが濡れ広がるスペースを確保することができる。従って、余剰はんだが意図しない範囲にまで濡れ広がることが抑制され、それに起因する絶縁不良を防止することができる。但し、これに限定されず、下側放熱板１４は、様々に変形可能である。 In the semiconductor device 10 of the first embodiment, the peripheral PE of the semiconductor element 12 has a substantially rectangular shape and is composed of four sides. Regarding the lower heat radiating plate 14, the distance W between the peripheral edge PE of the semiconductor element 12 and the boundary BL is along the peripheral edge PE of the semiconductor element 12, particularly each side of the four sides constituting the peripheral edge PE of the semiconductor element 12. Each is partially expanded in. According to such a configuration, it is possible to secure a space where the excess solder wets and spreads on all four sides constituting the peripheral PE. Therefore, it is possible to prevent the excess solder from spreading to an unintended range, and to prevent insulation defects caused by the excess solder. However, the present invention is not limited to this, and the lower heat radiating plate 14 can be deformed in various ways.

図５を参照して、下側放熱板１４のいくつかの変形例について説明する。図５（Ａ）に示すように、半導体素子１２の周縁ＰＥと境界ＢＬとの間の間隔Ｗは、半導体素子１２の周縁ＰＥに沿って、半導体素子１２の周縁ＰＥを構成する四つの辺のうち一辺において、部分的に拡大されていてもよい。この場合、間隔Ｗが拡大される範囲が減るため、その分だけ下側放熱板１４のサイズを比較的に小さく設計することもできる。 With reference to FIG. 5, some modifications of the lower heat radiating plate 14 will be described. As shown in FIG. 5 (A), the distance W between the peripheral PE of the semiconductor element 12 and the boundary BL is the four sides forming the peripheral PE of the semiconductor element 12 along the peripheral PE of the semiconductor element 12. One side of it may be partially enlarged. In this case, since the range in which the interval W is expanded is reduced, the size of the lower heat radiating plate 14 can be designed to be relatively small accordingly.

あるいは、図５（Ｂ）に示すように、間隔Ｗが、半導体素子１２の周縁ＰＥを構成する四つの辺のうち二辺において、部分的に拡大されていてもよい。この場合、図示したような互いに対向する二辺において、部分的に拡大されているとよい。このような構成によると、対向する二辺において、左右バランスよく余剰はんだが収容することができる。また、境界ＢＬが多方向において半導体素子１２を取り囲むことから、半導体素子１２の位置ずれを抑制することにも有利である。あるいは、図５（ｃ）に示すように、間隔Ｗが、半導体素子１２の周縁ＰＥを構成する四つの辺のうち三辺において、部分的に拡大されていてもよい。 Alternatively, as shown in FIG. 5B, the interval W may be partially expanded on two of the four sides constituting the peripheral PE of the semiconductor element 12. In this case, it is preferable that the two sides facing each other as shown in the figure are partially enlarged. According to such a configuration, excess solder can be accommodated in a well-balanced left and right on the two opposite sides. Further, since the boundary BL surrounds the semiconductor element 12 in multiple directions, it is also advantageous to suppress the positional deviation of the semiconductor element 12. Alternatively, as shown in FIG. 5C, the interval W may be partially expanded on three of the four sides constituting the peripheral PE of the semiconductor element 12.

あるいは、図５（Ｄ）に示すように、間隔Ｗは、半導体素子１２の周縁ＰＥの少なくとも一つの角部に対応する範囲において、部分的に拡大されていてもよい。このような構成によると、半導体素子１２を取り囲む周縁ＰＥの長さに対して、比較的に多量の余剰はんだを収容可能な領域を確保することができる。なお、間隔Ｗにおける周縁ＰＥに沿って拡大する幅及び長さや、拡大する箇所及び位置は、第１領域Ａ１及び第２領域Ａ２の第１接合材に対する親和性によって、適宜調整することができる。 Alternatively, as shown in FIG. 5D, the spacing W may be partially expanded in a range corresponding to at least one corner of the peripheral PE of the semiconductor element 12. According to such a configuration, it is possible to secure a region capable of accommodating a relatively large amount of excess solder with respect to the length of the peripheral PE surrounding the semiconductor element 12. The width and length of the expansion along the peripheral PE at the interval W and the expansion location and position can be appropriately adjusted depending on the affinity of the first region A1 and the second region A2 with respect to the first bonding material.

（実施例２）図６−１２を参照して、実施例２の半導体装置１００及びその製造方法について説明する。図６に示すように、半導体装置１００は、半導体素子１１２と、下側放熱板１１４と、上側放熱板１１６と、封止体１１８とを備える。半導体素子１１２は、封止体１１８の内部に封止されている。封止体１１８は、例えばエポキシ樹脂といった絶縁性を有する材料を用いて構成されている。封止体１１８は、概して板形状を有しており、互いに反対側に位置する二つの主表面を有する。一方の主表面には下側放熱板１１４が露出しており、他方の主表面には上側放熱板１１６が露出している。下側放熱板１１４及び上側放熱板１１６は、封止体１１８の内部において半導体素子１１２と電気的及び熱的に接続されている。これにより、下側放熱板１１４及び上側放熱板１１６は、半導体素子１１２に接続された電気回路の一部を構成するとともに、半導体素子１１２の熱を外部へ放熱する放熱板として機能する。ここで、下側放熱板１１４及び上側放熱板１１６は、本開示の第２の側面における第１導体板及び第２導体板の一例である。 (Example 2) The semiconductor device 100 of the second embodiment and a method for manufacturing the same will be described with reference to FIGS. 6-12. As shown in FIG. 6, the semiconductor device 100 includes a semiconductor element 112, a lower heat radiating plate 114, an upper heat radiating plate 116, and a sealing body 118. The semiconductor element 112 is sealed inside the sealing body 118. The sealing body 118 is constructed by using a material having an insulating property such as an epoxy resin. The sealant 118 generally has a plate shape and has two main surfaces located opposite to each other. The lower heat radiating plate 114 is exposed on one main surface, and the upper heat radiating plate 116 is exposed on the other main surface. The lower heat radiating plate 114 and the upper heat radiating plate 116 are electrically and thermally connected to the semiconductor element 112 inside the sealing body 118. As a result, the lower heat radiating plate 114 and the upper heat radiating plate 116 form a part of the electric circuit connected to the semiconductor element 112 and function as a heat radiating plate that dissipates the heat of the semiconductor element 112 to the outside. Here, the lower heat radiating plate 114 and the upper heat radiating plate 116 are examples of the first conductor plate and the second conductor plate on the second side surface of the present disclosure.

半導体素子１１２は、主に半導体基板で構成されているとともに、一対の主電極１１２ａ、１１２ｂと有する。一対の主電極１１２ａ、１１２ｂには、第１主電極１１２ａと第２主電極１１２ｂが含まれている。第１主電極１１２ａは、半導体素子１１２の一方の表面に位置しており、第２主電極１１２ｂは、半導体素子１１２の他方の表面に位置している。一対の主電極１１２ａ、１１２ｂは、半導体基板を介して電気的に接続される。 The semiconductor element 112 is mainly composed of a semiconductor substrate and has a pair of main electrodes 112a and 112b. The pair of main electrodes 112a and 112b includes a first main electrode 112a and a second main electrode 112b. The first main electrode 112a is located on one surface of the semiconductor element 112, and the second main electrode 112b is located on the other surface of the semiconductor element 112. The pair of main electrodes 112a and 112b are electrically connected via a semiconductor substrate.

半導体素子１１２は、パワー半導体素子であって、例えば、ＩＧＢＴ（Insulated Gate Bipolar Transistor）である。但し、半導体素子１１２はＩＧＢＴに限られず、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）又はダイオードであってもよい。なお、半導体素子の数や種類については、特に限定されない。半導体素子１１２を構成する半導体材料には、例えばケイ素（Ｓｉ）、炭化ケイ素（ＳｉＣ）、窒化ガリウム（ＧａＮ）又は他の種類の半導体材料を採用することができる。 The semiconductor element 112 is a power semiconductor element, for example, an IGBT (Insulated Gate Bipolar Transistor). However, the semiconductor element 112 is not limited to the IGBT, and may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or a diode. The number and types of semiconductor elements are not particularly limited. As the semiconductor material constituting the semiconductor element 112, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or other types of semiconductor materials can be adopted.

下側放熱板１１４及び上側放熱板１１６は、半導体素子１１２を挟んで対向している。下側放熱板１１４は、概して板形状又は直方体形状を有しており、例えば銅又は他の金属といった導体材料を用いて形成されている。下側放熱板１１４は、第１主表面１１４ａと、その反対側に位置する第２主表面１１４ｂを有している。下側放熱板１１４の第１主表面１１４ａは、半導体素子１１２の第２主電極１１２ｂにはんだ１２０を介して接合される。これにより、下側放熱板１１４は、半導体素子１１２と電気的及び熱的に接続されている。一方、下側放熱板１１４の第２主表面１１４ｂは、封止体１１８の一方の表面において露出されている。 The lower heat radiating plate 114 and the upper heat radiating plate 116 face each other with the semiconductor element 112 interposed therebetween. The lower heat radiating plate 114 generally has a plate shape or a rectangular parallelepiped shape, and is formed by using a conductor material such as copper or other metal. The lower heat radiating plate 114 has a first main surface 114a and a second main surface 114b located on the opposite side thereof. The first main surface 114a of the lower heat radiating plate 114 is joined to the second main electrode 112b of the semiconductor element 112 via the solder 120. As a result, the lower heat radiating plate 114 is electrically and thermally connected to the semiconductor element 112. On the other hand, the second main surface 114b of the lower heat radiating plate 114 is exposed on one surface of the sealing body 118.

上側放熱板１１６も、下側放熱板１１４と同様に、概して板形状又は直方体形状を有しており、例えば銅又は他の金属といった導体材料を用いて形成されている。上側放熱板１１６は、第１主表面１１６ａと、その反対側に位置する第２主表面１１６ｂとを有している。上側放熱板１１６には、半導体素子１１２と向かい合う範囲において、第２主表面１１６ｂから半導体素子１１２に向かって突出するスペーサ部１１６ｃが設けられている。このスペーサ部１１６ｃにおいて、上側放熱板１１６は、下側放熱板１１４とは異なっている。このスペーサ部１１６ｃによって、半導体装置１００の製造工程における組付け作業を一部簡素化することもできる。上側放熱板１１６の第１主表面１１６ａは、封止体１１８の他方の表面において露出されている。上側放熱板１１６は、第２主表面１１６ｂのスペーサ部１１６ｃにおける頂面部分において半導体素子１１２の第１主電極１１２ａにはんだ１２２を介して接合されている。これにより、上側放熱板１１６は、半導体素子１１２と電気的及び熱的に接続されている。なお、スペーサ部１１６ｃは、頂面からスペーサ部１１６ｃの基端部に向かって、スペーサ部１１６ｃの断面積が拡大するテーパ形状を有している。ここでいうスペーサ部１１６ｃの断面積は、半導体装置１００の積層方向に対して垂直にスペーサ部１１６ｃを切断したときの断面積を示す。 The upper heat radiating plate 116, like the lower heat radiating plate 114, generally has a plate shape or a rectangular parallelepiped shape, and is formed by using a conductor material such as copper or other metal. The upper heat radiating plate 116 has a first main surface 116a and a second main surface 116b located on the opposite side thereof. The upper heat radiating plate 116 is provided with a spacer portion 116c that projects from the second main surface 116b toward the semiconductor element 112 in a range facing the semiconductor element 112. In this spacer portion 116c, the upper heat radiating plate 116 is different from the lower heat radiating plate 114. The spacer portion 116c can also partially simplify the assembly work in the manufacturing process of the semiconductor device 100. The first main surface 116a of the upper heat radiating plate 116 is exposed on the other surface of the sealant 118. The upper heat radiating plate 116 is joined to the first main electrode 112a of the semiconductor element 112 via solder 122 at the top surface portion of the spacer portion 116c of the second main surface 116b. As a result, the upper heat radiating plate 116 is electrically and thermally connected to the semiconductor element 112. The spacer portion 116c has a tapered shape in which the cross-sectional area of the spacer portion 116c expands from the top surface toward the base end portion of the spacer portion 116c. The cross-sectional area of the spacer portion 116c referred to here indicates the cross-sectional area when the spacer portion 116c is cut perpendicularly to the stacking direction of the semiconductor device 100.

はんだ１２０及びはんだ１２２は、本開示の第２の側面における第１接合材及び第２接合材のそれぞれ一例である。第１接合材及び第２接合材は、はんだに限定されず、導電性及び流動性を有する接合材であればよい。 The solder 120 and the solder 122 are examples of the first bonding material and the second bonding material in the second aspect of the present disclosure, respectively. The first bonding material and the second bonding material are not limited to solder, and may be any bonding material having conductivity and fluidity.

図７を参照して、上側放熱板１１６について詳細に説明する。上側放熱板１１６の第２主表面１１６ｂには、はんだ１２０の周縁に沿って延びる第１溝１１６ｄが設けられている。第１溝１１６ｄは、はんだ１２０と接触している。第１溝１１６ｄの内面には、第１溝１１６ｄの長手方向に沿って延びる第２溝１１６ｅが設けられている。第２溝１１６ｅの断面積は、第１溝１１６ｄの断面積よりも小さい。ここでいう第１溝１１６ｄ及び第２溝１１６ｅの断面積は、第１溝１１６ｄの長手方向に対して垂直に第１溝１１６ｄ及び第２溝１１６ｅをそれぞれ切断したときの断面積を示す。一例ではあるが、第２溝１１６ｅの幅寸法は、約０．５ミリメートル程度であってよい。なお、第２溝１１６ｅの幅寸法は、第２溝１１６ｅにおける第１接合材又は第２接合材（本実施例でいうはんだ）の接触角等（第２溝１１６ｅにおける第１接合材又は第２接合材の表面張力に関与するパラメータ）によって決定される。 The upper heat radiating plate 116 will be described in detail with reference to FIG. 7. The second main surface 116b of the upper heat radiating plate 116 is provided with a first groove 116d extending along the peripheral edge of the solder 120. The first groove 116d is in contact with the solder 120. A second groove 116e extending along the longitudinal direction of the first groove 116d is provided on the inner surface of the first groove 116d. The cross-sectional area of the second groove 116e is smaller than the cross-sectional area of the first groove 116d. The cross-sectional area of the first groove 116d and the second groove 116e referred to here indicates the cross-sectional area when the first groove 116d and the second groove 116e are cut perpendicularly to the longitudinal direction of the first groove 116d, respectively. As an example, the width dimension of the second groove 116e may be about 0.5 mm. The width dimension of the second groove 116e is the contact angle of the first joint material or the second joint material (solder in the present embodiment) in the second groove 116e (the first joint material or the second joint material in the second groove 116e). It is determined by the parameters involved in the surface tension of the bonding material).

上記した半導体装置１００では、上側放熱板１１６に、第１溝１１６ｄが設けられている。この第１溝１１６ｄは、はんだ１２２に接触する一表面に設けられているとともに、はんだ１２２の周縁に沿って延びている。このような構成によると、半導体素子１１２と上側放熱板１１６とが接合されるときに、余剰なはんだを第１溝１１６ｄに収容することができる。さらに、第１溝１１６ｄの内面には、第１溝１１６ｄの長手方向に沿って延びるとともに第１溝１１６ｄよりも断面積の小さい第２溝１１６ｅが設けられている。これにより、第１溝１１６ｄに収容されたはんだ１２２は、第２溝１１６ｅにおける表面張力によって誘導されることで、第１溝１１６ｄの全体に亘って濡れ広がることができる。従って、第１溝１１６ｄが比較的に小さい場合でも、余剰なはんだを第１溝１１６ｄの全体で速やかに収容することができ、余剰なはんだが第１溝１１６ｄを越えて過剰に濡れ広がることが防止される。 In the semiconductor device 100 described above, the first groove 116d is provided on the upper heat radiating plate 116. The first groove 116d is provided on one surface in contact with the solder 122 and extends along the peripheral edge of the solder 122. According to such a configuration, when the semiconductor element 112 and the upper heat radiating plate 116 are joined, excess solder can be accommodated in the first groove 116d. Further, on the inner surface of the first groove 116d, a second groove 116e extending along the longitudinal direction of the first groove 116d and having a cross-sectional area smaller than that of the first groove 116d is provided. As a result, the solder 122 housed in the first groove 116d can be wetted and spread over the entire first groove 116d by being guided by the surface tension in the second groove 116e. Therefore, even when the first groove 116d is relatively small, the excess solder can be quickly accommodated in the entire first groove 116d, and the excess solder can be excessively wetted and spread beyond the first groove 116d. Be prevented.

図８、図９を参照して、実施例２の半導体装置１００の製造方法について説明する。先ず、上側放熱板１１６と半導体素子１１２を用意し、各々の接合部に予備はんだを配置する。予備はんだ後、上側放熱板１１６は、不図示の信号端子等と一体に形成された一つの部品（リードフレーム）として用意されてもよい。次いで、図３に示すように、上側放熱板１１６上に半導体素子１１２をはんだ付けする（第１リフロー工程）。具体的には、上側放熱板１１６の第２主表面１１６ｂにおけるスペーサ部１１６ｃの頂面部分に、半導体素子１１２の第１主電極１１２ａがはんだ１２２を介して接合される。このとき、上側放熱板１１６と半導体素子１１２との間にはシート形状のはんだが介挿されており、リフロー炉等でそのはんだを加熱し溶融することで、上側放熱板１１６と半導体素子１１２は接合される。余剰のはんだは、スペーサ部１１６ｃの特に角部を伝って第１溝１１６ｄに収容され、第１溝１１６ｄに設けられた第２溝１１６ｅにおける表面張力によって誘導されることで、第１溝１１６ｄ全体に濡れ広がる。なお、第１リフロー工程時に、半導体素子１１２の第２主電極１１２ｂ上にも予備はんだを配置しておく。 The manufacturing method of the semiconductor device 100 of the second embodiment will be described with reference to FIGS. 8 and 9. First, the upper heat radiating plate 116 and the semiconductor element 112 are prepared, and preliminary solder is arranged at each joint. After pre-soldering, the upper heat radiating plate 116 may be prepared as one component (lead frame) integrally formed with a signal terminal or the like (not shown). Next, as shown in FIG. 3, the semiconductor element 112 is soldered onto the upper heat radiating plate 116 (first reflow step). Specifically, the first main electrode 112a of the semiconductor element 112 is joined to the top surface portion of the spacer portion 116c on the second main surface 116b of the upper heat radiating plate 116 via the solder 122. At this time, a sheet-shaped solder is inserted between the upper heat radiating plate 116 and the semiconductor element 112, and by heating and melting the solder in a reflow furnace or the like, the upper heat radiating plate 116 and the semiconductor element 112 are separated from each other. Be joined. The excess solder is accommodated in the first groove 116d along the spacer portion 116c, particularly at the corners, and is guided by the surface tension in the second groove 116e provided in the first groove 116d, thereby causing the entire first groove 116d. Wet and spread. At the time of the first reflow step, the preliminary solder is also arranged on the second main electrode 112b of the semiconductor element 112.

第１リフロー工程後、下側放熱板１１４を用意する。次いで、図９に示すように、半導体素子１１２上に下側放熱板１１４をはんだ付けする（第２リフロー工程）。具体的には、半導体素子１１２の第２主電極１１２ｂに、下側放熱板１１４の第１主表面１１４ａがはんだ１２０を介して接合される。このとき、半導体素子１１２と下側放熱板１１４との間にはシート形状のはんだが介挿されており、リフロー炉等でそのはんだを加熱し溶融することで、半導体素子１１２と下側放熱板１１４は接合される。ここで、一例ではあるが、第２リフロー工程において、高さ合わせのための治具を用いてはんだ付けを行ってよい。高さ合わせの治具を用いることで下側放熱板１１４に対する上側放熱板１１６の高さ位置が決定し、下側放熱板１１４上に半導体素子１１２を精度よく配置することができる。なお、下側放熱板１１４の第１主表面１１４ａには、予め予備はんだが配置されていてもよい。 After the first reflow step, the lower heat radiating plate 114 is prepared. Next, as shown in FIG. 9, the lower heat radiating plate 114 is soldered onto the semiconductor element 112 (second reflow step). Specifically, the first main surface 114a of the lower heat radiating plate 114 is bonded to the second main electrode 112b of the semiconductor element 112 via the solder 120. At this time, sheet-shaped solder is inserted between the semiconductor element 112 and the lower heat radiating plate 114, and the solder is heated and melted in a reflow furnace or the like to melt the solder, thereby causing the semiconductor element 112 and the lower heat radiating plate 114. 114 are joined. Here, although it is an example, in the second reflow step, soldering may be performed using a jig for height adjustment. By using the height matching jig, the height position of the upper heat radiating plate 116 with respect to the lower heat radiating plate 114 is determined, and the semiconductor element 112 can be accurately arranged on the lower heat radiating plate 114. Preliminary solder may be arranged in advance on the first main surface 114a of the lower heat radiating plate 114.

以上の工程により、半導体装置１００は組み付けされる。上記の製造方法により、余剰なはんだを第１溝１１６ｄの全体で速やかに収容することができ、余剰なはんだが第１溝１１６ｄを越えて過剰に濡れ広がることが防止される。但し、この製造方法は一例であり、特別に限定されるものではない。なお、他の製造工程については、従来の技術を用いて製造することができる。 The semiconductor device 100 is assembled by the above steps. According to the above manufacturing method, the excess solder can be quickly accommodated in the entire first groove 116d, and the excess solder is prevented from being excessively wetted and spread beyond the first groove 116d. However, this manufacturing method is an example and is not particularly limited. The other manufacturing processes can be manufactured by using the conventional technique.

なお、実施例２の半導体装置１００は、様々に変更可能である。図１０−図１２を参照して、半導体装置１００のいくつかの変形例について説明する。上側放熱板１１６に設けられた第１溝１１６ｄにおける第２溝１１６ｅの具体的な位置や数については、特に限定されず、適宜調整することが可能である。図１０（Ａ）に示すように、第２溝１１６ｅは、第１溝１１６ｄの外周縁側に設けられていてもよい。あるいは、図１０（Ｂ）に示すように、第２溝１１６ｅは、第１溝１１６ｄの内周縁側に設けられていてもよい。また、図１０（Ｃ）に示すように、第２溝１１６ｅの数は一つに限定されず、第１溝１１６ｄ内に二又は三以上の第２溝１１６ｅが設けられていてもよい。 The semiconductor device 100 of the second embodiment can be changed in various ways. Some modifications of the semiconductor device 100 will be described with reference to FIGS. 10-12. The specific position and number of the second groove 116e in the first groove 116d provided on the upper heat radiating plate 116 are not particularly limited and can be appropriately adjusted. As shown in FIG. 10A, the second groove 116e may be provided on the outer peripheral edge side of the first groove 116d. Alternatively, as shown in FIG. 10B, the second groove 116e may be provided on the inner peripheral edge side of the first groove 116d. Further, as shown in FIG. 10C, the number of the second grooves 116e is not limited to one, and two or three or more second grooves 116e may be provided in the first groove 116d.

実施例２の半導体装置１００の上側放熱板１１６も、上記したものに限定されない。例えば、上側放熱板１１６は、スペーサ部１１６ｃは必ずしも必要としない。図１０（Ａ）から図１０（Ｃ）に示すように、上側放熱板１１６の第２主表面１１６ｂ全体が略フラットな面で構成されていてもよい。また、図１１に示すように、上側放熱板１１６のスペーサ部１１６ｃに代えて、又は加えて、上側放熱板１１６と半導体素子１１２との間に、別体の導体スペーサ１１５を有していてもよい。 The upper heat radiating plate 116 of the semiconductor device 100 of the second embodiment is not limited to the above. For example, the upper heat radiating plate 116 does not necessarily require the spacer portion 116c. As shown in FIGS. 10 (A) to 10 (C), the entire second main surface 116b of the upper heat radiating plate 116 may be formed of a substantially flat surface. Further, as shown in FIG. 11, even if a separate conductor spacer 115 is provided between the upper heat radiating plate 116 and the semiconductor element 112 in place of or in addition to the spacer portion 116c of the upper heat radiating plate 116. Good.

実施例２の半導体装置１００では、第１溝１１６ｄは、上側放熱板１１６に設けられている。但し、第１溝１１６ｄの設けられる位置は、これに限定されない。上側放熱板１１６に設けられた第１溝１１６ｄに代えて、又は加えて、図１２に示すように、下側放熱板１１４の第１主表面１１４ａに第１溝１１４ｄが設けられていてもよい。第１溝１１４ｄ、１１６ｄは、はんだ１２０、１２２に接触する下側放熱板１１４及び上側放熱板１１６の少なくとも一方に設けられていればよい。仮に第１溝１１４ｄが下側放熱板１１４に設けられた場合であっても、第１溝１１４ｄに収容されたはんだ１２０は、第２溝１１４ｅにおける表面張力によって誘導されることで、第１溝１１４ｄの全体に亘って濡れ広がることができる。 In the semiconductor device 100 of the second embodiment, the first groove 116d is provided on the upper heat radiating plate 116. However, the position where the first groove 116d is provided is not limited to this. In place of or in addition to the first groove 116d provided on the upper heat radiating plate 116, the first groove 114d may be provided on the first main surface 114a of the lower heat radiating plate 114, as shown in FIG. .. The first grooves 114d and 116d may be provided on at least one of the lower heat radiating plate 114 and the upper heat radiating plate 116 in contact with the solders 120 and 122. Even if the first groove 114d is provided on the lower heat radiating plate 114, the solder 120 housed in the first groove 114d is guided by the surface tension in the second groove 114e, so that the first groove 114d It can be wet and spread over the entire 114d.

以上、本明細書が開示する技術の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。本明細書、又は、図面に説明した技術要素は、単独で、あるいは各種の組合せによって技術的有用性を発揮するものであり、出願時の請求項に記載の組合せに限定されるものではない。本明細書又は図面に例示した技術は、複数の目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Although specific examples of the techniques disclosed in the present specification have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The techniques exemplified in the present specification or drawings can achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

１０、１００：半導体装置
１２、１１２：半導体素子
１２ａ、１２ｂ、１１２ａ、１１２ｂ：主電極
１２ｃ：信号電極
１４、１１４：下側放熱板
１６、１１６：上側放熱板
１６ｃ、１１６ｃ：スペーサ部
１８、１１８：封止体
２０、２２、１２０、１２２：はんだ
１１４ｄ、１１６ｄ：第１溝
１１４ｅ、１１６ｅ：第２溝
Ａ１：第１領域
Ａ２：第２領域
ＢＬ：第１領域と第２領域との間の境界
ＰＥ：半導体素子の周縁
Ｗ：半導体素子の周縁と境界との間隔 10, 100: Semiconductor device 12, 112: Semiconductor elements 12a, 12b, 112a, 112b: Main electrode 12c: Signal electrode 14, 114: Lower heat radiation plate 16, 116: Upper heat radiation plate 16c, 116c: Spacer portions 18, 118 : Sealing bodies 20, 22, 120, 122: Soldier 114d, 116d: First groove 114e, 116e: Second groove A1: First region A2: Second region BL: Between the first region and the second region Boundary PE: Periphery of semiconductor element W: Spacing between the peripheral edge of the semiconductor element and the boundary

Claims (2)

半導体素子と、
前記半導体素子に第１接合材を介して接合された第１導体板と、
前記第１導体板と前記半導体素子を挟んで対向するとともに、前記第２接合材を介して前記半導体素子に接合された第２導体板と、を備え、
前記第１導体板の一表面は、その少なくとも一部が前記第１接合材と接触する第１領域と、前記第１領域を取り囲むとともに前記第１領域よりも前記第１接合材に対する親和性が低い第２領域とを有し、
前記半導体素子が接合された前記第１導体板の前記一表面を平面視したときに、前記第１領域と前記第２領域との間の境界は、前記半導体素子の周縁を取り囲むとともに、前記半導体素子の前記周縁と前記境界との間の間隔は、前記半導体素子の前記周縁に沿って部分的に拡大されている、
半導体装置。 With semiconductor elements
A first conductor plate bonded to the semiconductor element via a first bonding material,
It is provided with a second conductor plate that faces the first conductor plate with the semiconductor element interposed therebetween and is joined to the semiconductor element via the second bonding material.
One surface of the first conductor plate surrounds the first region in which at least a part thereof contacts the first bonding material and the first region, and has a higher affinity for the first bonding material than the first region. Has a low second region and
When the one surface of the first conductor plate to which the semiconductor element is bonded is viewed in a plan view, the boundary between the first region and the second region surrounds the peripheral edge of the semiconductor element and the semiconductor. The distance between the peripheral edge of the device and the boundary is partially extended along the peripheral edge of the semiconductor device.
Semiconductor device. 半導体素子と、
前記半導体素子に第１接合材を介して接合された第１導体板と、
前記第１導体板と前記半導体素子を挟んで対向するとともに、前記第２接合材を介して前記半導体素子に接合された第２導体板と、を備え、
前記第１導体板と前記第２導体板の少なくとも一方の一表面には、前記第１接合材又は前記第２接合材に接触しているとともに、前記第１接合材又は前記第２接合材の周縁に沿って延びる第１溝が設けられており、
前記第１溝の内面には、前記第１溝の長手方向に沿って延びるとともに前記第１溝よりも断面積の小さい第２溝が設けられている、
半導体装置。 With semiconductor elements
A first conductor plate bonded to the semiconductor element via a first bonding material,
It is provided with a second conductor plate that faces the first conductor plate with the semiconductor element interposed therebetween and is joined to the semiconductor element via the second bonding material.
The surface of at least one of the first conductor plate and the second conductor plate is in contact with the first joint material or the second joint material, and is of the first joint material or the second joint material. A first groove extending along the periphery is provided,
The inner surface of the first groove is provided with a second groove extending along the longitudinal direction of the first groove and having a cross-sectional area smaller than that of the first groove.
Semiconductor device.
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JP2021077777A (en) * 2019-11-11 2021-05-20 株式会社 日立パワーデバイス Semiconductor device

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JP2007103909A (en) * 2005-09-12 2007-04-19 Denso Corp Semiconductor device
JP2008207207A (en) * 2007-02-26 2008-09-11 Fuji Electric Device Technology Co Ltd Method for solder joining, and method for manufacturing semiconductor device using the same
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JP3008242U (en) * 1994-08-25 1995-03-07 日本インター株式会社 Semiconductor pellet mounting board
JP2007103909A (en) * 2005-09-12 2007-04-19 Denso Corp Semiconductor device
JP2008207207A (en) * 2007-02-26 2008-09-11 Fuji Electric Device Technology Co Ltd Method for solder joining, and method for manufacturing semiconductor device using the same
JP2012084686A (en) * 2010-10-12 2012-04-26 Toyota Industries Corp Connection structure between wiring members

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021077777A (en) * 2019-11-11 2021-05-20 株式会社 日立パワーデバイス Semiconductor device
JP7489181B2 (en) 2019-11-11 2024-05-23 株式会社 日立パワーデバイス Semiconductor Device

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