JP7271381B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7271381B2 JP7271381B2 JP2019171824A JP2019171824A JP7271381B2 JP 7271381 B2 JP7271381 B2 JP 7271381B2 JP 2019171824 A JP2019171824 A JP 2019171824A JP 2019171824 A JP2019171824 A JP 2019171824A JP 7271381 B2 JP7271381 B2 JP 7271381B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40095—Kinked
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
- H01L2224/4101—Structure
- H01L2224/4103—Connectors having different sizes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Bipolar Transistors (AREA)
- Noodles (AREA)
- Die Bonding (AREA)
Description
以下に、第1の実施形態について、図1乃至図6を参照して説明する。なお、本明細書において、実施形態に係る構成要素及び当該要素の説明が、複数の表現で記載されることがある。構成要素及びその説明は、一例であり、本明細書の表現によって限定されない。構成要素は、本明細書におけるものとは異なる名称で特定され得る。また、構成要素は、本明細書の表現とは異なる表現によって説明され得る。
以下に、第2の実施形態について、図7乃至図9を参照して説明する。なお、以下の実施形態の説明において、既に説明された構成要素と同様の機能を持つ構成要素は、当該既述の構成要素と同じ符号が付され、さらに説明が省略される場合がある。また、同じ符号が付された複数の構成要素は、全ての機能及び性質が共通するとは限らず、各実施形態に応じた異なる機能及び性質を有していても良い。
以下に、出願当初の特許請求の範囲の内容を付記する。
[1]
第1のリードフレームと、
凹部が設けられた第1の面を有し、前記第1のリードフレームから離間した第2のリードフレームと、
前記第1のリードフレームに搭載された半導体チップと、
導電性接着剤によって前記第1の面に接続された第2の面と、前記第2の面に設けられるとともに前記凹部に少なくとも部分的に収容された凸部と、を有し、前記半導体チップと前記第2のリードフレームとを電気的に接続する導電部材と、
を具備し、
前記第1の面が延びる方向における前記凹部の長さは、前記第1の面に沿うとともに前記第1の面が延びる方向と直交する方向における前記凹部の長さよりも長く、
前記第1の面が延びる方向における前記凸部の長さは、前記第1の面に沿うとともに前記第1の面が延びる方向と直交する方向における前記凸部の長さよりも長い、
半導体装置。
[2]
前記凹部及び前記凸部は、互いに相似の断面形状を有し、
前記凹部の断面は、前記凸部の断面よりも大きい、
[1]の半導体装置。
[3]
前記凹部は、前記第1の面が延びる方向に延び、
前記凸部は、前記第1の面が延びる方向に延びる、
[1]又は[2]の半導体装置。
[4]
前記凹部は、前記第1の面が延びる方向における前記第1の面の両端から離間した、[1]乃至[3]のいずれか一つの半導体装置。
[5]
前記第1の面が延びる方向において、前記凸部の長さは、前記凹部の長さよりも短い、[1]乃至[4]のいずれか一つの半導体装置。
[6]
前記第1の面に、前記第1の面に沿うとともに前記第1の面が延びる方向と直交する方向に並んだ複数の前記凹部が設けられ、
前記第2の面に、前記第1の面に沿うとともに前記第1の面が延びる方向と直交する方向に並んだ複数の前記凸部が設けられた、
[1]乃至[5]のいずれか一つの半導体装置。
[7]
前記第1の面に、前記第1の面が延びる方向に互いに離間した複数の前記凹部が設けられ、
前記第2の面に、前記第1の面が延びる方向に互いに離間した複数の前記凸部が設けられた、
[1]乃至[6]のいずれか一つの半導体装置。
Claims (8)
- 第1のリードフレームと、
第1の面を有し、前記第1の面から窪んだ凹部が設けられ、前記第1のリードフレームから離間した第2のリードフレームと、
前記第1のリードフレームに搭載された半導体チップと、
導電性接着剤によって前記第1の面に接続された第2の面と、前記第2の面から突出して前記凹部に少なくとも部分的に収容されるとともに前記導電性接着剤によって前記凹部の内面に接続された凸部と、を有し、前記半導体チップと前記第2のリードフレームとを電気的に接続する導電部材と、
を具備し、
前記第1の面が延びる方向における前記凹部の長さは、前記第1の面に沿うとともに前記第1の面が延びる方向と直交する方向における前記凹部の長さよりも長く、
前記第1の面が延びる方向における前記凸部の長さは、前記第1の面に沿うとともに前記第1の面が延びる方向と直交する方向における前記凸部の長さよりも長く、
前記凹部と前記凸部とは、前記第1の面が延びる方向と直交する断面の形状が互いに相似し、
前記凹部の断面は、前記凸部の断面よりも大きい、
半導体装置。 - 前記凹部は、前記第1の面が延びる方向に延び、
前記凸部は、前記第1の面が延びる方向に延びる、
請求項1の半導体装置。 - 前記凹部は、前記第1の面が延びる方向における前記第1の面の両端から離間した、請求項1又は請求項2の半導体装置。
- 前記第1の面が延びる方向において、前記凸部の長さは、前記凹部の長さよりも短い、請求項1乃至請求項3のいずれか一つの半導体装置。
- 前記第1の面に、前記第1の面に沿うとともに前記第1の面が延びる方向と直交する方向に並んだ複数の前記凹部が設けられ、
前記第2の面に、前記第1の面に沿うとともに前記第1の面が延びる方向と直交する方向に並んだ複数の前記凸部が設けられた、
請求項1乃至請求項4のいずれか一つの半導体装置。 - 前記第1の面に、前記第1の面が延びる方向に互いに離間した複数の前記凹部が設けられ、
前記第2の面に、前記第1の面が延びる方向に互いに離間した複数の前記凸部が設けられた、
請求項1乃至請求項5のいずれか一つの半導体装置。 - 前記凸部は前記第2の面の外縁から離間している、
請求項1乃至請求項6のいずれか一つの半導体装置。 - 前記凹部と前記凸部とのそれぞれの断面の形状は半円形である、
請求項1乃至請求項7のいずれか一つの半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019171824A JP7271381B2 (ja) | 2019-09-20 | 2019-09-20 | 半導体装置 |
US17/018,654 US11289408B2 (en) | 2019-09-20 | 2020-09-11 | Semiconductor device |
DE102020211500.1A DE102020211500A1 (de) | 2019-09-20 | 2020-09-14 | Halbleitervorrichtung |
CN202010959502.2A CN112542438B (zh) | 2019-09-20 | 2020-09-14 | 半导体装置 |
TW109131491A TWI777238B (zh) | 2019-09-20 | 2020-09-14 | 半導體裝置 |
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JP2019171824A JP7271381B2 (ja) | 2019-09-20 | 2019-09-20 | 半導体装置 |
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Publication Number | Publication Date |
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JP2021048376A JP2021048376A (ja) | 2021-03-25 |
JP7271381B2 true JP7271381B2 (ja) | 2023-05-11 |
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US (1) | US11289408B2 (ja) |
JP (1) | JP7271381B2 (ja) |
CN (1) | CN112542438B (ja) |
DE (1) | DE102020211500A1 (ja) |
TW (1) | TWI777238B (ja) |
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WO2023181957A1 (ja) * | 2022-03-24 | 2023-09-28 | ローム株式会社 | 半導体装置 |
JP2024035665A (ja) * | 2022-09-02 | 2024-03-14 | 株式会社東芝 | 半導体装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2011049244A (ja) | 2009-08-25 | 2011-03-10 | Shindengen Electric Mfg Co Ltd | 樹脂封止型半導体装置 |
US20150214139A1 (en) | 2014-01-30 | 2015-07-30 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20180331021A1 (en) | 2017-05-09 | 2018-11-15 | Taiwan Semiconductor Co., Ltd. | Die package component with jumper structure and manufacturing method thereof |
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US4935803A (en) * | 1988-09-09 | 1990-06-19 | Motorola, Inc. | Self-centering electrode for power devices |
KR20040004978A (ko) * | 2002-07-08 | 2004-01-16 | 주식회사 하이닉스반도체 | Loc 형 패키지를 갖는 반도체 장치 |
JP2005243685A (ja) | 2004-02-24 | 2005-09-08 | Renesas Technology Corp | 半導体装置 |
US7495323B2 (en) * | 2006-08-30 | 2009-02-24 | Semiconductor Components Industries, L.L.C. | Semiconductor package structure having multiple heat dissipation paths and method of manufacture |
US9761435B1 (en) * | 2006-12-14 | 2017-09-12 | Utac Thai Limited | Flip chip cavity package |
US8035221B2 (en) * | 2007-11-08 | 2011-10-11 | Intersil Americas, Inc. | Clip mount for integrated circuit leadframes |
JP2009302209A (ja) * | 2008-06-11 | 2009-12-24 | Nec Electronics Corp | リードフレーム、半導体装置、リードフレームの製造方法および半導体装置の製造方法 |
JP5745238B2 (ja) | 2010-07-30 | 2015-07-08 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置およびその製造方法 |
JP2012238737A (ja) * | 2011-05-12 | 2012-12-06 | Sanken Electric Co Ltd | 半導体モジュール及びその製造方法 |
JP6011277B2 (ja) * | 2012-06-14 | 2016-10-19 | 株式会社デンソー | 半導体装置の製造方法 |
US10622288B2 (en) * | 2017-11-06 | 2020-04-14 | Rohm Co., Ltd. | Semiconductor device and method for producing semiconductor device |
JP7043225B2 (ja) | 2017-11-08 | 2022-03-29 | 株式会社東芝 | 半導体装置 |
US10204844B1 (en) * | 2017-11-16 | 2019-02-12 | Semiconductor Components Industries, Llc | Clip for semiconductor package |
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- 2019-09-20 JP JP2019171824A patent/JP7271381B2/ja active Active
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2020
- 2020-09-11 US US17/018,654 patent/US11289408B2/en active Active
- 2020-09-14 CN CN202010959502.2A patent/CN112542438B/zh active Active
- 2020-09-14 DE DE102020211500.1A patent/DE102020211500A1/de active Pending
- 2020-09-14 TW TW109131491A patent/TWI777238B/zh active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011049244A (ja) | 2009-08-25 | 2011-03-10 | Shindengen Electric Mfg Co Ltd | 樹脂封止型半導体装置 |
US20150214139A1 (en) | 2014-01-30 | 2015-07-30 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2015142072A (ja) | 2014-01-30 | 2015-08-03 | 株式会社東芝 | 半導体装置 |
US20180331021A1 (en) | 2017-05-09 | 2018-11-15 | Taiwan Semiconductor Co., Ltd. | Die package component with jumper structure and manufacturing method thereof |
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Publication number | Publication date |
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JP2021048376A (ja) | 2021-03-25 |
TW202125740A (zh) | 2021-07-01 |
TWI777238B (zh) | 2022-09-11 |
CN112542438B (zh) | 2024-04-16 |
CN112542438A (zh) | 2021-03-23 |
US20210090976A1 (en) | 2021-03-25 |
US11289408B2 (en) | 2022-03-29 |
DE102020211500A1 (de) | 2021-03-25 |
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