CN110520983A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN110520983A CN110520983A CN201880021615.9A CN201880021615A CN110520983A CN 110520983 A CN110520983 A CN 110520983A CN 201880021615 A CN201880021615 A CN 201880021615A CN 110520983 A CN110520983 A CN 110520983A
- Authority
- CN
- China
- Prior art keywords
- protrusion
- semiconductor wafer
- fixture
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 193
- 239000004020 conductor Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000002093 peripheral effect Effects 0.000 claims description 15
- 235000012431 wafers Nutrition 0.000 description 105
- 229910000679 solder Inorganic materials 0.000 description 44
- 238000004519 manufacturing process Methods 0.000 description 32
- 238000000034 method Methods 0.000 description 27
- 239000011347 resin Substances 0.000 description 26
- 229920005989 resin Polymers 0.000 description 26
- 230000008569 process Effects 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 11
- 238000005476 soldering Methods 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000009434 installation Methods 0.000 description 3
- 239000011265 semifinished product Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
- H01L2224/0901—Structure
- H01L2224/0903—Bonding areas having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
- H01L2224/091—Disposition
- H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/09181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29007—Layer connector smaller than the underlying bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32258—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/3301—Structure
- H01L2224/3303—Layer connectors having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75754—Guiding structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75754—Guiding structures
- H01L2224/75755—Guiding structures in the lower part of the bonding apparatus, e.g. in the apparatus chuck
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75754—Guiding structures
- H01L2224/75756—Guiding structures in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9221—Parallel connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
本发明提出能够更加适当地使半导体晶片散热的半导体装置。提出的半导体装置具有:半导体晶片,具有半导体基板和在所述半导体基板的表面设置的表面电极;及导体板,具有板状部和从所述板状部突出的凸部,并且所述凸部的端面与所述表面电极连接。所述凸部的所述端面的宽度比所述凸部的所述板状部侧的基部的宽度窄。
Description
技术领域
本说明书所公开的技术涉及半导体装置。
背景技术
日本专利公开第2009-146950号公报所公开的半导体装置具有半导体晶片和导体板。半导体晶片具有半导体基板和在半导体基板的表面设置的表面电极。导体板具有板状部和从板状部突出的凸部。凸部的端面连接于表面电极。导体板作为使电流在半导体晶片流动的端子发挥功能,并且也作为用于从半导体晶片散热的散热板发挥功能。
发明内容
发明所要解决的课题
在具有与日本专利公开第2009-146950号公报相同结构的半导体装置中,若在凸部与表面电极的接合面处凸部比表面电极向外侧伸出,则容易对表面电极施加较高的应力。因此,需要使凸部的宽度变窄。
另外,若向半导体晶片通电,则由半导体晶片产生的热经由凸部向板状部传递。此时,若凸部的宽度较窄,则热难以从半导体晶片向板状部传递,无法使半导体晶片充分散热。因此,在本说明书中,提出能够更适当地使半导体晶片散热的半导体装置。
用于解决课题的技术方案
本说明书公开的半导体装置具备:半导体晶片,具有半导体基板和在所述半导体基板的表面设置的表面电极;及导体板。所述导体板具有板状部和从所述板状部突出的凸部。所述凸部的端面与所述表面电极连接。所述凸部的所述端面的宽度比所述凸部的所述板状部侧的基部的宽度窄。
在该半导体装置中,凸部的端面的宽度比凸部的基部的宽度窄。由于凸部的端面的宽度窄,所以能够抑制在将凸部的端面连接于表面电极时在其接合面处凸部的端面比表面电极向外侧伸出。因此,能够将凸部适当地连接于表面电极,能够防止对表面电极施加较高的应力。另外,相比端面,凸部的宽度在基部扩张,因此半导体晶片所产生的热在凸部内从端面侧朝向基部侧以放射状扩张并传递。因此,即便端面的宽度窄,也可高效地使热朝向板状部传递。因此,在该半导体装置中,能够比以往更适当地使半导体晶片散热。
附图说明
图1是半导体装置的俯视图。
图2是图1的II-II线处的剖视图。
图3是图1的III-III线处的剖视图。
图4是与变形例的半导体装置的图2对应的剖视图。
图5是与变形例的半导体装置的图2对应的剖视图。
图6是与变形例的半导体装置的图2对应的剖视图。
图7是与变形例的半导体装置的图2对应的剖视图。
图8是与变形例的半导体装置的图3对应的剖视图。
图9是变形例的半导体装置的分解立体图。
图10是引线框的立体图。
图11是引线框的主端子的放大俯视图。
图12是图10、11的XI-XI线处的剖视图。
图13是图10、11的XII-XII线处的剖视图。
图14是安装了夹具的状态的引线框的立体图。
图15是安装了夹具的状态的主端子的与图11对应的放大俯视图。
图16是安装了夹具的状态的引线框的与图12对应的剖视图。
图17是安装了夹具的状态的引线框的与图13对应的剖视图。
图18是定位后的半导体晶片和引线框的与图11对应的放大俯视图。
图19是定位后的半导体晶片和引线框的与图12对应的剖视图。
图20是定位后的半导体晶片和引线框的与图13对应的剖视图。
图21是回流焊后的半导体晶片和引线框的与图12对应的剖视图。
图22是回流焊后的半导体晶片和引线框的与图13对应的剖视图。
图23是连接了导体板(集电极端子)后的半成品的与图12对应的剖视图。
图24是形成了绝缘树脂层后的半成品的与图12对应的剖视图。
图25是形成了绝缘树脂层后的半成品的俯视图。
图26是通过实施方式的制造方法制造的半导体装置的俯视图。
图27是以往的制造方法的说明图。
图28是以往的制造方法的说明图。
图29是通过以往的制造方法制造的半导体装置的俯视图。
图30是表示位置偏移大时的焊料层的剖视图。
图31是表示变形例的定位用凸部的俯视图。
图32是表示变形例的定位用凸部的剖视图。
图33是表示变形例的定位用凸部的剖视图。
图34是表示变形例的定位用凸部的剖视图。
图35是表示变形例的定位用凸部的俯视图。
图36是表示变形例的定位用凸部的俯视图。
图37是表示变形例的定位用凸部的俯视图。
图38是表示变形例的定位用凸部的俯视图。
图39是表示变形例的定位用凸部的俯视图。
图40是表示变形例的定位用凸部的俯视图。
图41是表示变形例的定位用凸部的俯视图。
图42是表示变形例的定位用凸部的俯视图。
图43是表示变形例的定位用凸部的俯视图。
图44是表示变形例的定位用凹部的剖视图。
具体实施方式
图1所示的实施方式的半导体装置10具有两个半导体晶片40、41、导体板60~64、信号端子26及绝缘树脂70。半导体晶片40、41分别内置有开关元件(例如,IGBT(insulatedgate bipolar transistor,绝缘栅双极型晶体管))。在导体板62的上表面安装有半导体晶片41。在导体板64的上表面安装有半导体晶片40。相对于半导体晶片40、41分别连接有多个信号端子26。在半导体晶片41的上表面连接有导体板61。导体板61连接于导体板63。在半导体晶片40的上表面连接有导体板60。导体板60连接于导体板62。半导体晶片40、41通过绝缘树脂70密封。各导体板62、63、64的一部分向绝缘树脂70的外部突出而构成端子28a、28b、28c。另外,各信号端子26的一部分向绝缘树脂70的外部突出。此外,实施方式的半导体装置10的特征在于半导体晶片40与导体板64连接的连接构造及半导体晶片41与导体板62连接的连接构造。半导体晶片40与导体板64连接的连接构造和半导体晶片41与导体板62连接的连接构造大致相等。因此,以下,对半导体晶片40与导体板64连接的连接构造详细地进行说明。
如图2、3所示,导体板64具有散热板16(板状部)和从散热板16的上表面16a向上侧突出的凸部17。凸部17具有第一凸部18和第二凸部20。第一凸部18从散热板16的上表面16a向上侧突出。第二凸部20从第一凸部18的端面18a(上表面)向上侧突出。如图2所示,第二凸部20的端面20a(上表面)的宽度W2比第一凸部18的宽度W3(即,凸部17的散热板16侧的基部的宽度)窄。即,凸部17的宽度随着从基部朝向端面20a而呈台阶状地变窄。
如图2、3所示,半导体晶片40具有半导体基板42、发射电极44、集电极48及信号电极46。半导体基板42内置有IGBT。发射电极44设置于半导体基板42的第一表面(图2、3中下侧的面)。发射电极44对半导体基板42的第一表面的大部分进行覆盖。信号电极46多个设置于半导体基板42的第一表面。各信号电极46设置于发射电极44的旁边。各信号电极46的尺寸远远小于发射电极44的尺寸。集电极48设置于半导体基板42的第二表面(在图2、3中上侧的面)。集电极48覆盖第二表面的整个区域。半导体晶片40配置为发射电极44位于凸部17的端面20a的上部。发射电极44通过焊料层50与凸部17的端面20a连接。
如图3所示,各信号端子26配置为其前端部位于对应的信号电极46的下部。各信号端子26通过焊料层50与所对应的信号电极46连接。
如图2、3所示,在半导体晶片40的上部配置有导体板60。导体板60配置为其下表面位于集电极48的上部。导体板60的下表面通过焊料层52与集电极48连接。
绝缘树脂70除去导体板64的下表面和导体板60的上表面而覆盖导体板64、焊料层50、半导体晶片40、焊料层52及导体板60。
导体板60、64作为用于使电流在半导体晶片40流动的端子发挥功能,并且作为从半导体晶片40散热的散热构件发挥功能。若作为信号端子26中的一个的栅极端子的电位比阈值高,则半导体晶片40(即,IGBT)接通。在该状态下,若对导体板60施加比导体板64高的电位,则在半导体晶片40流动有电流。若在半导体晶片40流动有电流,则半导体晶片40发热。由半导体晶片40产生的热从导体板60和导体板64散热。图2的箭头90表示导体板64内的散热路径。导体板64的凸部17具有宽度从端面20a朝向散热板16侧变大的形状,因此如箭头90所示热从半导体晶片40朝向散热板16以放射状扩张并传递。因此,容易向散热板16传递热。因此,在本实施方式的半导体装置10中,能够从半导体晶片40高效地散热。
另外,如图2所示,凸部17具有宽度随着从基部(即,散热板16侧)朝向端面20a变窄的形状,因此凸部17的端面20a的宽度W2比发射电极44的宽度W1窄。因此,焊料层50具有其宽度随着从发射电极44侧朝向端面20a侧而变窄的形状。焊料层50具有这样的形状,从而难以对发射电极44的外周缘施加较高的应力。这样,凸部17的端面20a的宽度W2比发射电极44的宽度W1窄,从而可抑制施加于发射电极44的外周缘的应力。
如以上说明那样,在本实施方式的半导体装置10中,凸部17具有宽度随着从基部(即,散热板16侧)朝向端面20a而变窄的形状,从而能够抑制施加于发射电极44的应力,并且充分确保散热路径(即,箭头90)。因此,能够从半导体晶片40高效地散热。
此外,如图4所示,也可以在第一凸部18的端面18a设置有沿着第二凸部20的端面20a的外周缘延伸的槽80。优选槽80包围端面20a的周围。根据该结构,能够通过槽80吸收多余的焊料。即,在经由焊料层50将凸部17和发射电极44连接的工序中,有时焊料的量多。在这种情况下,若设置有槽80,则多余的焊料流入槽80内。作为其结果,能够防止多余的焊料附着于不希望的部分。另外,如图5所示,也可以在第二凸部20的端面20a设置有沿着端面20a的外周缘延伸的槽80。在该结构中也能够通过槽80吸收多余的焊料。
另外,如图6所示,也可以是,凸部17具有宽度随着从基部(散热板16侧)朝向端面20a而变窄的锥形状(即,宽度随着从基部朝向端面20a连续变窄的形状)。这样的结构也与图2相同,能够以放射状传递热。
另外,如图7所示,也可以是,在散热板16的上表面16a设置沿着凸部17的外周缘延伸的槽80。槽80优选包围端面20a的周围。根据该结构,能够由槽80吸收多余的焊料。
另外,图3中,信号端子26通过焊料层50与信号电极46连接。然而,如图8所示,也可以是,信号端子26通过接合线58而与信号电极46连接。
另外,在图1的半导体装置10中,半导体晶片40、41在横向方向(y方向)上排列配置。然而,如图9所示,也可以在层叠构造的半导体装置设置凸部17。在图9中,导体板60、半导体晶片40、导体板64、半导体晶片41及导体板62在它们的厚度方向上层叠。在导体板64的散热板16的上表面设置有凸部17,在该凸部17的端面连接有半导体晶片40的发射电极44。另外,在导体板62的散热板16的上表面设置有凸部17,在该凸部17的端面连接有半导体晶片41的发射电极44。这样的结构也能够经由凸部17而从半导体晶片40、41适当地散热。
(制造方法)
接下来,对半导体装置的制造方法进行说明。以下,对多个制造方法进行说明。通过以下说明的制造方法中的几个方法,能够制造图2、3所示的半导体装置10。另外,通过应用了以下说明的制造方法中的几个方法的制造方法,能够制造图4、8、9的半导体装置。但是,图2、3、4、8、9的半导体装置也可以通过其他的制造方法来制造。
图10~13示出在本实施方式的制造方法中使用的引线框12。引线框12是用于与半导体晶片连接的多个端子相互连接而成的部件。引线框12具备两个裸片焊盘14、主端子28a~28c及多个信号端子26。相对于各裸片焊盘14连接有一个半导体晶片。主端子28a、28c与对应的裸片焊盘14连接。主端子28b是与导体板60(集电极端子60)连接的端子。此外,两个裸片焊盘14的构造及使用方法大致相等,因此以下,以一方的裸片焊盘14(图10的右侧的裸片焊盘14)为中心进行说明。
裸片焊盘14具有散热板16、定位用凸部18(第一凸部18)及接合用凸部20(第二凸部20)。此外,在图11及其以后的放大俯视图中,通过斜线阴影表示定位用凸部18,通过点状阴影表示接合用凸部20。散热板16是厚度比引线框12的其他部分厚的板状的部分。以下,将散热板16的厚度方向称为z方向,将与z方向正交的一方向称为x方向,将与x方向和z方向正交的方向称为y方向。定位用凸部18是从散热板16的上表面向上侧突出的部分。如图11所示,在沿着z方向观察时,定位用凸部18具有大致四边形的形状。接合用凸部20是从定位用凸部18的上表面进一步向上侧突出的部分。如图11所示,在沿着z方向观察时,接合用凸部20具有四边形的形状。如图11、12所示,在接合用凸部20的侧方配置有多个信号端子26。各信号端子26在x方向上较长地延伸,并且在y方向上隔开间隔排列。各信号端子26的一方的端部配置于散热板16的上部。在信号端子26与裸片焊盘14之间设置有间隔。如图10所示,各信号端子26通过系杆22相互连接。另外,各信号端子26通过系杆22及悬吊引线23与裸片焊盘14连接。如图11所示,定位用凸部18未配置于与信号端子26对置的位置。定位用凸部18配置为除去与信号端子26对置的位置而包围接合用凸部20的周围。
在本实施方式的制造方法中,首先,实施夹具安装工序。在夹具安装工序中,如图14~17所示,在引线框12安装夹具30。夹具30具有截面为四边形的筒形状。如图15所示,以夹具30的内周面30a紧贴于定位用凸部18的外周面18b的方式将夹具30卡合于定位用凸部18。由此,夹具30准确地相对于引线框12定位。此外,如图14、16所示,在夹具30的下表面的一部分设置有缺口部30b。在将夹具30安装于引线框12时,缺口部30b配置于与多个信号端子26对应的位置。由于设置有缺口部30b,所以夹具30未与各信号端子26接触。如图15所示,在夹具30与接合用凸部20之间设置有间隔。如图16、17所示,夹具30的高度比接合用凸部20的高度高。
接下来,实施半导体晶片配置工序。在半导体晶片配置工序中,如图18~20所示,在夹具30的内部配置半导体晶片40。即,使夹具30与半导体晶片40卡合。首先,对半导体晶片40进行说明。如图19、20所示,半导体晶片40具有半导体基板42、发射电极44、信号电极46及集电极48。在半导体基板42的内部形成有IGBT(Insulated Gate Bipolar Transistor)。发射电极44和信号电极46设置于半导体基板42的第一表面(图19、20中下侧的面)。此外,图19中图示出单一的信号电极46,但半导体晶片40具有与信号端子26对应的数量(例如,5个)的信号电极46。信号电极46配置于与发射电极44相邻的位置。发射电极44远远大于各信号电极46。信号电极46是IGBT的栅电极、温度检测用的电极、电流检测用的电极、电压检测用的电极等。对信号电极46施加以发射电极44的电位为基准电位的信号。因此,信号电极46与发射电极44之间的电位差小。集电极48对半导体基板42的第二表面(第一表面的相反一侧的表面且图19、20中上侧的面)的整体进行覆盖。
在半导体晶片配置工序中,以发射电极44朝向下侧的方向将半导体晶片40从上侧插入夹具30。由此,将半导体晶片40配置于夹具30的内部。此处,如图19所示,以发射电极44配置在接合用凸部20上、各信号电极46配置在对应的信号端子26的端部上的方式设置半导体晶片40。此时,在发射电极44与接合用凸部20之间及各信号电极46与对应的信号端子26之间夹设焊料层50。如图18所示,在沿着z方向观察时,半导体晶片40的轮廓比定位用凸部18的轮廓(即,外周面18b)稍小。因此,半导体晶片40比夹具30的内周面30a稍小。因此,在夹具30的内部配置半导体晶片40时,可抑制从夹具30向半导体晶片40施加较高的载荷。由此,可抑制半导体基板42产生破裂、缺损。在半导体晶片配置工序中,半导体晶片40的外周面由夹具30的内周面30a引导,因此半导体晶片40相对于夹具30被定位。即,经由夹具30,半导体晶片40相对于引线框12被定位。图18通过虚线表示接合用凸部20和发射电极44。如图18所示,在沿着z方向观察时,接合用凸部20的上表面整体配置于发射电极44的轮廓的内侧。通过使用夹具30,如图18所示能够将发射电极44和接合用凸部20准确地定位。
接下来,实施回流焊工序。在回流焊工序中,使如图18~20所示组装而成的层叠体经过回流焊炉。由此,层叠体暂时被加热,其后,层叠体被冷却至常温。若层叠体被加热,则焊料层50熔融。其后,若层叠体冷却,则焊料层50凝固。于是,如图21、22所示,通过焊料层50,将发射电极44连接于接合用凸部20,并且将信号电极46与对应的信号端子26连接。在实施了回流焊工序后,将夹具30从引线框12及半导体晶片40取下。
接下来,如图23所示,在半导体晶片40上配置集电极端子60(即,导体板60),通过焊料层52将集电极48连接于集电极端子60。集电极端子60是与集电极48连接的布线,并且也是用于从集电极48散热的散热构件。另外,此时,图10的主端子28b与集电极端子60连接。
接下来,如图24、25所示,通过注塑成型形成覆盖半导体晶片40的绝缘树脂层70。与各端子的半导体晶片40连接的部分也被绝缘树脂层70覆盖。各信号端子26及各主端子28a~28c从绝缘树脂层70向外侧突出。
接下来,在绝缘树脂层70的外部将引线框12切断,从而将图25中斜线阴影的部分(系杆22、悬吊引线23等)除去。由此,信号端子26相互分离,并且信号端子26从裸片焊盘14分离。另外,主端子28a~28c相互分离。作为其结果,图26所示的半导体装置完成。
接下来,对以往的半导体装置的制造方法进行说明。在以往的制造方法中,如图27所示,使用集电极用的裸片焊盘160与信号端子126一体化后的引线框112。首先,如图27所示,在第一夹具191上安装引线框112。通过在设置于引线框112的孔112a插入第一夹具191的销191a,从而将引线框112相对于第一夹具191定位。接下来,在引线框112上安装第二夹具192。通过在第二夹具192的孔192a插入第一夹具191的销191a,第二夹具192相对于第一夹具191定位。接下来,在第二夹具192的筒状部192b的内部配置半导体晶片140。半导体晶片140具有半导体基板142、发射电极144、信号电极146及集电极148。此处,以集电极148朝向下侧的方式配置半导体晶片140。其后,经由焊料层150而将集电极148接合于裸片焊盘160。在将集电极148接合于裸片焊盘160后,取下第一夹具191和第二夹具192。
接下来,通过引线接合,将半导体晶片140的各信号电极146连接于引线框112的对应的信号端子126。
接下来,如图28所示,在第三夹具193设置发射极端子114。第三夹具193具有凹部193a,并在该凹部193a内配置发射极端子114。通过凹部193a,将发射极端子114相对于第三夹具193定位。接下来,将连接有半导体晶片140和引线框112的部件安装于第三夹具193。此处,将半导体晶片140的发射电极144配置在发射极端子114的接合用凸部114a上。此处,通过将第三夹具193的销193b插入引线框112的孔112a,从而将引线框112相对于第三夹具193定位。其后,经由焊料层152将发射电极144接合于接合用凸部116a。其后,如图29所示,通过绝缘树脂层170对半导体晶片140进行密封。在绝缘树脂层170形成后,在绝缘树脂层170的外部将引线框112切断,从而将图29中斜线阴影的部分(系杆、悬吊引线等)除去。由此,使各端子相互分离。通过以上的工序,基于以往的方法的半导体装置的制造结束。
在以往的方法中,在发射电极144与接合用凸部116a之间产生将第一夹具191与引线框112的位置偏移、第一夹具191与第二夹具192的位置偏移、第二夹具192与半导体晶片140的位置偏移、第三夹具193与发射极端子114的位置偏移、及第三夹具193与引线框112的位置偏移累积而成的位置偏移。由于位置偏移主要因素多,所以发射电极144与接合用凸部116a的位置偏移容易变大。若发射电极144与接合用凸部116a的位置偏移大,则在半导体晶片140的一部分难以向发射极端子114传递热,半导体晶片140的一部分有时局部成为高温。并且,如图30所示,在发射电极144与接合用凸部114a的位置偏移极大的情况下,有时接合用凸部114a伸出至发射电极144的外侧。在这种情况下,焊料层152扩展至比发射电极144靠外侧,焊料层152成为悬垂状。在该结构中,绝缘树脂层170进入焊料层152与半导体基板142之间的间隙。在该构造中,由于焊料层152与半导体基板142之间的绝缘树脂层170的热膨胀而对焊料层152和发射电极144施加极高的应力,因此焊料层152和发射电极144的可靠性极度降低。
相对于此,在实施方式的方法中,夹具30与引线框12的位置偏移及夹具30与半导体晶片40的位置偏移影响发射电极44与接合用凸部20的位置偏移。位置偏移主要因素少,因此能够抑制发射电极44与接合用凸部20的位置偏移。因此,在半导体装置的量产时,能够使散热性稳定。能够防止制造出散热性差的半导体装置。特别是在实施方式的方法中,如图18所示,发射电极44比接合用凸部20大,因此能够更可靠地防止图30所示那样的情况。因此,能够确保焊料层50与发射电极44的可靠性。
另外,在以往的方法中,使用集电极用的裸片焊盘160和信号端子126一体化后的引线框112。在切断了引线框112(即,图29的斜线部)后,如图29所示,在从绝缘树脂层170露出的位置残存悬吊引线的残存部160a。悬吊引线的残存部160a连接于集电极用的裸片焊盘160,因此在信号端子126(与发射极大致相同电位)与残存部160a(与集电极相同电位)之间产生极大的电位差。因此,容易在信号端子126与残存部160a之间产生沿面放电。因此,在以往的方法中,为了防止沿面放电,需要在残存部160a与信号端子126之间的绝缘树脂层170的侧面设置缺口部180(用于使残存部160a与信号端子126之间的沿面距离变长的凹部)。然而,若设置缺口部180,则存在绝缘树脂层170的内部应力变大、绝缘树脂层170的对于裂缝等的耐受性降低的问题。
相对于此,在实施方式的方法中,使用发射极用的裸片焊盘14与信号端子26一体化后的引线框12。在将引线框12(即,图25的斜线部)切断后,如图26所示,在从绝缘树脂层70露出的位置残存悬吊引线23的残存部23a。残存部23a连接于发射极用的裸片焊盘14,因此信号端子26(与发射极大致相同电位)与残存部23a(与发射极相同电位)之间的电位差极小。因此,在残存部23a与信号端子26之间难以产生沿面放电。因此,在它们之间的绝缘树脂层70的侧面不需要缺口部。因此,绝缘树脂层70的对于裂缝的耐受性提高。另外,不需要缺口部,由此不需要信号端子26与信号电极46的y方向的偏置。由此,能够在信号端子26的两侧设置悬吊引线23,信号端子26与半导体晶片40的位置精度提高。
另外,在实施方式的制造方法中,如图19所示,接合用凸部20从散热板16的上表面向上侧突出,并且在接合用凸部20与夹具30之间设置有间隔,因此能够在信号电极46与散热板16之间确保空间。因此,能够在该空间配置针对信号电极46的布线(即,信号端子26)。因此,能够适当地设置针对信号电极46的布线。
此外,在上述的实施方式中,在将夹具30安装于引线框12后,在夹具30的内部配置半导体晶片40。然而,也可以是,在夹具30的内部配置了半导体晶片40后,将夹具30安装于引线框12。但是,实施方式的顺序多是容易稳定实施各工序的情况。
另外,在上述的实施方式中,接合用凸部20与定位用凸部18相连。然而,如图31、32所示,也可以是,定位用凸部18配置于离开接合用凸部20的位置。
另外,在上述的实施方式中,接合用凸部20比定位用凸部18高,但也可以是,如图33、图34所示,接合用凸部20和定位用凸部18为相同的高度。
另外,在上述的实施方式中,定位用凸部18沿着接合用凸部20的周围配置。然而,如图35~36所示,也可以是,定位用凸部18离散地设置于接合用凸部20的周围。若能够将夹具30定位,则定位用凸部18也可以任意配置。
另外,在上述的实施方式中,夹具30具有筒形状。然而,如图39~40所示,夹具30也可以具有除筒形状以外的形状。此外,图42示出通过夹具30将两个半导体晶片40、41(相对于两个接合用凸部20连接的半导体晶片)定位的结构。在这些结构中,也能够通过夹具30与引线框12的定位部和半导体晶片40双方卡合,来将引线框12与半导体晶片40定位。另外,如图43所示,也可以是,夹具30在板状的构件设置有四边形的孔。
另外,在上述的实施方式中,定位用凸部18的上表面整体接合于焊料层50。然而,也可以对定位用凸部18的上表面的外周部实施不具有焊料浸润性的表面处理(例如,粗糙化处理等)。在该结构中,定位用凸部18的上表面的一部分(中央部)接合于焊料层50。在这种情况下,优选定位用凸部18的上表面的具有焊料浸润性的部分(即,连接于焊料的区域)比发射电极44小。
另外,在上述的实施方式中,通过定位用凸部18使夹具30定位。然而,如图44所示,也可以取代定位用凸部18而设置定位用凹部19。通过使夹具30的外周面30c与定位用凹部19的侧面接触,能够使夹具30定位。
以下列记本说明书公开的技术要素。此外,以下的各技术要素分别是即使独立也有用的要素。
在本说明书公开的一个例子的半导体装置中,也可以是,凸部的宽度随着从基部朝向端面而呈台阶状地变窄。另外,在本说明书公开的其他的一个例子的半导体装置中,也可以是,凸部的宽度随着从基部朝向端面而连续变窄。
在本说明书公开的一个例子的半导体装置中,也可以是,在凸部的表面或者在与凸部相邻的板状部的表面设置有沿着凸部的端面的外周缘延伸的槽。
根据这样的结构,在将凸部的端面经由焊料而连接于半导体晶片的表面电极时,多余的焊料被吸收到槽内。由此,能够防止多余的焊料附着于不希望的位置。
在本说明书公开的一个例子的半导体装置中,也可以是,半导体晶片具有设置于表面的信号电极。另外,也可以是,半导体装置还具有与信号电极连接的信号端子。
(相关技术的公开)
针对本说明书公开的制造方法,与以往技术比较,并且以下进行说明。
日本专利公开第2009-146950号公报公开了一种半导体装置,引线框具有接合用凸部,接合用凸部与半导体晶片的主电极连接。通过引线框的接合用凸部,可确保用于设置信号布线的空间。通过在引线框插入定位用的销,抑制半导体晶片与引线框之间的位置偏移。
在如日本专利公开第2009-146950号公报那样采用具有接合用凸部的引线框的情况下,在主电极焊接接合用凸部时,有时产生位置偏移。若引线框的接合用凸部的位置相对于半导体晶片的主电极偏移,则热难以从半导体晶片向引线框传递。因此,半导体装置的散热性降低。在日本专利公开第2009-146950号公报的方法中,在引线框需要用于插入销的孔,在孔的位置处阻碍散热。因此,在本说明书中,提供能够不阻碍散热而进行引线框和半导体晶片的定位的方法。
本说明书公开的半导体装置的制造方法使用夹具将半导体晶片连接于引线框。上述半导体晶片在一个面具有主电极。上述引线框具有接合用凸部和由在上述接合用凸部的周围配置的凸形状或者凹形状构成的定位部。上述制造方法具有:以在上述接合用凸部与上述夹具之间隔开间隔的状态使上述夹具卡合于上述定位部的工序;使上述夹具卡合于上述半导体晶片的工序;以及在上述夹具与上述定位部和上述半导体晶片卡合的状态下,将上述接合用凸部经由焊料连接于上述半导体晶片的上述主电极的工序。
在该制造方法中,夹具卡合于引线框的定位部,因此可抑制引线框与夹具的位置偏移。另外,夹具卡合于半导体晶片,因此可抑制半导体晶片与夹具的位置偏移。因此,经由夹具而使引线框和半导体晶片定位。因此,可抑制引线框与半导体晶片之间的位置偏移。在像这样经由夹具而定位的状态下半导体晶片的主电极经由焊料而接合于引线框的接合用凸部。因此,可抑制接合用凸部相对于主电极位置偏移,能够防止半导体装置的散热性的降低。另外,在该方法中,定位部通过凸形状或者凹形状构成,因此不会在定位部阻碍散热。因此,根据该制造方法,能够稳定地制造散热性高的半导体装置。
在本说明书公开的一个例子的制造方法中,也可以是,上述定位部为上述凸形状。也可以是,在使上述夹具卡合于上述定位部的上述工序中,使上述夹具的侧面与上述凸形状的侧面接触。
在本说明书公开的其他的一个例子的制造方法中,也可以是,上述定位部为上述凹形状。也可以是,在使上述夹具卡合于上述定位部的上述工序中,使上述夹具的侧面与上述凹形状的侧面接触。
在本说明书公开的一个例子的制造方法中,也可以是,在上述夹具与上述定位部和上述半导体晶片卡合的状态下,在沿着上述半导体晶片和上述引线框的层叠方向观察时,上述接合用凸部的与上述焊料连接的区域整体配置于上述主电极的轮廓的内侧。
根据该结构,能够防止连接主电极和接合用凸部的焊料成为悬垂状。
在本说明书公开的一个例子的制造方法中,也可以是,在使上述夹具卡合于上述定位部的上述工序后,实施使上述夹具卡合于上述半导体晶片的上述工序。
在本说明书公开的一个例子的制造方法中,也可以是,上述主电极为发射电极。也可以是,上述半导体晶片具有设置于与上述发射电极同一面的信号电极和在位于上述发射电极的相反一侧的背面设置的集电极。也可以是,上述引线框具备具有上述接合用凸部和上述定位部的主体部及从上述主体部延伸的信号端子。也可以是,上述制造方法还具有:将上述信号端子连接于上述信号电极的工序;在上述集电极连接集电极端子的工序;在将上述接合用凸部、上述信号端子及上述集电极端子连接于上述半导体晶片后,形成覆盖上述半导体晶片的绝缘树脂层的工序;及在形成了上述绝缘树脂层后,将上述信号端子从上述主体部切去的工序。
在该制造方法中,在将信号端子和主体部切去后,信号端子和主体部在绝缘树脂的外部露出。然而,信号端子(即,信号电极)与主体部(即,发射电极)之间的电位差小,因此难以在它们之间产生沿面放电。
另外,本说明书提供散热性高的半导体装置。该半导体装置在一个面具备具有主电极的半导体晶片和引线框。上述引线框具有接合用凸部和由在上述接合用凸部的周围配置的凸形状或者凹形状构成的定位部。上述接合用凸部经由焊料而连接于上述主电极。
该半导体装置能够通过上述的制造方法来制造。该半导体装置由于定位部由凸形状或者凹形状构成,因此不会在定位部阻碍散热而散热性高。
以上,对实施方式详细地进行了说明,但这些只不过为例示,未对请求保护的范围进行限定。请求保护的范围所记载的技术包括以上例示的具体例进行了各种变形、变更的技术。本说明书或者附图说明的技术要素单独或者通过各种组合来发挥技术有用性,不限定为申请时请求保护的范围所记载的组合。另外,本说明书或者附图例示的技术是同时实现多个目的的技术,实现其中的一个目的的情况自身具有技术有用性。
Claims (6)
1.一种半导体装置,具有:
半导体晶片,具有半导体基板和在所述半导体基板的表面设置的表面电极;及
导体板,具有板状部和从所述板状部突出的凸部,所述凸部的端面与所述表面电极连接,
所述凸部的所述端面的宽度比所述凸部的所述板状部侧的基部的宽度窄。
2.根据权利要求1所述的半导体装置,其中,
所述凸部的宽度随着从所述基部朝向所述端面而以台阶状变窄。
3.根据权利要求1所述的半导体装置,其中,
所述凸部的宽度随着从所述基部朝向所述端面而连续变窄。
4.根据权利要求1~3中任一项所述的半导体装置,其中,
在所述凸部的表面或者与所述凸部相邻的所述板状部的表面设置有沿着所述端面的外周缘延伸的槽。
5.根据权利要求4所述的半导体装置,其中,
所述槽设置于所述凸部的所述端面。
6.根据权利要求1~5中任一项所述的半导体装置,其中,
所述半导体晶片具有设置于所述表面的信号电极,
所述半导体装置还具有与所述信号电极连接的信号端子。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017065283A JP6874467B2 (ja) | 2017-03-29 | 2017-03-29 | 半導体装置とその製造方法 |
JP2017-065283 | 2017-03-29 | ||
PCT/JP2018/005584 WO2018179981A1 (ja) | 2017-03-29 | 2018-02-16 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN110520983A true CN110520983A (zh) | 2019-11-29 |
Family
ID=63524640
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201880021615.9A Pending CN110520983A (zh) | 2017-03-29 | 2018-02-16 | 半导体装置 |
CN201810263524.8A Active CN108695177B (zh) | 2017-03-29 | 2018-03-28 | 半导体装置及其制造方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810263524.8A Active CN108695177B (zh) | 2017-03-29 | 2018-03-28 | 半导体装置及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US20200035588A1 (zh) |
JP (2) | JP6874467B2 (zh) |
CN (2) | CN110520983A (zh) |
DE (2) | DE112018001743T5 (zh) |
WO (1) | WO2018179981A1 (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10431528B2 (en) * | 2016-02-08 | 2019-10-01 | Mitsubishi Electric Corporation | Semiconductor device |
US10541223B2 (en) * | 2017-05-05 | 2020-01-21 | Kulicke And Soffa Industries, Inc. | Methods of operating a wire bonding machine to improve clamping of a substrate, and wire bonding machines |
JP7141316B2 (ja) | 2018-11-21 | 2022-09-22 | 日立Astemo株式会社 | パワー半導体装置 |
JP7215320B2 (ja) * | 2019-05-15 | 2023-01-31 | 株式会社デンソー | 半導体装置 |
JP7207150B2 (ja) * | 2019-05-15 | 2023-01-18 | 株式会社デンソー | 半導体装置 |
JP2020198388A (ja) * | 2019-06-04 | 2020-12-10 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP7327134B2 (ja) * | 2019-12-12 | 2023-08-16 | 株式会社デンソー | 半導体装置 |
DE112020006643T5 (de) * | 2020-01-30 | 2022-11-24 | Mitsubishi Electric Corporation | Halbleitervorrichtung und leistungswandler |
CN112289752B (zh) * | 2020-12-01 | 2023-04-11 | 江苏捷捷微电子股份有限公司 | 一种倒装GaN功率器件封装结构及其制备方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001156219A (ja) * | 1999-11-24 | 2001-06-08 | Denso Corp | 半導体装置 |
CN1649098A (zh) * | 2004-01-30 | 2005-08-03 | 株式会社电装 | 半导体器件 |
US20070057373A1 (en) * | 2005-09-12 | 2007-03-15 | Denso Corporation | Semiconductor device having metallic plate with groove |
CN102460694A (zh) * | 2009-06-19 | 2012-05-16 | 株式会社安川电机 | 电力变换装置 |
CN102881659A (zh) * | 2011-07-14 | 2013-01-16 | 三菱电机株式会社 | 半导体装置以及半导体装置的制造方法 |
CN103081104A (zh) * | 2010-09-30 | 2013-05-01 | 日立汽车系统株式会社 | 功率半导体模块及其制造方法 |
JP2013123016A (ja) * | 2011-12-12 | 2013-06-20 | Denso Corp | 半導体装置 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0831558B2 (ja) * | 1991-03-29 | 1996-03-27 | 日本碍子株式会社 | 半導体装置の組立方法 |
JPH06252320A (ja) * | 1993-02-25 | 1994-09-09 | Toppan Printing Co Ltd | リードフレーム並びにボンディング治具及びそのボンディング方法 |
JP2001298033A (ja) * | 2000-04-12 | 2001-10-26 | Hitachi Ltd | 半導体装置 |
JP3836010B2 (ja) * | 2001-10-19 | 2006-10-18 | 三菱電機株式会社 | 半導体装置 |
JP4814639B2 (ja) * | 2006-01-24 | 2011-11-16 | 富士通セミコンダクター株式会社 | 半導体装置および半導体装置の製造方法 |
US7838974B2 (en) * | 2007-09-13 | 2010-11-23 | National Semiconductor Corporation | Intergrated circuit packaging with improved die bonding |
JP4952556B2 (ja) * | 2007-12-11 | 2012-06-13 | 株式会社デンソー | 半導体装置およびその製造方法 |
US8497572B2 (en) * | 2010-07-05 | 2013-07-30 | Denso Corporation | Semiconductor module and method of manufacturing the same |
JP5745238B2 (ja) * | 2010-07-30 | 2015-07-08 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置およびその製造方法 |
CN102522340A (zh) * | 2011-12-21 | 2012-06-27 | 杭州士兰集成电路有限公司 | 一种大功率模块的散热片安装方法 |
CN202816923U (zh) * | 2012-08-10 | 2013-03-20 | 福建闽航电子有限公司 | 一种集成电路陶瓷封装外壳用的引线框架 |
US9847235B2 (en) * | 2014-02-26 | 2017-12-19 | Infineon Technologies Ag | Semiconductor device with plated lead frame, and method for manufacturing thereof |
JP5910653B2 (ja) * | 2014-03-18 | 2016-04-27 | トヨタ自動車株式会社 | 放熱板付きリードフレーム、放熱板付きリードフレームの製造方法、半導体装置、および半導体装置の製造方法 |
JP6256145B2 (ja) * | 2014-03-26 | 2018-01-10 | 株式会社デンソー | 半導体装置及びその製造方法 |
JP6485397B2 (ja) * | 2016-04-04 | 2019-03-20 | 株式会社デンソー | 電子装置及びその製造方法 |
JP6485398B2 (ja) * | 2016-04-13 | 2019-03-20 | 株式会社デンソー | 電子装置及びその製造方法 |
JP6610590B2 (ja) * | 2017-03-21 | 2019-11-27 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
-
2017
- 2017-03-29 JP JP2017065283A patent/JP6874467B2/ja active Active
-
2018
- 2018-02-16 US US16/491,328 patent/US20200035588A1/en not_active Abandoned
- 2018-02-16 DE DE112018001743.5T patent/DE112018001743T5/de active Pending
- 2018-02-16 WO PCT/JP2018/005584 patent/WO2018179981A1/ja active Application Filing
- 2018-02-16 CN CN201880021615.9A patent/CN110520983A/zh active Pending
- 2018-02-16 JP JP2018512232A patent/JP7156025B2/ja active Active
- 2018-02-22 US US15/902,479 patent/US20180286702A1/en not_active Abandoned
- 2018-03-27 DE DE102018204668.9A patent/DE102018204668A1/de active Pending
- 2018-03-28 CN CN201810263524.8A patent/CN108695177B/zh active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001156219A (ja) * | 1999-11-24 | 2001-06-08 | Denso Corp | 半導体装置 |
CN1649098A (zh) * | 2004-01-30 | 2005-08-03 | 株式会社电装 | 半导体器件 |
US20070057373A1 (en) * | 2005-09-12 | 2007-03-15 | Denso Corporation | Semiconductor device having metallic plate with groove |
CN102460694A (zh) * | 2009-06-19 | 2012-05-16 | 株式会社安川电机 | 电力变换装置 |
CN103081104A (zh) * | 2010-09-30 | 2013-05-01 | 日立汽车系统株式会社 | 功率半导体模块及其制造方法 |
CN102881659A (zh) * | 2011-07-14 | 2013-01-16 | 三菱电机株式会社 | 半导体装置以及半导体装置的制造方法 |
JP2013123016A (ja) * | 2011-12-12 | 2013-06-20 | Denso Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
DE102018204668A1 (de) | 2018-10-04 |
CN108695177A (zh) | 2018-10-23 |
US20200035588A1 (en) | 2020-01-30 |
JP2018170348A (ja) | 2018-11-01 |
CN108695177B (zh) | 2021-11-02 |
WO2018179981A1 (ja) | 2018-10-04 |
JPWO2018179981A1 (ja) | 2020-03-05 |
JP6874467B2 (ja) | 2021-05-19 |
JP7156025B2 (ja) | 2022-10-19 |
DE112018001743T5 (de) | 2019-12-19 |
US20180286702A1 (en) | 2018-10-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110520983A (zh) | 半导体装置 | |
US9391006B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
US9966327B2 (en) | Lead frame, semiconductor device, method for manufacturing lead frame, and method for manufacturing semiconductor device | |
JP3267045B2 (ja) | Led素子 | |
US9691730B2 (en) | Semiconductor device and method for manufacturing the same | |
US10170394B2 (en) | Semiconductor device | |
CN104103611B (zh) | 加压加热接合结构及加压加热接合方法 | |
US9159715B2 (en) | Miniaturized semiconductor device | |
CN106952897A (zh) | 半导体装置及其制造方法 | |
US9214418B2 (en) | Lead frame with radiator plate, method for manufacturing lead frame with radiator plate, semiconductor device, and method for manufacturing semiconductor device | |
US9786587B2 (en) | Semiconductor device and method for manufacturing the semiconductor device | |
CN107527883A (zh) | 半导体装置及其制造方法以及导电柱 | |
CN106298700A (zh) | 半导体装置 | |
US20170194296A1 (en) | Semiconductor module | |
US9666557B2 (en) | Small footprint semiconductor package | |
JP2015176871A (ja) | 半導体装置及びその製造方法 | |
JP2015026791A (ja) | 半導体装置及びリードフレーム | |
JP5762319B2 (ja) | 電力用半導体装置および電力用半導体装置の製造方法 | |
US11742251B2 (en) | Power semiconductor device including press-fit connection terminal | |
US20230327350A1 (en) | Transfer molded power modules and methods of manufacture | |
CN107195622A (zh) | 半导体装置 | |
CN116207523A (zh) | 用于电子装置的焊料停止特征 | |
US11244922B2 (en) | Semiconductor device | |
JP5132407B2 (ja) | 半導体装置 | |
JP4534675B2 (ja) | 集積回路装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20200410 Address after: Aichi Prefecture, Japan Applicant after: DENSO Corp. Address before: TOYOTA City, Aichi Prefecture, Japan Applicant before: Toyota Motor Corp. |
|
TA01 | Transfer of patent application right | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191129 |
|
RJ01 | Rejection of invention patent application after publication |