CN102881659A - 半导体装置以及半导体装置的制造方法 - Google Patents
半导体装置以及半导体装置的制造方法 Download PDFInfo
- Publication number
- CN102881659A CN102881659A CN2012100898453A CN201210089845A CN102881659A CN 102881659 A CN102881659 A CN 102881659A CN 2012100898453 A CN2012100898453 A CN 2012100898453A CN 201210089845 A CN201210089845 A CN 201210089845A CN 102881659 A CN102881659 A CN 102881659A
- Authority
- CN
- China
- Prior art keywords
- metallic object
- insulating barrier
- semiconductor element
- semiconductor device
- metallic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
- H01L2224/3018—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/30181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
- H01L2224/37599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本发明的目的在于提供一种能够抑制针对半导体元件的应力并提高散热性能的半导体装置及其制造方法。本发明的半导体装置具有:半导体元件(1);第一金属体(2),设置在半导体元件(1)背面上;第一绝缘层(4),设置在第一金属体(2)背面上;第二金属体(3),设置在第一绝缘层(4)背面上;第三金属体(9),设置在半导体元件(1)表面上;第二绝缘层(10),设置在第三金属体(9)表面上;以及第四金属体(11),设置在第二绝缘层(10)表面上,第二金属体(3)比第一金属体(2)薄,第四金属体(11)比第三金属体(9)厚。
Description
技术领域
本发明涉及一种半导体装置以及半导体装置的制造方法,特别涉及内置MOSFET或IGBT等的一个或多个功率半导体元件对马达等负载进行控制的功率半导体装置。
背景技术
半导体装置中的半导体元件特别是功率半导体元件对马达等大的负载进行控制。因此,进行控制的电流大,自发热也大。因此,容纳功率半导体元件的功率半导体装置特别地需要充分的散热性。
以往的功率半导体元件搭载在绝缘基板上,该绝缘基板接合在金属板上,进而容纳在壳体中。在功率半导体元件的上表面电极连接有多个接合线(bonding wire),该接合线的另一端与绝缘基板上的布线或者在进行容纳的壳体上安装的电极连接。另一方面,功率半导体元件的背面电极焊接在绝缘基板上的布线上。
功率半导体装置在金属板表面隔着润滑脂等安装在冷却器上,在功率半导体元件中所产生的热经由焊料、绝缘基板、金属板等在冷却器中进行散热。
另外,为了供给用于使功率半导体元件工作的电压,在与功率半导体元件的上表面电极同一平面上设置有控制电极,如上述那样,利用接合线与基板上的布线或者在壳体上安装的电极连接。流过大电流的布线或电极与控制用的布线或电极设置在同一基板表面上或壳体表面上的情况比较多。
功率半导体元件大多用于MOSFET或IGBT这样的控制大电流的用途,由功率半导体装置来控制数A~数百A左右的电流。因此,为了提高功率半导体装置的冷却性能,公开了例如专利文献1所示那样的功率半导体装置。
专利文献1所示的功率半导体装置包括具有集电极电极以及形成在与控制电极同一面上的发射极电极的多个半导体元件,进而,还具有以夹着这些半导体元件的方式设置并且在夹着的一侧的面配设了用于与半导体芯片的电极接合的电极图案的高导热性绝缘基板。将高导热性基板的电极图案和半导体元件的电极进行钎焊,从而进行接合。
专利文献1:日本特开平10-56131号公报。
但是,以往的半导体装置以夹着半导体元件的表面和背面的方式设置绝缘基板,所以,存在因装配的偏差而使绝缘基板的表面的平行度恶化这样的问题。特别是,如专利文献1公开的功率半导体装置那样,在使用氮化铝等陶瓷作为绝缘基板的情况下,绝缘基板非常硬,所以,在绝缘基板的表面安装冷却器时,存在发生了一端接触的情况。在冷却器和绝缘基板之间产生大的间隙,所以,润滑脂层变厚,散热性能恶化。
进而,对硬且脆的绝缘基板和半导体元件的局部施加过大的力,由此,有可能将这些破坏。
发明内容
本发明是为了解决上述问题而提出的,其目的在于提供能够抑制针对半导体元件的应力并提高散热性能的半导体装置及其制造方法。
本发明提供一种半导体装置,其特征在于,具有:半导体元件;第一金属体,设置在所述半导体元件背面上;第一绝缘层,设置在所述第一金属体背面上;第二金属体,设置在所述第一绝缘层背面上;第三金属体,设置在所述半导体元件表面上;第二绝缘层,设置在所述第三金属体表面上;以及第四金属体,设置在所述第二绝缘层表面上,所述第二金属体比所述第一金属体薄,所述第四金属体比所述第三金属体厚。
本发明提供一种半导体装置的制造方法,其特征在于,包括如下工序:(a)在半导体元件背面上配设第一金属体;(b)在所述第一金属体背面上配设第一绝缘层;(c)在所述第一绝缘层背面上配设第二金属体;(d)在所述半导体元件表面上配设第三金属体;(e)在所述第三金属体表面上配设第二绝缘层;(f)在所述第二绝缘层表面上配设第四金属体,所述工序(c)是配设比所述第一金属体薄的所述第二金属体的工序,所述工序(f)是配设比所述第三金属体厚的所述第四金属体的工序。
根据本发明的半导体装置,具有:半导体元件;第一金属体,设置在所述半导体元件背面上;第一绝缘层,设置在所述第一金属体背面上;第二金属体,设置在所述第一绝缘层背面上;第三金属体,设置在所述半导体元件表面上;第二绝缘层,设置在所述第三金属体表面上;以及第四金属体,设置在所述第二绝缘层表面上,所述第二金属体比所述第一金属体薄,所述第四金属体比所述第三金属体厚,由此,在半导体元件表面侧设置厚度薄的第三金属体,能够抑制针对半导体元件施加的应力,另外,在半导体元件背面侧设置厚度厚的第一金属体,能够低热阻化,提高散热性。
根据本发明的半导体装置的制造方法,包括:包括如下工序:(a)在半导体元件背面上配设第一金属体;(b)在所述第一金属体背面上配设第一绝缘层;(c)在所述第一绝缘层背面上配设第二金属体;(d)在所述半导体元件表面上配设第三金属体;(e)在所述第三金属体表面上配设第二绝缘层;(f)在所述第二绝缘层表面上配设第四金属体,所述工序(c)是配设比所述第一金属体薄的所述第二金属体的工序,所述工序(f)是配设比所述第三金属体厚的所述第四金属体的工序,由此,在半导体元件表面侧设置厚度薄的第三金属体,能够抑制针对半导体元件的应力,另外,在半导体元件背面侧设置厚度厚的第一金属体,能够低热阻化,提高散热性。
附图说明
图1是实施方式1的半导体装置的示意剖视图。
图2是表示实施方式1的半导体装置的变形例的示意剖视图。
图3是表示实施方式1的半导体装置的变形例的示意剖视图。
图4是实施方式1的半导体装置的制造流程图。
图5是实施方式1的半导体装置的平面图。
其中,附图标记说明如下:
1 半导体元件
2 第一金属体
3 第二金属体
4 第一绝缘层
5a、5b主端子
6 信号端子
9 第三金属体
10 第二绝缘层
11 第四金属体
12 接合线
13 模塑树脂
14 金属基板
15、17 第五金属体。
具体实施方式
<A.实施方式1>
<A-1.结构>
图1是用于说明本发明的实施方式的半导体装置的示意剖视图。
如图1所示,本发明的半导体装置具有:半导体元件1,在表面具有器件结构(元件结构);第一金属体2,经由焊料7连接在作为半导体元件1的背面侧的下方向;第一绝缘层4,设置在第一金属体2的下方向;第二金属体3,设置在第一绝缘层4的下方向;第三金属体9,经由焊料8连接在作为半导体元件1的表面侧的上方向;第二绝缘层10,设置在第三金属体9的上方向;第四金属体11,设置在第二绝缘层10的上方向。在此,半导体元件1可以是以碳化硅为主要成分的元件。在是以碳化硅为主要成分的元件的情况下,提高冷却性能,由此,能够实现耐压更高的半导体装置。
如图1所示,第二金属体3在上下方向形成得比第一金属体2薄。另外,第四金属体11在上下方向形成得比第三金属体9厚。
另外,主端子5a以及主端子5b分别与第一金属体2以及第三金属体9连接,半导体元件1和信号端子6经由接合线12而连接。主端子5a以及主端子5b可以是预先与第一金属体2以及第三金属体9成为一体的构件,在该情况下,能够省略用于连接的工序。
另外,能够在半导体元件1的表面侧形成用于驱动半导体元件1或者用于进行传感检测(sensing)的输入输出电极。这些电极利用接合线12与信号端子6连接。
进而,能够用模塑树脂13覆盖整体,在该情况下,第二金属体3的下方向的面以及第四金属体11的上方向的面从模塑树脂13露出。
在半导体元件1的背面侧(下方向)经由焊料等接合层(在图1中为焊料7)设置有第一金属体2。在第一金属体2的下方向即与半导体元件1相对的面侧配置有第一绝缘层4,进而,在其下方向配置有第二金属体3。
在半导体元件1的背面侧,在半导体元件1的正下方设置厚度厚的第一金属体2,从而能够使热充分地扩散以确保散热性。第一金属体2的厚度与第二金属体3的厚度相比充分厚即可。此外,设置左右方向的面积比半导体元件1大的第一金属体2,从而能够提高热的扩散性,提高散热性(使热阻(thermal resistance)降低)。
在第一绝缘层4的下方向设置的第二金属体3是为了保护第一绝缘层4而设置的,对于其厚度来说,只要足够用于进行保护,较薄也可以。由于较薄能够减小热阻,所以优选。具体地说,优选例如为0.01~0.5mm左右。
此外,若将厚度薄的金属体设置在半导体元件1的正下方,则如后述那样,能够减轻针对半导体元件1的机械应力,但是,在厚度薄的金属体的正下方设置的绝缘层设置在半导体元件1的附近。在这样的结构中,半导体元件1产生的热未充分扩散而到达该绝缘层,导致散热性恶化。因而,在本实施方式中,在半导体元件1的正下方设置厚度厚的金属体(第一金属体2)。
另一方面,在具有半导体元件1的元件结构的表面侧(上方向),与背面侧的情况同样地,经由焊料等接合层(在图1中为焊料8)配置有第三金属体9。在第三金属体9的上方向即与半导体元件1相对的面侧配置有第二绝缘层10,进而,在其上方向配置有第四金属体11。
在半导体元件1的表面侧,在半导体元件1的正上方设置厚度薄的第三金属体9,由此,能够减小针对包括起到沟道部、栅极电极等的半导体的功能的层的器件结构的机械应力,提高器件的可靠性。第三金属体9的厚度与第四金属体11的厚度相比充分薄即可,但具体地说,优选例如为0.1~1.5mm左右。
若将与第一金属体2相同程度的厚度的金属体设置在半导体元件1的正上方,则对立体地形成在半导体元件1的有源面(active surface)上的器件结构(元件结构)施加机械应力,有可能使其特性降低。因而,在本实施方式中,在半导体元件1的正上方设置厚度薄的金属体(第三金属体9)。
此外,在半导体元件1的表面侧形成有信号电极等,另外,在边缘部设置有用于确保耐压的区域,所以,与半导体元件1的背面侧相比,能够接合的面积变小。因此,需要减小第三金属体9的左右方向的面积。通过减小该面积,能够减小机械应力。
另外,在第三金属体9的正上方形成第二绝缘层10,从而能够减小针对第三金属体9上表面的散热路径的机械应力,此外,能够实现高的散热性。
由于第二绝缘层10的强度低,所以,优选预先由第四金属体11保持无法由模具保持的第二绝缘层10。在该状态下进行模塑,由此,能够提高第二绝缘层10的强度,能够实现具有绝缘性优良的绝缘层的两面绝缘结构。
进而,除了第三金属体9之外,第三金属体9、第二绝缘层10、第四金属体11也能够使用通过加压冲压等方法预先被一体化的层压基板(laminate substrate)。通过这样形成,从而能够进一步提高强度,能够实现具有绝缘性优良的绝缘层的两面绝缘结构。
另外,第三金属体9、第二绝缘层10、第四金属体11也能够形成电路基板。通过这样形成,从而模塑时的供给变得容易,能够可靠地确保绝缘层和金属体之间的紧贴。
在此,在从外侧用冷却器夹着装配半导体装置的情况下,优选第四金属体11的上表面确保与半导体装置的背面侧即第二金属体3的背面的所希望的平行度。否则,在对在半导体装置的外侧设置的冷却器进行安装时,在冷却器和半导体装置之间间隙变大,存在散热性恶化的情况。
因此,能够预先将第四金属体11形成得厚,在使用模塑树脂13进行模塑后,磨削第四金属体11的上表面,调整其露出和平行度。此时,为了不因研磨阻力(grinding resistance)对第二绝缘层10造成损伤,也优选第四金属体11形成得比第二金属体3厚。
另外,为了在半导体装置的上下表面实现以及保持高的平行度,优选以在半导体元件1的上下配置的金属体的刚性为相同程度的方式构成。
相对于此,在本发明的半导体装置中,在半导体元件1的背面侧设置厚度厚的第一金属体2,进而经由第一绝缘层4设置厚度薄的第二金属体3。另一方面,在半导体元件1的表面侧设置厚度薄的第三金属体9,进而,经由第二绝缘层10设置厚度厚的第四金属体11。
通过这种结构,作为整体能够使夹持半导体元件l的上下方向的结构体的刚性为相同程度,能够减小模塑后的半导体装置的翘曲。因而,向冷却器的安装变得容易,此外,能够减小针对半导体元件1的机械应力。
此外,图5是用于说明本发明的实施方式的半导体装置的平面图。如图5所示,第四金属体11的上方向的面从模塑树脂13露出,另外,信号端子6、主端子5a以及主端子5b分别从模塑树脂13的侧面延伸。
图2是表示本实施方式的半导体装置的变形例的示意剖视图。对与图1同样的结构标注相同的附图标记,省略其详细说明。
在本变形例中,在半导体元件1的表面侧,在半导体元件1和第三金属体9之间设置第五金属体15。第五金属体15经由例如焊料等接合层(在图2中为焊料16)与第三金属体9接合。
若第五金属体15的上表面高于接合线12的弯曲部分(loop)所到达的上下方向的高度,则第三金属体9与接合线12不会发生干涉,所以优选。因此,优选使第五金属体15的上下方向的厚度厚到满足该条件的程度。
设置第五金属体15,由此,在发热的半导体元件1和第二绝缘层10之间,热充分地扩散,因此,第二绝缘层10的到达温度(attained temperature)降低。因此,能够防止第二绝缘层10和第三金属体9之间或第二绝缘层10和第四金属体11之间的由温度循环引起的剥离。另外,也能够防止由有机材料等构成的第二绝缘层10的由温度引起的变质。
另外,在图2中,第五金属体15如在图2中用(a)所示那样,在由焊料8连接的部分外侧的金属体端部设置有倾斜部。即,第五金属体15具有末端部向上方向扩展的形状。通过这样形成,能够维持半导体元件1周边的耐压,并且能够进一步扩散热。此外,不仅可以为如图示那样的倾斜形状,而且也可以具有例如朝向上方向且左右方向的宽度变大那样的阶梯形状。
此外,也能够形成预先使第二绝缘层10、第三金属体9、第五金属体15一体化的金属基板14,设置在半导体装置内部。这样一来,能够将厚度厚的第四金属体11可靠地设置在第二绝缘层10的上方,工业价值提高。
图3是表示按每个半导体分别配置第五金属体17的情况。对与图2相同的结构标注相同的附图标记,并省略其详细说明。
存在半导体元件1由于其种类而上下方向的厚度不同的情况。在该情况下,分别设置第五金属体17,利用厚度不同的焊料等接合层(在图3中为焊料16)吸收厚度方向上的差异,由此,即使设置例如各自厚度相等的第五金属体17,也能够适当装配。反之,在使用厚度相等的焊料16的情况下,对应于各半导体元件1设置厚度不同的第五金属体17,从而也能够适当装配。
此外,关于在对第五金属体17进行分割来设置时的分割方法即按每个半导体元件1进行分割还是对多个半导体元件1形成一个金属体、还是进而对它们进行组合,根据电路结构做成适当的结构即可。
另外,各第五金属体17也可以具有如图2所示那样的向上方向的末端扩展形状,进而,也可以形成预先使第二绝缘层10、第三金属体9和第五金属体17一体化的金属基板。
<A-2.制造方法>
在图4中示出图3所示的半导体装置的制造流程。
首先,将半导体元件1(芯片)配置在第一金属体2之上进行接合。此时,若也同时接合第五金属体17,则能够省略工序(图4(a))。
另外,能够预先通过加压冲压等一体化制造第二绝缘层10、第三金属体9、第四金属体11,根据需要与主端子5b焊接。
对它们进行装配之后,如图4(b)所示那样进行模塑成型。此时,在第四金属体11的上方也设置模塑树脂13的层。
之后,将半导体装置上表面研磨至预定的厚度(图4(c))。这样一来,能够良好地维持半导体装置的上下表面的平行度。因此,在安装在冷却器上时不会产生不需要空隙,得到良好的散热性能。
由于绝缘层的强度低,所以,预先用第四金属体11保持无法由模具保持的第二绝缘层10进行模塑,从而能够实现具有绝缘性优良的绝缘层的两面绝缘结构。
进而,在模塑时无需使第四金属体11的上表面露出,不需要用于高精度地维持模具的繁杂的管理、高频度的维护,能够可靠地制造上表面良好露出的半导体装置。
另外,预先通过加压冲压等一体地形成第三金属体9、第二绝缘层10、第五金属体17后进行装配来制造半导体装置,从而能够可靠地将绝缘层和金属体粘接。
<A-3.效果>
根据本发明的实施方式,半导体装置具有:半导体元件1;第一金属体2,设置在半导体元件1背面上;第一绝缘层4,设置在第一金属体2背面上;第二金属体3,设置在第一绝缘层4背面上;第三金属体9,设置在半导体元件1表面上;第二绝缘层10,设置在第三金属体9表面上;以及第四金属体11,设置在第二绝缘层10表面上,第二金属体3比第一金属体2薄,第四金属体11比第三金属体9厚,由此,在半导体元件表面侧设置厚度薄的第三金属体9,能够抑制针对半导体元件1施加的压力,另外,在半导体元件1背面侧设置厚度厚的第一金属体2,能够实现低热阻化,能够提高散热性。
另外,在模塑中使模具抵接时产生偏压,由此,使第一绝缘层4以及第二绝缘层10产生倾斜,即使在该情况下,也能够通过在模塑后研磨厚度厚的第四金属体而调整上下表面的平行度。因此,能够抑制因一端接触使散热性能恶化的情况。
另外,根据本发明的实施方式,在半导体装置中,还具有覆盖半导体元件1、第一金属体2、第二金属体3、第三金属体9、第四金属体11、第一绝缘层4、第二绝缘层10而形成的模塑树脂13,第二金属体3的背面从模塑树脂13露出,第四金属体11的表面从模塑树脂13露出,从而能够提高散热性。
另外,即使不使第二金属体3和第四金属体11的平行度为精度高的平行度,由于能够使第四金属体11露出,所以生产率高。
另外,根据本发明的实施方式,在半导体装置中,第三金属体9、第二绝缘层10、第四金属体11作为被一体化的层压基板而形成,由此,能够预先用第三金属体9以及第四金属体11保持无法由模具保持的强度低的第二绝缘层10进行模塑,能够实现绝缘性优良的两面绝缘结构。
另外,根据本发明的实施方式,在半导体装置中,第三金属体9、第二绝缘层10、第四金属体11形成电路基板,从而模塑时的供给变得容易,能够可靠地确保绝缘层和金属体之间的紧贴。
另外,根据本发明的实施方式,在半导体装置中,半导体元件1能够使用以碳化硅为主要成分从而耐压更高的半导体元件,因此能够提供高耐压的半导体装置。
另外,根据本发明的实施方式,在半导体装置中,还具有在半导体元件1和第三金属体9之间设置的第五金属体15或第五金属体17,由此,在发热的半导体元件1和第二绝缘层10之间,热充分地扩散,因此第二绝缘层10的到达温度降低,能够防止由温度引起的变质或剥离。
另外,根据本发明的实施方式,在半导体装置中,第五金属体15或第五金属体17具有末端部向表面的方向扩展的形状,由此,能够维持半导体元件1周边的耐压并且进而使热进行扩散,提高散热性。
另外,根据本发明的实施方式,在半导体装置中,第三金属体9、第二绝缘层10、第五金属体15作为被一体化的金属基板14而形成,由此,能够预先用第三金属体9以及第四金属体11保持无法由模具保持的强度低的第二绝缘层10进行模塑,能够实现绝缘性优良的两面绝缘结构。
另外,根据本发明的实施方式,在半导体装置中,具有多个半导体元件1,与各半导体元件1对应地具有多个第五金属体17,第三金属体9跨越(across)多个第五金属体17的表面而设置,由此,利用金属体和绝缘层的组合,能够将各种变化的电路结构组入半导体装置。
在本发明的实施方式中,对各结构要素的材质、材料、实施条件等进行了记载,但这些仅是例示,并不限于记载的这些。
Claims (13)
1.一种半导体装置,其特征在于,具有:
半导体元件(1);
第一金属体(2),设置在所述半导体元件(1)背面上;
第一绝缘层(4),设置在所述第一金属体(2)背面上;
第二金属体(3),设置在所述第一绝缘层(4)背面上;
第三金属体(9),设置在所述半导体元件(1)表面上;
第二绝缘层(10),设置在所述第三金属体(9)表面上;以及
第四金属体(11),设置在所述第二绝缘层(10)表面上,
所述第二金属体(3)比所述第一金属体(2)薄,
所述第四金属体(11)比所述第三金属体(9)厚。
2.如权利要求1所述的半导体装置,其特征在于,
还具有覆盖所述半导体元件(1)、所述第一~第四金属体(2、3、9、11)、所述第一~第二绝缘层(4、10)而形成的该模塑树脂(13),
所述第二金属体(3)的背面从所述模塑树脂(13)露出,
所述第四金属体(11)的表面从所述模塑树脂(13)露出。
3.如权利要求1或2所述的半导体装置,其特征在于,
所述第三金属体(9)、所述第二绝缘层(10)、所述第四金属体(11)作为被一体化的层压基板而形成。
4.如权利要求1或2所述的半导体装置,其特征在于,
所述第三金属体(9)、所述第二绝缘层(10)、所述第四金属体(11)形成电路基板。
5.如权利要求1或2所述的半导体装置,其特征在于,
所述半导体元件(1)以碳化硅为主要成分。
6.如权利要求1或2所述的半导体装置,其特征在于,
还具有在所述半导体元件(1)和所述第三金属体(9)之间设置的第五金属体(15)。
7.如权利要求6所述的半导体装置,其特征在于,
所述第五金属体(15)具有末端部向所述表面的方向扩展的形状。
8.如权利要求6所述的半导体装置,其特征在于,
所述第三金属体(9)、所述第二绝缘层(10)、所述第五金属体(15)作为被一体化的金属基板(14)而形成。
9.如权利要求6所述的半导体装置,其特征在于,
具有多个所述半导体元件(1),
与各所述半导体元件(1)对应地具有多个所述第五金属体(17),
所述第三金属体(9)跨越多个所述第五金属体(17)表面而设置。
10.一种半导体装置的制造方法,其特征在于,包括如下工序:
(a)在半导体元件(1)背面上配设第一金属体(2);
(b)在所述第一金属体(2)背面上配设第一绝缘层(4);
(c)在所述第一绝缘层(4)背面上配设第二金属体(3);
(d)在所述半导体元件(1)表面上配设第三金属体(9);
(e)在所述第三金属体(9)表面上配设第二绝缘层(10);以及
(f)在所述第二绝缘层(10)表面上配设第四金属体(11),
所述工序(c)是配设比所述第一金属体(2)薄的所述第二金属体(3)的工序,
所述工序(f)是配设比所述第三金属体(9)厚的所述第四金属体(11)的工序。
11.如权利要求10所述的半导体装置的制造方法,其特征在于,
所述工序(d)、(e)、(f)中的所述第三金属体(9)、所述第二绝缘层(10)、所述第四金属体(11)作为被一体化的金属基板(14)而形成,配设在所述半导体元件(1)表面上。
12.如权利要求10或11所述的半导体装置的制造方法,其特征在于,还包括如下工序:
(g)形成覆盖所述半导体元件(1)、所述第一~第四金属体(2、3、9、11)、所述第一~第二绝缘层(4、10)的模塑树脂(13);
(h)使至少所述第四金属体(11)表面从所述模塑树脂(13)露出。
13.如权利要求10或11所述的半导体装置的制造方法,其特征在于,
还包括如下工序(i):在所述工序(d)之前,在所述半导体元件(1)表面上配设第五金属体(15),
所述工序(d)是在所述第五金属体(15)表面上配设第三金属体(9)的工序。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011-155525 | 2011-07-14 | ||
JP2011155525A JP2013021254A (ja) | 2011-07-14 | 2011-07-14 | 半導体装置および半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN102881659A true CN102881659A (zh) | 2013-01-16 |
Family
ID=47425802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2012100898453A Pending CN102881659A (zh) | 2011-07-14 | 2012-03-30 | 半导体装置以及半导体装置的制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20130015468A1 (zh) |
JP (1) | JP2013021254A (zh) |
CN (1) | CN102881659A (zh) |
DE (1) | DE102012211424B4 (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017092628A1 (zh) * | 2015-11-30 | 2017-06-08 | 比亚迪股份有限公司 | 用于igbt模组的散热模组以及具有其的igbt模组 |
CN108206141A (zh) * | 2016-12-19 | 2018-06-26 | 丰田自动车株式会社 | 半导体装置的制造方法 |
CN110098178A (zh) * | 2018-01-30 | 2019-08-06 | 丰田自动车株式会社 | 半导体器件 |
CN110383439A (zh) * | 2017-03-08 | 2019-10-25 | 三菱电机株式会社 | 半导体装置、其制造方法以及半导体模块 |
CN110391195A (zh) * | 2018-04-23 | 2019-10-29 | 意法半导体股份有限公司 | 具有双岛表面安装封装件的功率半导体器件 |
CN110520983A (zh) * | 2017-03-29 | 2019-11-29 | 丰田自动车株式会社 | 半导体装置 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013232495A (ja) * | 2012-04-27 | 2013-11-14 | Mitsubishi Electric Corp | 半導体装置 |
JP6125089B2 (ja) * | 2014-02-24 | 2017-05-10 | 三菱電機株式会社 | パワー半導体モジュールおよびパワーユニット |
DE102014221147A1 (de) * | 2014-10-17 | 2016-04-21 | Robert Bosch Gmbh | Modul mit mindestens einem Leistungshalbleiter |
DE102016120778B4 (de) * | 2016-10-31 | 2024-01-25 | Infineon Technologies Ag | Baugruppe mit vertikal beabstandeten, teilweise verkapselten Kontaktstrukturen |
US20190103342A1 (en) | 2017-10-04 | 2019-04-04 | Infineon Technologies Ag | Semiconductor chip package comprising substrate, semiconductor chip, and leadframe and a method for fabricating the same |
JP7040032B2 (ja) * | 2018-01-17 | 2022-03-23 | 株式会社デンソー | 半導体装置 |
JP7354076B2 (ja) | 2020-09-24 | 2023-10-02 | 株式会社東芝 | 半導体モジュール |
US11658171B2 (en) * | 2020-12-23 | 2023-05-23 | Semiconductor Components Industries, Llc | Dual cool power module with stress buffer layer |
US11502064B2 (en) * | 2021-02-17 | 2022-11-15 | Infineon Technologies Ag | Power semiconductor module having a current sensor module fixed with potting material |
US11874303B2 (en) * | 2021-07-06 | 2024-01-16 | Infineon Technologies Ag | Power semiconductor module with current sensor rotation bar |
JPWO2023047881A1 (zh) * | 2021-09-21 | 2023-03-30 | ||
WO2024018851A1 (ja) * | 2022-07-22 | 2024-01-25 | ローム株式会社 | 半導体装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030022464A1 (en) * | 2001-07-26 | 2003-01-30 | Naohiko Hirano | Transfer-molded power device and method for manufacturing transfer-molded power device |
CN1599063A (zh) * | 2003-09-17 | 2005-03-23 | 株式会社电装 | 具有一对散热器的半导体器件及其制造方法 |
JP2005175130A (ja) * | 2003-12-10 | 2005-06-30 | Toyota Motor Corp | 半導体モジュール、半導体装置および負荷駆動装置 |
US20090224398A1 (en) * | 2008-03-04 | 2009-09-10 | Denso Corporation | Semiconductor module and method of manufacturing the same |
JP2011114176A (ja) * | 2009-11-27 | 2011-06-09 | Mitsubishi Electric Corp | パワー半導体装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3879150B2 (ja) * | 1996-08-12 | 2007-02-07 | 株式会社デンソー | 半導体装置 |
JP3596388B2 (ja) * | 1999-11-24 | 2004-12-02 | 株式会社デンソー | 半導体装置 |
DE10062108B4 (de) * | 2000-12-13 | 2010-04-15 | Infineon Technologies Ag | Leistungsmodul mit verbessertem transienten Wärmewiderstand |
JP2002329804A (ja) * | 2001-04-27 | 2002-11-15 | Denso Corp | 半導体装置 |
JP4281050B2 (ja) * | 2003-03-31 | 2009-06-17 | 株式会社デンソー | 半導体装置 |
JP4302607B2 (ja) * | 2004-01-30 | 2009-07-29 | 株式会社デンソー | 半導体装置 |
JP4338620B2 (ja) * | 2004-11-01 | 2009-10-07 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP2007251076A (ja) * | 2006-03-20 | 2007-09-27 | Hitachi Ltd | パワー半導体モジュール |
DE112009000447B4 (de) * | 2008-04-09 | 2016-07-14 | Fuji Electric Co., Ltd. | Halbleitervorrichtung und Verfahren zu ihrer Herstellung |
JP5009956B2 (ja) * | 2009-05-29 | 2012-08-29 | 三菱電機株式会社 | 半導体装置 |
JP5273101B2 (ja) * | 2010-06-23 | 2013-08-28 | 株式会社デンソー | 半導体モジュールおよびその製造方法 |
-
2011
- 2011-07-14 JP JP2011155525A patent/JP2013021254A/ja active Pending
-
2012
- 2012-02-27 US US13/405,720 patent/US20130015468A1/en not_active Abandoned
- 2012-03-30 CN CN2012100898453A patent/CN102881659A/zh active Pending
- 2012-07-02 DE DE102012211424.6A patent/DE102012211424B4/de not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030022464A1 (en) * | 2001-07-26 | 2003-01-30 | Naohiko Hirano | Transfer-molded power device and method for manufacturing transfer-molded power device |
CN1599063A (zh) * | 2003-09-17 | 2005-03-23 | 株式会社电装 | 具有一对散热器的半导体器件及其制造方法 |
JP2005175130A (ja) * | 2003-12-10 | 2005-06-30 | Toyota Motor Corp | 半導体モジュール、半導体装置および負荷駆動装置 |
US20090224398A1 (en) * | 2008-03-04 | 2009-09-10 | Denso Corporation | Semiconductor module and method of manufacturing the same |
JP2011114176A (ja) * | 2009-11-27 | 2011-06-09 | Mitsubishi Electric Corp | パワー半導体装置 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017092628A1 (zh) * | 2015-11-30 | 2017-06-08 | 比亚迪股份有限公司 | 用于igbt模组的散热模组以及具有其的igbt模组 |
CN108206141A (zh) * | 2016-12-19 | 2018-06-26 | 丰田自动车株式会社 | 半导体装置的制造方法 |
CN110383439A (zh) * | 2017-03-08 | 2019-10-25 | 三菱电机株式会社 | 半导体装置、其制造方法以及半导体模块 |
CN110383439B (zh) * | 2017-03-08 | 2023-04-28 | 三菱电机株式会社 | 半导体装置、其制造方法以及半导体模块 |
CN110520983A (zh) * | 2017-03-29 | 2019-11-29 | 丰田自动车株式会社 | 半导体装置 |
CN110098178A (zh) * | 2018-01-30 | 2019-08-06 | 丰田自动车株式会社 | 半导体器件 |
CN110391195A (zh) * | 2018-04-23 | 2019-10-29 | 意法半导体股份有限公司 | 具有双岛表面安装封装件的功率半导体器件 |
Also Published As
Publication number | Publication date |
---|---|
DE102012211424A1 (de) | 2013-01-17 |
DE102012211424B4 (de) | 2014-05-08 |
US20130015468A1 (en) | 2013-01-17 |
JP2013021254A (ja) | 2013-01-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102881659A (zh) | 半导体装置以及半导体装置的制造方法 | |
US11810887B2 (en) | Double-sided cooling type power module and manufacturing method therefor | |
US9257363B2 (en) | Semiconductor device and method of manufacturing the same | |
US8872332B2 (en) | Power module with directly attached thermally conductive structures | |
CN102437138B (zh) | 半导体装置 | |
KR101876237B1 (ko) | 파워 모듈 및 그 제조 방법 | |
JP6813259B2 (ja) | 半導体装置 | |
US10354940B2 (en) | Semiconductor device | |
CN103000559A (zh) | 半导体芯片的定位夹具以及半导体装置的制造方法 | |
US20180277462A1 (en) | Semiconductor device, manufacturing method for semiconductor device, and electrode plate | |
TW201533857A (zh) | 半導體裝置 | |
CN102648520B (zh) | 用于车辆的电力模块 | |
JP2008270527A (ja) | 電力用半導体モジュール | |
CN111584443A (zh) | 双面散热功率模块及其双面平行度的控制方法 | |
CN102201402A (zh) | 半导体装置 | |
US9698076B1 (en) | Metal slugs for double-sided cooling of power module | |
JP7176397B2 (ja) | 半導体装置とその製造方法 | |
JP2013168421A (ja) | 配線基板および配線基板の製造方法 | |
JP2009170702A (ja) | 半導体モジュール | |
CN104952815A (zh) | 半导体模块以及半导体模块的制造方法 | |
JP4742964B2 (ja) | 実装基板及びその製造方法 | |
US20240096720A1 (en) | Semiconductor module having a double-sided heat dissipation structure and A Method for fabricating the same | |
KR101703724B1 (ko) | 파워 모듈 패키지 | |
JP4084324B2 (ja) | 半導体装置 | |
JP2014093356A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130116 |