JP7141316B2 - パワー半導体装置 - Google Patents
パワー半導体装置 Download PDFInfo
- Publication number
- JP7141316B2 JP7141316B2 JP2018217859A JP2018217859A JP7141316B2 JP 7141316 B2 JP7141316 B2 JP 7141316B2 JP 2018217859 A JP2018217859 A JP 2018217859A JP 2018217859 A JP2018217859 A JP 2018217859A JP 7141316 B2 JP7141316 B2 JP 7141316B2
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- power semiconductor
- conductor
- semiconductor device
- semiconductor element
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- 239000004065 semiconductor Substances 0.000 title claims description 163
- 239000004020 conductor Substances 0.000 claims description 154
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- 238000004519 manufacturing process Methods 0.000 claims description 10
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- 238000002844 melting Methods 0.000 claims 1
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- 229910000679 solder Inorganic materials 0.000 description 56
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- 229910000838 Al alloy Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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- 229910000962 AlSiC Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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Description
図13は、本実施形態に係るパワー半導体装置の正面図である。図12は、本発明の実施形態1に係るパワー半導体装置の展開斜視図である。図1は、本発明の実施形態1に係るパワー半導体装置の断面図である。図1は、図12中のA-A’における断面の一部を示している。
図4は、本発明の実施形態2を示すパワー半導体装置の断面図である。パワー半導体装置製造時の製造時に、絶縁基板5と放熱材8との熱伝導率の差から反りが生じてしまう。この反りにより、接続材7にひずみが生じてしまい、接続材7が破壊されてしまう虞がある。本実施形態では、図4に示されるように、放熱部材8の絶縁基板5を実装する面8bに凹部8dを設ける。これにより、接続材7の端部の接続材厚(はんだ厚)を増加することで、ひずみを低減させ、接続材7の破壊を防止する。凹部8dを設ける位置は、第2導体4の端部から放熱材8への垂線の放熱部材の絶縁基板実装面8bとの交点8eよりも外側に設けてもよい。また、凹部8dを設ける位置は、パワー半導体素子1端部から45度の線4bと放熱部材の絶縁基板実装面8bとの交点8cよりも外側に設けてもよい。このような構成により、熱抵抗の悪化を抑制し、信頼性の高いパワー半導体装置が提供できる。
実施形態1では、第1導体3上に半導体素子1を1個備える構成としていたが、第1導体3上に半導体素子1を複数備える構成としてもよい。これにより、半導体素子が1個の半導体装置を並べるよりも、幅方向の長さを小さくすることができ、より小型化したパワー半導体装置を提供することができる。
図1で示される第1の実施形態では、パワー半導体素子1の表裏面にそれぞれ第1導体3、第2導体4が接続材2により接続され、さらにその外側に絶縁基板5、放熱部材8がそれぞれ接続材6、接続材7で接続された両面冷却構造のパワー半導体装置の例を示した。しかし、図6に示すように、片面冷却構造のパワー半導体装置であってもよい。パワー半導体素子1は、接続材2を介して第2導体4に接される。さらに、パワー半導体素子1は、接続材6を介して絶縁基板5の第1導体層5bに接続され、絶縁基板5の第2導体層5cが放熱部材8に接続されている。ここで、このような構造の場合、第1導体1と絶縁基板5との熱膨張係数の差が大きくなるため、片面冷却構造のパワー半導体装置であったとしても、接続材6のひずみが大きくなってしまうという問題がある。
図7は、本発明の実施形態5を示すパワー半導体装置の断面図である。図1で示される第1の実施形態では、第1導体3および第2導体4の絶縁基板5とはんだ接続されている面の周辺部に設ける凹部3a及び凹部4aの形状が段差形状である例を示した。しかし、凹部3a及び凹部4aの形状が段差形状である場合、段差の角部まで接続材6が埋まらず、空隙が生じてしまう虞がある。そこで、本実施形態では、図7に示されるように、凹部の形状は、凹部3e及び凹部4eのようなテーパ形状に形成する。つまり、前記半導体素子1の電極面の直角方向から見た場合、凹部3e及び凹部4eの深さは、半導体素子1に近い側より遠い側の方が大きくなるように形成される。
図8は、本発明の実施形態5を示すパワー半導体装置の断面図である。図1に示した第1の実施形態では、第1導体3及び第2導体4の絶縁基板5とはんだ接続されている面の周辺部に設ける凹部3a及び凹部4aの形状が段差形状であり、第1導体3、第2導体4の最外周に設けられる場合を示した。本実施形態では、図8に示されるように、第1導体3、第2導体4の最外周に、壁3f及び壁4fが設けられている。この場合も、第1導体、第2導体の周辺部において、接続材6のはんだ材の厚みが他の部分よりも厚くなることにより、はんだのひずみを低減できる。また、凹部3a及び凹部4a以外のはんだの厚は、周辺に比べて相対的に薄いので、熱抵抗を増加させることなく、はんだの疲労破壊を防止でき、信頼性の高いパワー半導体装置が実現できる。また、壁3f及び壁4fは、一部が第1導体層5bと少なくとも一部が接触する構成としてもよい。こうすることで、壁3f及び壁4f付近でのはんだの広がりを防ぎ、よりはんだのはみ出しを防止することができる。
図9は、本発明の実施形態6を示すパワー半導体装置の断面図である。図1に示される実施形態では、第1導体3及び第2導体4にパワー半導体素子1が1つの接続材2により接続されている構造を示したが、本実施形態は、図9に示されるように、多チップ並列駆動のパワー半導体装置にも適用可能である。具体的には、第1導体3及び第2導体4に2つ以上のパワー半導体素子1が接続材2を介して接続される構成する。これにより、横方向の幅を狭くすることができるので、パワー半導体装置の小型化を実現できる。本実施例においても、第2導体4の絶縁基板5とはんだ接続されている面の周辺部には、凹部4aが設けられている。これにより、第2導体4の周辺部において、接続材6の厚みが他の部分よりも厚くなることにより、はんだのひずみを低減できる。また、凹部以外のはんだの厚は、周辺に比べて相対的に薄いので、熱抵抗を増加させることなく、はんだの疲労破壊を防止でき、信頼性の高いパワー半導体装置が実現できる。
本発明に係る実施形態8を図18を用いて説明する。図18は、本発明の実施形態8に係るパワー半導体装置の断面図である。図18に示されるように、本実施例では、第2導体層5cに直接放熱フィン9を設けた構造であってもよい。この場合、放熱フィン9は、アーク溶接等により第2導体層5cに接合される。これにより、小型化や部品点数を低減することができる。
本発明の一実施形態に係るパワー半導体装置の製造方法を図1及び図15を用いて説明する。図15(a)から(d)は、本発明の一実施形態に係るパワー半導体装置の製造工程を示した図である。
Claims (15)
- 一面に第1導体層が配置される第1絶縁基板と、
前記第1導体層に第1接続材を介して接続される第1導体と、
前記第1導体と第2接続材を介して接続される半導体素子と、を備え、
前記半導体素子の電極面の直角方向から見た場合、前記第1導体は、前記半導体素子よりも大きく形成される周辺部を有し、
前記周辺部には、前記第1接続材の厚みが他の部分よりも厚くなるための第1凹部が形成されているパワー半導体装置。 - 請求項1に記載のパワー半導体装置であって、
前記半導体素子の前記第1導体が接続されている面とは反対の面に第4接続材を介して接続される第2導体と、
一面に第3導体層が配置される第2絶縁基板と、を備え、
前記第2導体は、第5接続材を介して前記第3導体層に接続され、
前記半導体素子の電極面の直角方向から見た場合、
前記第2導体は、前記半導体素子よりも大きく形成される周辺部を有し、
前記周辺部には、前記第5接続材の厚みが他の部分よりも厚くなるための第2凹部が形成されているパワー半導体装置。 - 請求項1又は2に記載のパワー半導体装置であって、
前記半導体素子の電極面の直角方向から見た場合、
前記第1凹部の深さは、前記半導体素子に近い側より遠い側の方が大きいパワー半導体装置。 - 請求項1乃至3のいずれかに記載のパワー半導体装置であって、
前記半導体素子の電極面の直角方向から見た場合、
前記第1凹部において、前記電極面と平行である幅方向の長さをWと定義し、深さ方向の長さをDと定義した場合、
W/Dは2以上であるパワー半導体装置。 - 請求項1乃至4のいずれかに記載のパワー半導体装置であって、
前記第1導体の最外周に前記第1接続材の前記第1凹部を形成する壁を有し、
前記壁は、前記第1接続材と接触するパワー半導体装置。 - 請求項5に記載のパワー半導体装置であって、
前記壁は、前記第1導体層と接触するパワー半導体装置。 - 請求項1乃至6のいずれかに記載のパワー半導体装置であって、
前記半導体素子の電極面の直角方向から見た場合、
前記第1凹部は、前記半導体素子の端部から前記第1導体の厚み分だけ離れた点の集合からなる仮想線と前記第1導体の外周との間に形成されるパワー半導体装置。 - 請求項1乃至7のいずれかに記載のパワー半導体装置であって、
前記第1絶縁基板は、他面に第2導体層が配置され、
前記第2導体層に第3接続材を介して接続される放熱部を備えるパワー半導体装置。 - 請求項8に記載のパワー半導体装置であって、
前記第1導体層と前記第2導体層の配列方向から見た場合、
前記放熱部は、前記第1導体よりも大きく形成される第2周辺部を有し、
前記第2周辺部には、前記第3接続材の厚みが他の部分よりも厚くなるための第3凹部が形成されるパワー半導体装置。 - 請求項1乃至7のいずれかに記載のパワー半導体装置であって、
前記第1絶縁基板は、他面に第2導体層が配置され、
前記第2導体層は、放熱するためのフィンを備えるパワー半導体装置。 - 請求項1乃至10のいずれかに記載のパワー半導体装置であって、
前記周辺部は、前記第1凹部が形成される第1辺と、凹部が形成されない第2辺と、により構成され、
前記半導体素子は、当該半導体素子から前記第1辺までの距離が当該半導体素子から前記第2辺までの距離より小さくなるように配置されるパワー半導体装置。 - 請求項1乃至11のいずれかに記載のパワー半導体装置であって、
前記第1絶縁基板と前記第1導体と前記半導体素子を封止する封止部材を備え、
前記第1凹部の深さは、当該深さ方向に沿った前記第1導体の側面の長さよりも小さいパワー半導体装置。 - 請求項1乃至12のいずれかに記載のパワー半導体装置であって、
前記半導体素子を前記第1導体に2個以上備えているパワー半導体装置。 - 引抜により当該引抜の方向に沿って第1凹部を第1導体に形成する第1工程と、
前記第1凹部が形成された前記第1導体の面に第1接続材を介して絶縁基板の第1導体層を配置しかつ前記第1凹部が形成された前記面とは反対側の面に他の接続材を介して半導体素子を配置する第2工程と、
前記第1凹部における前記第1接続材の厚みが他の部分の前記第1接続材よりも厚くなるように当該第1接続材を溶融させる第3工程と、を備えるパワー半導体装置の製造方法。 - 請求項14に記載されたパワー半導体装置の製造方法であって、
前記第2工程において、前記半導体素子から前記第1凹部までの距離が当該半導体素子から前記第1導体の凹部が形成されない一辺までの距離より小さくなるように当該半導体素子が配置されるパワー半導体装置の製造方法。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009070907A (ja) | 2007-09-11 | 2009-04-02 | Toyota Motor Corp | 半導体装置 |
WO2015033515A1 (ja) | 2013-09-04 | 2015-03-12 | 三菱電機株式会社 | 半導体モジュール及びインバータ装置 |
WO2017119286A1 (ja) | 2016-01-04 | 2017-07-13 | 日立オートモティブシステムズ株式会社 | パワー半導体モジュール |
JP2018101664A (ja) | 2016-12-19 | 2018-06-28 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
WO2018179981A1 (ja) | 2017-03-29 | 2018-10-04 | トヨタ自動車株式会社 | 半導体装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH10189845A (ja) | 1996-12-25 | 1998-07-21 | Denso Corp | 半導体素子の放熱装置 |
JP5077536B2 (ja) | 2007-05-08 | 2012-11-21 | 富士電機株式会社 | 半導体装置の製造方法 |
JP5502805B2 (ja) | 2011-06-08 | 2014-05-28 | 日立オートモティブシステムズ株式会社 | パワーモジュールおよびそれを用いた電力変換装置 |
US9585241B2 (en) | 2013-09-24 | 2017-02-28 | Infineon Technologies Ag | Substrate, chip arrangement, and method for manufacturing the same |
KR101755769B1 (ko) * | 2014-10-29 | 2017-07-07 | 현대자동차주식회사 | 양면 냉각 파워 모듈 및 이의 제조 방법 |
-
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009070907A (ja) | 2007-09-11 | 2009-04-02 | Toyota Motor Corp | 半導体装置 |
WO2015033515A1 (ja) | 2013-09-04 | 2015-03-12 | 三菱電機株式会社 | 半導体モジュール及びインバータ装置 |
WO2017119286A1 (ja) | 2016-01-04 | 2017-07-13 | 日立オートモティブシステムズ株式会社 | パワー半導体モジュール |
JP2018101664A (ja) | 2016-12-19 | 2018-06-28 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
WO2018179981A1 (ja) | 2017-03-29 | 2018-10-04 | トヨタ自動車株式会社 | 半導体装置 |
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