JP4847357B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4847357B2 JP4847357B2 JP2007018477A JP2007018477A JP4847357B2 JP 4847357 B2 JP4847357 B2 JP 4847357B2 JP 2007018477 A JP2007018477 A JP 2007018477A JP 2007018477 A JP2007018477 A JP 2007018477A JP 4847357 B2 JP4847357 B2 JP 4847357B2
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- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
11 半導体素子(半導体チップ)
12 ヒートシンク(放熱板)
13 中間層
14 基板
15 サーマルコンパウンド(中間熱伝導材)
21 第1の金属板
22 第2の金属板
24 第3の金属板
31 窪み
32 斜線部(塗布領域)
32A 扇形状領域
33 中心
35 非塗布溝
41 斜線部(塗布領域)
42 非塗布溝
Claims (5)
- 半導体チップを搭載しかつ円形の窪み形状を有する基板を流動性を有する中間熱伝導材を介して放熱板に組み付ける半導体装置の製造方法であり、
前記中間熱伝導材は、組み付け前に、前記放熱板の組み付け面に塗布され、
前記中間熱伝導材の塗布形状は、中心から放射状に形成される形状でありかつ前記中心または中心近くの場所から放射状に延びた円弧形状の未塗布溝を有し、
前記未塗布溝の形状は、前記中心から外周縁に向かうに従って末広がりの形状であることを特徴とする半導体装置の製造方法。 - 前記中間熱伝導材の外周縁の形状は、前記基板に形成された前記円形の前記窪み形状の径よりも大きい径を有する円の円弧の形状であることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記未塗布溝は、前記中心の周りの円周方向にて等間隔で複数形成されていることを特徴とする請求項1または2記載の半導体装置の製造方法。
- 前記未塗布溝を形成する両側の辺部の前記円弧形状は溝内に膨出することを特徴とする請求項1〜3のいずれか1項に記載の半導体装置の製造方法。
- 前記中間熱伝導材は、前記放熱板の前記組み付け面に印刷により均一厚みで塗布されることを特徴とする請求項1〜4のいずれか1項に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007018477A JP4847357B2 (ja) | 2007-01-29 | 2007-01-29 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007018477A JP4847357B2 (ja) | 2007-01-29 | 2007-01-29 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008186958A JP2008186958A (ja) | 2008-08-14 |
JP4847357B2 true JP4847357B2 (ja) | 2011-12-28 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007018477A Expired - Fee Related JP4847357B2 (ja) | 2007-01-29 | 2007-01-29 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP4847357B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103081097A (zh) * | 2010-09-02 | 2013-05-01 | 丰田自动车株式会社 | 半导体模块 |
DE102015116807A1 (de) * | 2015-10-02 | 2017-04-06 | Infineon Technologies Austria Ag | Funktionalisierte Schnittstellenstruktur |
JP7051774B2 (ja) * | 2019-09-25 | 2022-04-11 | 本田技研工業株式会社 | 電気部品組立体の放熱構造、熱伝導シート、電気部品組立体の製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000030312A (ja) * | 1998-07-08 | 2000-01-28 | Tomoe Engineering Co Ltd | 接着剤塗布用金属スクリーン |
JP4091896B2 (ja) * | 2003-10-23 | 2008-05-28 | 三菱電機株式会社 | 半導体装置の製造方法 |
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2007
- 2007-01-29 JP JP2007018477A patent/JP4847357B2/ja not_active Expired - Fee Related
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JP2008186958A (ja) | 2008-08-14 |
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