JP6448418B2 - 電力用半導体装置 - Google Patents
電力用半導体装置 Download PDFInfo
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- JP6448418B2 JP6448418B2 JP2015045442A JP2015045442A JP6448418B2 JP 6448418 B2 JP6448418 B2 JP 6448418B2 JP 2015045442 A JP2015045442 A JP 2015045442A JP 2015045442 A JP2015045442 A JP 2015045442A JP 6448418 B2 JP6448418 B2 JP 6448418B2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
本発明の実施の形態1について、図面を用いて以下に説明する。尚、各図において、同一又は同様の構成部分については同じ符号を付している。便宜的に図で示す上下などの位置関係を示す表現を説明に用いるが、装置中での方向および装置を使用する際の方向とは異なるものである。図1は、実施の形態1に係る電力用半導体装置100の平面図であり、図2は、図1のII-II断面図である。
次に、実施の形態2に係る電力用半導体装置100Bについて説明する。図5は、実施の形態2に係る電力用半導体装置100Bの平面図である。なお、実施の形態2において、実施の形態1で説明したものと同一の構成要素については同一符号を付して説明は省略する。
次に、実施の形態3に係る電力用半導体装置100Cについて説明する。図6は、実施の形態3に係る電力用半導体装置100Cの断面図であり、図5を電力用半導体装置100Cの平面図とした場合のVI-VI線断面図である。なお、実施の形態3において、実施の形態1,2で説明したものと同一の構成要素については同一符号を付して説明は省略する。
次に、実施の形態4に係る電力用半導体装置100Dについて説明する。図7は、実施の形態4に係る電力用半導体装置100Dの平面図である。なお、実施の形態4において、実施の形態1から3で説明したものと同一の構成要素については同一符号を付して説明は省略する。
Claims (6)
- 第1主電極が配置される第1主面を有する半導体素子と、
接合材を介して前記第1主電極と接合される主電極リードと、
前記主電極リードおよび前記半導体素子を封止する封止樹脂と、
前記主電極リードに対して前記第1主電極との接合部に設けられ、かつ、前記接合材の少なくとも一部が配置される貫通孔と、
前記主電極リードに対して前記貫通孔を中心に互いに対向する方向に延びるように設けられ、かつ、前記貫通孔に配置される前記接合材の少なくとも一部が配置される切り欠きと、
を備え、
前記第1主電極と前記接合材との接合面は長方形状であり、
前記切り欠きは、前記接合面における長方形状の対角線と平行に設けられ、
前記主電極リードにおける前記切り欠きの延在方向の先端部に、前記切り欠きの幅よりも大きな開口部が設けられる、電力用半導体装置。 - 第1主電極が配置される第1主面を有する半導体素子と、
接合材を介して前記第1主電極と接合される主電極リードと、
前記主電極リードおよび前記半導体素子を封止する封止樹脂と、
前記主電極リードに対して前記第1主電極との接合部に設けられ、かつ、前記接合材の少なくとも一部が配置される貫通孔と、
前記主電極リードに対して前記貫通孔を中心に互いに対向する方向に延びるように設けられ、かつ、前記貫通孔に配置される前記接合材の少なくとも一部が配置される切り欠きと、
を備え、
前記第1主電極と前記接合材との接合面は長方形状であり、
前記切り欠きは、前記接合面における長方形状の長辺と平行に設けられ、
前記主電極リードにおける前記切り欠きの延在方向の先端部に、前記切り欠きの幅よりも大きな開口部が設けられる、電力用半導体装置。 - 前記半導体素子は、第2主電極が配置される第2主面をさらに備え、
前記電力用半導体装置は、前記第2主電極と接合される金属板をさらに備える、請求項1または請求項2記載の電力用半導体装置。 - 前記切り欠きの延在方向の先端部は、前記第1主電極と前記接合材との接合面の外周部よりも外側に位置する、請求項3記載の電力用半導体装置。
- 前記貫通孔の外周部は、前記切り欠きの延在方向の先端部よりも前記半導体素子に近接する位置に位置する、請求項3または請求項4記載の電力用半導体装置。
- 前記開口部は、前記主電極リードにおける前記第1主電極と前記接合材との接合面の外周部と対応する領域に設けられる、請求項1または請求項2記載の電力用半導体装置。
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Families Citing this family (4)
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CN108109983B (zh) * | 2017-12-14 | 2024-05-10 | 常州星海电子股份有限公司 | 一种汽车专用整流二极管结构 |
US11302655B2 (en) | 2018-06-29 | 2022-04-12 | Mitsubishi Electric Corporation | Semiconductor device including a semiconductor element and a lead frame with a plurality of holes |
JP7359581B2 (ja) | 2019-07-10 | 2023-10-11 | 株式会社デンソー | 半導体装置 |
US20230352376A1 (en) * | 2020-07-20 | 2023-11-02 | Rohm Co., Ltd. | Semiconductor device |
Family Cites Families (6)
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JPS6175553A (ja) * | 1984-09-21 | 1986-04-17 | Hitachi Tobu Semiconductor Ltd | 電子部品 |
JPS6279637A (ja) * | 1985-10-03 | 1987-04-13 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JP2510708B2 (ja) * | 1988-12-02 | 1996-06-26 | ローム株式会社 | 半導体装置 |
JP2002043587A (ja) * | 2000-07-28 | 2002-02-08 | Origin Electric Co Ltd | メサ型ダイオード及びその製造方法 |
JP4112816B2 (ja) * | 2001-04-18 | 2008-07-02 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
JP4498170B2 (ja) * | 2005-03-02 | 2010-07-07 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
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