CN106952897A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN106952897A
CN106952897A CN201610849375.4A CN201610849375A CN106952897A CN 106952897 A CN106952897 A CN 106952897A CN 201610849375 A CN201610849375 A CN 201610849375A CN 106952897 A CN106952897 A CN 106952897A
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Prior art keywords
conductive component
wiring substrate
semiconductor device
substrate
opening
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CN201610849375.4A
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CN106952897B (zh
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稻叶祐树
井上大辅
征矢野伸
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Abstract

本发明提供使大电流流过与半导体芯片的主电极连接的配线部件,抑制过度增加与控制电极连接的配线部件的导电箔的厚度的半导体装置。半导体装置具备:半导体芯片,具备正面和背面,在上述正面具有主电极和控制电极,上述背面固定于上述电路板;第一配线基板,包括第一导电部件,以与上述主电极对置的方式配置,上述主电极与上述第一导电部件电连接;第二配线基板,包含第二导电部件,以与上述控制电极对置的方式配置,具有开口;导电柱,具备一端和另一端,上述一端与上述控制电极电连接且机械连接,上述另一端与上述第二导电部件电连接且机械连接,上述第一导电部件的厚度比上述第二导电部件的厚度厚,上述第一配线基板配置于上述开口的内侧。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
一种作为控制大电流、大电压的半导体装置的功率半导体模块,具备:具有绝缘板和电路板的层叠基板;在正面具有电极,背面固定于上述电路板的半导体芯片;以及外部端子,还具备配线部件,即:与上述半导体芯片的正面和上述电路板对置的印刷电路基板;以及,一端与上述半导体芯片的电极或上述电路板电连接且机械连接、另一端与上述印刷电路基板连接的导电柱(专利文献1)。具备印刷电路基板与导电柱的配线部件与键合线相比,能够流过大电流,且能够使功率半导体模块小型化。
现有技术文献
专利文献
专利文献1:日本特开2014-57005号公报
发明内容
技术问题
在专利文献1所记载的功率半导体模块中,半导体芯片例如是IGBT、功率MOSFET,在其正面形成有主电极和控制电极。多个导电柱中,一部分的导电柱的一端与主电极电连接且机械连接,另一部分的导电柱的一端与控制电极电连接且机械连接。电连接且机械连接在这些导电柱的另一端的印刷电路基板,在其绝缘基板上层叠有以构成规定的电气电路的方式选择性地形成的导电箔,具体而言层叠有铜箔。
在功率半导体模块动作时,印刷电路基板的铜箔因从半导体芯片的主电极流通的电流而引起发热。为了将由该印刷电路基板的发热导致的封装的温度上升抑制到规定的范围内而设计功率半导体模块。
近年来,期望功率半导体模块能够流通比以往更大的电流,为了按照设计方式抑制与此相伴的印刷电路基板的发热,想到的是将印刷电路基板的铜箔的厚度做得比以往的厚。
作为印刷电路基板的铜箔,通过蚀刻选择性地形成有半导体芯片的主电极用的铜箔部分和控制电极用的铜箔部分。该主电极用的铜箔部分的厚度和控制电极用的铜箔部分的厚度由通常的印刷电路基板的制造工艺得到,因而两个厚度相同。因此,如果将印刷电路基板的铜箔的厚度做得比以往的厚度更厚,则控制电极用的铜箔部分的厚度也变厚。
然而,与半导体芯片的主电极用的铜箔部分流通大电流的情况相比,控制电极用的铜箔部分不需要流通像主电极的那样的大电流。因此,如果使印刷电路基板的铜箔的厚度比以往的厚度更厚,则控制电极用的铜箔部分会有不必要的厚度。
此外,如果使印刷电路基板的铜箔的厚度比以往的厚度更厚,则难以通过蚀刻选择性地形成宽度窄的控制电极用的铜箔部分。
本发明为了有利地解决上述问题,目的在于提供一种能够向与半导体芯片的主电极连接的配线部件流通大电流,还能够抑制与控制电极连接的配线部件的导电箔的厚度变得过厚的半导体装置及其制造方法。
技术方案
本发明的一个方式的半导体装置的特征在于,具备:
层叠基板,其具备绝缘板和电路板;
半导体芯片,其具备正面和背面,且在上述正面具有主电极和控制电极,上述背面固定于上述电路板;
第一配线基板,其包括第一导电部件,且以与上述主电极对置的方式配置,上述主电极与上述第一导电部件电连接;
第二配线基板,其包括第二导电部件,且以与上述控制电极对置的方式配置,且具有开口;以及
导电柱,其具备一端和另一端,上述一端与上述控制电极电连接且机械连接,上述另一端与上述第二导电部件电连接且机械连接,
上述第一导电部件的厚度比上述第二导电部件的厚度更厚,
上述第一配线基板配置于上述开口的内侧。
发明效果
根据本发明的半导体装置,能够向与半导体芯片的主电极连接的配线部件流通大电流,还能够抑制不必要地增加与控制电极连接的配线部件的导电箔的厚度。
附图说明
图1是本发明的一个实施方式的功率半导体模块的示意截面图。
图2A是图1的局部放大俯视图。
图2B是图1的局部放大截面图。
图2C是说明本发明的实施方式1的制造方法的流程图。
图3是本发明的另一实施方式的功率半导体模块的主要部分立体图。
图4是图3的功率半导体模块的部件的俯视图。
图5A是表示金属块的与半导体芯片对置的一侧的面的立体图。
图5B是表示金属块的与引线端子接合的一侧的面的立体图。
图6是印刷电路基板的俯视图。
图7是从背面侧观察印刷电路基板的图。
图8是本发明的功率半导体模块的变形例的截面图。
图9是图8的局部放大截面图。
图10是功率半导体模块在模塑成型时的密封树脂的流动的截面图。
图11是本发明的功率半导体模块的制造方法的说明图。
图12是现有的半导体装置的示意截面图。
图13A是图12的局部放大俯视图。
图13B是图12的局部放大截面图。
符号说明
1,11,12:功率半导体模块(半导体装置)
2:层叠基板
2a:绝缘板
2b:电路板
2c:金属板
3:半导体芯片
3a:主电极
3b:控制电极
4:导电柱
5:第一配线基板
6:第二配线基板
15:金属块
16:印刷电路基板
具体实施方式
(实施方式1)
以下,参照附图对本发明的半导体装置的实施方式1进行具体说明。应予说明,本申请的记载中使用的“电连接且机械连接”这一术语不限于通过直接接合将对象物彼此连接的情况,也包括借由焊料、金属烧结材料等导电性的接合材料将对象物彼此连接的情况。
在图1中示出作为本实施方式的半导体装置的功率半导体模块1的示意截面图。在图2A、图2B中示出由图1的II表示的部分的放大截面图。
在图1、图2A、图2B中,作为本实施方式的半导体装置的功率半导体模块1具备:层叠基板2、半导体芯片3、导电柱4、第一配线基板5以及第二配线基板6。另外,功率半导体模块1还具备外部端子7A、7B和密封树脂8。
层叠基板2由绝缘板2a、设置于绝缘板2a的正面即主面的电路板2b以及设置于绝缘板2a的背面的金属板2c层叠而成。绝缘板2a例如由氮化铝、氮化硅、氧化铝等绝缘性陶瓷构成,电路板2b、金属板2c例如由铜等金属构成。作为绝缘板2a,除了可以使用陶瓷以外,还可以使用含有聚酰亚胺等绝缘性树脂、玻璃环氧材料的部件。并且,电路板2b选择性地形成于绝缘板2a上,由此构成规定的电气电路。作为层叠基板2,例如可以使用DCB(DirectCopper Bonding:直接键合铜)基板等。DCB基板是在绝缘板2a上直接接合由铜等构成的电路板2b、金属板2c而成的基板。由于绝缘板2a是绝缘性的,所以与电路板2b和金属板2c电绝缘。在电路板2b的正面,通过焊料9等接合材料电接合且机械接合有半导体芯片3。在金属板2c的背面,热连接且机械连接有后述的冷却器10。该热连接且机械连接的具体的方法,在图示的例子中是通过焊料9等接合材料进行的连接。
半导体芯片3没有特别限定,例如可以是IGBT(Insulated Gate BipolarTransistor:绝缘栅双极晶体管)、功率MOSFET(Metal Oxide Semiconductor FieldEffect Transistor:金属氧化物半导体场效应晶体管)、FWD(Free Wheeling Diode:续流二极管),还可以是在一个半导体芯片中纵向地形成有这些器件的RB-IGBT(ReverseBlocking-Insulated Gate Bipolar Transistor:反向阻断绝缘栅双极型晶体管)、RC-IGBT(Reverse Conducting-Insulated Gate Bipolar Transistor:反向导通绝缘栅双极晶体管)。与由硅构成的半导体芯片相比,由SiC构成的半导体芯片(例如SiC-MOSFET)具有高耐压特性,且能够进行高频下的开关。
半导体芯片3中,具备正面和背面的半导体基板上设有垂直型的开关元件,如图2B所示,半导体芯片3在其正面具备主电极3a和控制电极3b。另外,半导体芯片3在其背面具备主电极(未图示)。例如在半导体芯片3为IGBT的情况下,在正面形成有作为主电极3a的发射电极和作为控制电极3b的栅电极。在背面形成有集电极电极。
半导体芯片3不限于IGBT、功率MOSFET,也可以是在正面具备主电极和控制电极,能够进行开关动作的一个半导体芯片或多个半导体芯片的组合。
导电柱4A是具备一端和另一端的棒状的导电部件,一端以与形成于半导体芯片3的正面侧的主电极3a对置的方式配置。主电极3a与导电柱4A通过例如焊料9等接合材料电连接且机械连接。导电柱4A的另一端电连接且机械连接到与半导体芯片3的主电极3a对置配置的第一配线基板5。
导电柱4B是具备一端和另一端的棒状的导电部件,一端以与形成于半导体芯片3的正面侧的控制电极3b对置的方式配置。导电柱4B的另一端电连接且机械连接到与半导体芯片3的控制电极3b对置配置的第二配线基板6。
控制电极3b与导电柱4B通过例如焊料9等接合材料电连接且机械连接。导电柱4A和导电柱4B具有销形状,适合使用电阻低且导热率高的金属材料,具体而言,优选铜、铝。就导电柱4A、导电柱4B而言,相对于1个半导体芯片3的主电极3a和控制电极3b,分别配置多个导电柱为优选。由此,能够提高导热性。
导电柱4A和第一配线基板5例如通过向形成于第一配线基板5的规定的位置的孔中压入导电柱4A而进行电连接且机械连接。导电柱4B与第二配线基板6例如通过向形成于第二配线基板6的规定的位置的孔中压入导电柱4B而进行电连接且机械连接。除了压入以外,还可以采用焊接、钎焊或嵌缝等方法。
以与半导体芯片3的主电极3a对置的方式配置有第一配线基板5。另外,以与半导体芯片3的控制电极3b对置的方式配置有第二配线基板6。如图2A所示,第二配线基板6在面内具有开口6c,第一配线基板5被配置于该开口6c的内侧。优选第一配线基板5与该开口6c的内侧接触。配置第一配线基板5和第二配线基板6时可以使两者位于同一面内。在图示的例子中,开口6c的俯视形状为长方形,但也可以采用容易固定第一配线基板5的各种形状,可以为多边形、圆形、长圆形等。
如图2B所示,第一配线基板5由第一绝缘基板5a和配置于该第一绝缘基板5a的两个面上的第一导电部件5b层叠而成。在图示的例子中,第一配线基板5的第一导电部件5b形成在第一绝缘基板5a的整个面上。第一绝缘基板5a可以使用由聚酰亚胺等绝缘性树脂构成的绝缘基板、由玻璃环氧材料、陶瓷绝缘板构成的绝缘基板等。第一导电部件5b例如为铜箔。第一配线基板5的第一导电部件5b可以形成于第一绝缘基板5a的一侧的表面,但是为了抑制第一配线基板5的翘曲,另外,为了提高电磁屏蔽性,优选将第一导电部件5b形成在第一绝缘基板5a的两侧的表面。在图示的例子中,第一配线基板5的俯视形状为长方形,但也可以为多边形、圆形、长圆形等。
第二配线基板6由第二绝缘基板6a和配置于该第二绝缘基板6a的两个面上的第二导电部件6b层叠而成。在图示的例子中,第二配线基板6的第二导电部件6b选择性地形成在第二绝缘基板6a上,以此成为用于构成电气电路的规定的配线。应予说明,在图2A中,省略了通过第二导电部件6b的选择性形成而构成的配线图案的图示。通过缩短第二配线基板6的第二导电部件6b的长度,能够使功率半导体模块1小型化。另外,通过仅改变第二配线基板6的第二导电部件6b的配线,能够根据顾客的要求改变控制端子的排列。优选第一配线基板5和第二配线基板6以第一绝缘基板5a的侧面与第二绝缘基板6a的开口6c的内侧侧面对置的方式配置。另外,作为将第一配线基板5与第二配线基板6相互固定的方法,只要不使第一导电部件5b与第二导电部件6b电导通,就可以使用任意方法。例如,可以在开口6c内的第二绝缘基板6a上设置突起,使这些突起与第一绝缘基板5a的侧面嵌合,并进行定位而固定两者。另外,可以在第二配线基板6的开口6c与第一配线基板5之间夹设绝缘性的薄片、隔离物并固定两者。
第二绝缘基板6a可以使用由聚酰亚胺等绝缘性树脂构成的绝缘基板、由玻璃环氧材料或陶瓷绝缘板构成的绝缘基板等。第二导电部件6b例如为铜箔。第二配线基板6的第二导电部件6b可以形成于第二绝缘基板6a的一侧的表面,但是为了抑制第二配线基板6的翘曲,另外,为了提高电磁屏蔽性,优选形成于第二绝缘基板6a的两侧的表面。
第一配线基板5的第一导电部件5b的厚度比第二配线基板6的第二导电部件6b的厚度更厚。由于第一配线基板5的第一导电部件5b的厚度更厚,所以即使在200A(安培)、400A之类的大电流流过第一导电部件5b的情况下也能够抑制该第一导电部件5b的发热。
另外,由于与第一配线基板5的第一导电部件5b的厚度相比,第二配线基板6的第二导电部件6b的厚度相对较薄,所以不会导致将流通几A(安培)的电流的第二导电部件6b做成与第一配线基板5的第一导电部件5b同等的厚度而造成的浪费,另外,为了构成电气电路,可以通过蚀刻容易地选择性地形成第二导电部件6b。
应予说明,第一导电部件5b的厚度为第一绝缘基板5a和第一导电部件5b的层叠方向上的厚度。第二导电部件6b的厚度为第二绝缘基板6a和第二导电部件6b的层叠方向上的厚度。
功率半导体模块1的外部端子7A、7B是使半导体芯片3的正面和背面的主电极3a等与外部之间进行导通的端子,导通主电力。外部端子7A、7B的一端通过例如焊料9等接合材料电连接到层叠基板2的电路板2b上。外部端子7A、7B的另一端从形成功率半导体模块1的外形的密封树脂8的上表面导出到外部。来自外界的主电气的输入和输出从外部端子7A、7B进行。除了外部端子7A、7B以外,功率半导体模块1还具备未图示的控制端子。控制端子是用于控制半导体芯片3的端子,一端通过第二配线基板6与形成于半导体芯片3的正面的控制电极3b电连接。
密封树脂8至少密封半导体芯片3、层叠基板2、第一配线基板5、第二配线基板6、导电柱4A、导电柱4B。密封树脂8例如具有规定的绝缘性能,只要是具有规定的成型性的树脂就没有特别限定,可以使用热固性树脂。密封树脂8具体而言可以使用环氧树脂、马来酰亚胺树脂等。另外,为了提高散热性,还可以在树脂中添加导热性高的材料的填料。填料例如可以使用氧化铝、氮化硼等。
在本实施方式中,利用密封树脂8构成功率半导体模块1的外形,即框体,另外不具备壳体。密封树脂8的成型可以使用模塑成型,更具体而言,可以使用传递模塑法,但不限于传递模塑法。例如也可以利用树脂的灌封成型。另外,功率半导体模块1不限于图示的例子,也可以是除了密封树脂以外还具备壳体的构成。
层叠基板2的金属板2c固定于冷却器10的正面。冷却器10在其内部空间具备多个散热片10b。散热片10b彼此之间的部分成为冷却通路10a。将冷却介质从外部流通到该冷却通路10a中。冷却介质没有特别限定,可以使用乙二醇水溶液、水等液体制冷剂,也可以使用空气那样的气体制冷剂,还可以使用像氟利昂那样,利用在冷却器中蒸发而产生的气化热将冷却器冷却的、能够相变的制冷剂。对于冷却器10与金属板2c的固定,在图示的例子中,通过焊料9等接合材料进行接合。通过焊料9将冷却器10与金属板2c接合,使从半导体芯片3传递到层叠基板2的热再传导到冷却器10。
将半导体芯片3与电路板2b接合的焊料9、将半导体芯片3と导电柱4A或4B接合的焊料9和将冷却器10与金属板2c接合的焊料9可以使用Sn-Ag系、Sn-Cu系、Sn-Sb系、Sn-Sb-Ag系等焊料材料。在功率半导体模块1中,各接合中的焊料9可以使用相同的焊料材料,或者,例如在将半导体芯片3和电路板2b接合的焊料9与将半导体芯片3和导电柱4A等接合的焊料9中也可以使用不同的焊料材料。
如上所述,功率半导体模块1中,第一配线基板5的第一导电部件5b的厚度比第二配线基板6的第二导电部件6b的厚度更厚。
通常,电流流过导体时的发热根据下式的焦耳定律计算。
Q=I2·R·t
这里,Q为热量,I为电流,R为电阻,t为通电时间。
另外,导体的电阻R由下式表示。
R=ρ·L/S
这里,R为电阻,ρ为电阻率,L为导体的长度,S为导体的截面积。
通过上述的2个式子,可知为了抑制施加了电流的导体的发热量,可以使电阻率变小,缩短配线路径,增大截面积。
在产品设计中,需要将由通电引起的发热设定为某一热量以下,但在构成半导体芯片3的主电流的电路的一部分的配线基板中,导电部件的厚度的上限值由配线基板的制造约束决定,可能发生难以大电流化的情况。另外,即使能够增加导电部件的厚度,导电柱的压入所需要的力也得增加,从而导致制造成本变高,另外,难以通过蚀刻选择性地形成宽度窄的控制电极用的导电部件。
因此,为了克服上述问题,有效的是由第一配线基板5与第二配线基板6构成配线基板,并将第一配线基板5的第一导电部件5b的厚度做得比第二配线基板6的第二导电部件6b更厚。
接下来,使用图2C对实施方式1的功率半导体模块1的制造方法进行说明。
首先,准备:具备绝缘板2a和电路板2b的层叠基板2;具备正面和背面,在正面具有主电极3a和控制电极3b的半导体芯片3;包含第一导电部件5b的第一配线基板5;包含比第一导电部件5b更薄的第二导电部件6b,具有开口6c的第二配线基板6;以及,具备一端和另一端,另一端与第二导电部件6b电连接且机械连接的导电柱4B(S1)。
接下来,将半导体芯片3的背面固定于电路板2b上(S2),以与主电极3a对置的方式配置第一配线基板5,将第一导电部件5b与主电极3a电连接(S3),以第一配线基板5位于开口6c的内侧的方式,与控制电极3b对置地配置第二配线基板6,将导电柱4B的一端与控制电极3b电连接且机械连接(S4)。
在这样的制造方法中,优选第一配线基板5具备具有正面和背面的第一绝缘基板5a,第一导电部件5b可以形成于第一绝缘基板5a的正面和背面中的至少一方。另外,第二配线基板6具备具有正面和背面的第二绝缘基板6a,第二导电部件6b可以形成于第二绝缘基板6a的正面和背面中的至少一方。此外,第二绝缘基板6a上可以设有开口6c。
(实施方式2)
接下来,参照附图对本发明的半导体装置的实施方式2进行具体说明。
在图3中,以立体图的形式示出作为本实施方式2的半导体装置的功率半导体模块11的主要部分。为了容易理解,在图3中,省略了外部端子7A、外部端子7B和密封树脂8的图示,图示了被密封树脂8密封之前的主要部分的样子。应予说明,在以下的附图中,对与图1和图2A、图2B中示出的部件相同的部件标注相同的符号。因此,在以下的说明中,对已经说明的部件省略重复的说明。
在图3中,具备2个半导体芯片3(图中未出现)。半导体芯片3例如是RC-IGBT。RC-IGBT在一个芯片中包含IGBT元件和FWD元件。
在层叠基板2的电路板2b上,电连接且机械连接有半导体芯片3(图中未出现)。在形成于该半导体芯片3的正面的主电极3a(图中未出现)上电连接且机械连接有作为第一配线基板的金属块15。另外,在形成于半导体芯片3的正面的控制电极3b(图中未出现)上,以对置的方式配置作为第二配线基板的印刷电路基板16,介由导电柱4B将印刷电路基板16的第二铜箔部分16c与控制电极3b电连接。
在印刷电路基板16的可挠性绝缘板16a上,选择性地形成有用于控制电极的、形成为窄宽度的第二铜箔部分16c,在该第二铜箔部分16c的长度方向的一端,通过压入等方式电连接且机械连接有导电柱4B的一端(上端)。另外,在第二铜箔部分16c的长度方向的另一端,利用焊料9等接合材料接合有作为控制端子的外部端子7C的一端(下端)。可挠性绝缘板16a相当于本发明的第二绝缘基板,第二铜箔部分16c相当于本发明的第二导电部件。
在半导体芯片3的一个金属块15上,通过激光熔接等方式接合有宽度宽的引线端子7d。另外,在半导体芯片3的另一个金属块15上,通过激光熔接等方式接合有宽度宽的引线端子7e。另外,在层叠基板2的电路板2b上,通过激光熔接等方式接合有宽度宽的引线端子7f。
图4是去掉了图3所示出的部件中的印刷电路基板16、引线端子7d、引线端子7e和引线端子7f后的俯视图。即,在图4中示出了层叠基板2的绝缘板2a、电路板2b、半导体芯片3、金属块15。在图4中,电路板2b被划分为第一电路部2ba、第二电路部2bb、第三电路部2bc、第四电路部2bd和第五电路部2be。
第一电路部2ba与一个半导体芯片3A的背面的主电极电连接。该第一电路部2ba具备突起部2bf,将该突起部2bf的顶面与引线端子7f激光接合。第二电路部2bb与另一个半导体芯片3B的背面的主电极电连接。第四电路部2bd被配置在与外部端子7C的下端对置的位置。第四电路部2bd与外部端子7C可以电连接,也可以不连接。第五电路部2be被配置在与外部端子7C的下端对置的位置。第五电路部2be与外部端子7C可以电连接,也可以不连接。
2个RC-IGBT被配置在层叠基板2上,该2个RC-IGBT与电路板2b、金属块15、引线端子7d、引线端子7e、引线端子7f和印刷电路基板16连接而构成逆变器电路的上下臂。可以在1个层叠基板2上配置电并联连接的2个1组的总计2组的半导体芯片3,构成逆变器电路的一相中的上臂和下臂。
涉及金属块15,图5A是表示与半导体芯片3对置的一侧的面的立体图,图5B是表示与引线端子7d或引线端子7e接合的一侧的面的立体图。如图5A、图5B所示,图中举例示出的金属块15,具有与半导体芯片3的主电极3a几乎相同的面积且具有大致长方形的平面形状,并具备:具有规定厚度的板状的基部15a;和从该基部15a突出的多个销部15b。基部15a可以为大致长方体形状。通过焊料9等接合材料将销部15b的前端与半导体芯片3的主电极3a电连接且机械连接。金属块15是铜、铝等导电性和导热性良好的金属制的金属块。另外,基部15a的厚度,即,基部15a中的与半导体芯片3对置的一侧的面与接合到引线端子7d或引线端子7e的一侧的面之间的距离比印刷电路基板16的第一铜箔部分16b的厚度更厚。因此,能够使大电流流过金属块15。另外,金属块15由散热性良好的材料构成,并且,能够在销部的各销之间的空间进行散热。因此,通过使用金属块15,能够抑制通电时的发热。
应予说明,销部15b的各销的形状不特别限于图示的圆柱状,也可以是棱柱状,还可以是翅片状。
通过使用金属块15,不会像现有的半导体装置使用厚铜箔的印刷电路基板的情况那样,的向铜箔压入导电柱时所必须的力,另外,避免导电柱折断或弯曲等。
另外,作为本实施方式的金属块15的变形例,可举出没有销部15b的金属块。换言之,可以是仅有基部15a的板状的金属块。此时,在板状的金属块具有贯通其厚度方向的孔的结构也属于本实施方式的金属块15的变形例。
图6是从正面观察印刷电路基板16而得到的图,图7是从背面观察印刷电路基板16而得到的图。在图6、图7中,对于印刷电路基板16,在可挠性绝缘板16a的两个面选择性地形成有第一铜箔部分16b和第二铜箔部分16c。其中,第一铜箔部分16b和第二铜箔部分16c可以仅形成于可挠性绝缘板16a的单面。
通过缩短印刷电路基板16的第二铜箔部分16c的长度,能够使功率半导体模块1小型化。另外,通过改变第二铜箔部分16c的配线,能够根据顾客需求改变控制端子的排列。
可挠性绝缘板16a由具有挠性的绝缘性树脂构成,例如可以使用聚酰亚胺树脂。可挠性绝缘板16a形成有用于插入金属块15并使其贯穿的开口16d。在该开口16d,沿着周边形成有多个舌片16e。由于插入金属块15并使其贯穿,因而该舌片16e形成为与金属块15的侧面接触并翘曲的形状。可以以金属块15与印刷电路基板16位于同一面内的方式配置两者。由此,在相对于金属块15定位印刷电路基板16的状态下使两者固定为一体。应予说明,舌片16e的形状不受图示例子的限定。
开口16d中的舌片16e以外的部分是向开口16d插入金属块15并使其贯穿时形成间隙的部分。该间隙被舌片16e限定。通过形成被该舌片16e限定的间隙,从而在密封树脂8的模塑成型时,密封树脂8能够通过该间隙并进行流通。
像使用图3进行说明那样,第二铜箔部分16c在印刷电路基板16的可挠性绝缘板16a上形成为控制电极用的宽度窄的形状。在该第二铜箔部分16c的长度方向的一端,通过压入等方式电连接且机械连接有导电柱4B的一端(上端)。印刷电路基板16与层叠基板之间的间隔根据一端与第二铜箔部分16c接合、另一端与半导体芯片3的控制电极3b接合的导电柱4B的长度而确定。
在第二铜箔部分16c的长度方向的另一端形成贯通印刷电路基板16的厚度方向的孔,在该贯通孔插入外部端子7C的一端(下端),并通过压入或使用焊料9等接合材料进行电连接且机械连接。该外部端子7C的下端可以与层叠基板2的第四电路部2bd或第五电路部2be接触,也可以不接触。
第一铜箔部分16b在开口16d附近不干扰第二铜箔部分16c的范围,且不阻碍舌片16e的变形的范围内形成在可挠性绝缘板16a上。利用第一铜箔部分16b抑制印刷电路基板16的变形,另外,提高电磁屏蔽性。
本实施方式的功率半导体模块11具备金属块15和印刷电路基板16,金属块15的基部15a的厚度比印刷电路基板16的第二铜箔部分16c的厚度更厚。在一个例子中,基部的厚度为0.5~3.0mm。如果基部的厚度为0.5mm以上,则即使在大电流流过金属块15的情况下也能够抑制该金属块15的发热。如果基部的厚度为3.0mm以下,则能够利用适当厚度的焊料9来接合半导体芯片3的主电极3a与销部15b之间,从而保持功率半导体模块11的可靠性。
另外,印刷电路基板16的第一铜箔部分16b的厚度没有像金属块15的基部15a的厚度那样厚,在一个例子中,第一铜箔部分16b的厚度为0.1~0.3mm。如果第一铜箔部分16b的厚度为0.1mm以上,则能够形成足够可以流通控制用的电流的、满足充分必要厚度的第二铜箔部分16c。另外,如果第一铜箔部分16b的厚度为0.3mm以下,则为了构成电气电路,能够通过蚀刻容易选择性地形成与第一铜箔部分16b同时形成的第二铜箔部分16c。
此外,印刷电路基板16上形成有开口16d,通过使金属块15贯穿该开口16d,从而能够使接合有金属块15的、半导体芯片3中的控制电极3b的位置与连接到印刷电路基板16的第二铜箔部分16c的一端的、导电柱4B的一端的位置定位在相互对置的位置上。即,能够在不需要用于对位的夹具的情况下,仅通过使金属块15贯穿印刷电路基板16的开口16d,就能够自动且精度良好地定位控制电极3b的位置与导电柱4B的一端的位置。因此,能够以低成本制造可靠性高的功率半导体模块。经实际制作了实施方式2的功率半导体模块11的结果,确认了能够自动且精度良好地定位控制电极3b的位置与导电柱4B的一端的位置的事实。
特别是,在开口16d处形成有由印刷电路基板16的可挠性绝缘板16a构成的舌片16e的功率半导体模块11具有以下效果。下面,使用图8、图9说明该效果。
图8是功率半导体模块11的变形例的功率半导体模块12的截面图,图9是图8的功率半导体模块12中的金属块15和印刷电路基板16附近的放大截面图。应予说明,在图8、图9中,对与图1~图7中示出的部件相同的部件标注相同的符号,并在下文中省略重复的说明。
图8和图9中示出的功率半导体模块12的外部端子的形状与图3中示出的功率半导体模块11不同。但是,与功率半导体模块11同样地,在印刷电路基板16的开口16d处形成有由可挠性绝缘板16a构成的舌片16e。
通过以突出的方式形成舌片16e,从而如果在印刷电路基板16的开口16d的大小比金属块15的基部15a的大小更小的情况下使金属块15贯穿开口16d的话,,则如图9中放大截面图所示,舌片16e成为与金属块15接触并翘曲的状态。由此,在印刷电路基板16相对于金属块15被定位的状态下,两者被固定为一体。因此,能够自动且精度良好地定位控制电极3b的位置与导电柱4B的一端的位置,进而能够以低成本制造可靠性高的功率半导体模块。
另外,通过形成有舌片16e,可以针对大小不同的多种金属块15使舌片16e翘曲,从而可以在一个印刷电路基板上进行定位,固定。
此外,在开口16d中,由于舌片16e以外的部分是向开口16d插入金属块15并使其贯穿通时形成间隙的部分,所以能够抑制密封树脂8在模塑成型时的空隙。图10用箭头表示功率半导体模块12中的在模塑成型时的密封树脂8的流动。由于在印刷电路基板16的上方,阻碍流动的部件少,所以密封树脂8能够快速、大量地进行流动,而在印刷电路基板16与层叠基板2之间,阻碍流动的部件多,因此密封树脂8会相对低速,少量流动。以印刷电路基板16为边界,由于流动的不同而容易产生空隙,所以,根据舌片16e以外的部分是向开口16d插入金属块15并使其贯穿时形成间隙的部分这样的结构,密封树脂8可以通过该间隙从比印刷电路基板16更靠上方的位置起向印刷电路基板16与层叠基板2之间流动。由此,能够有效地抑制空隙。在所涉及的模塑件内,从印刷电路基板16到模模塑件上壁的距离L1为1.0~3.0mm的程度,印刷电路基板16与层叠基板2之间的距离L2为0.3~2.0mm的程度。如果从印刷电路基板16到模塑件上壁的距离L1为1.0mm以上,则即使功率半导体模块12因热等发生变形,密封树脂8也不易破裂。如果从印刷电路基板16到模塑件上壁的距离L1为3.0mm以下,则容易制造,能够降低成本,此外,功率半导体模块12的变形量变小,能够保持其可靠性。另外,如果印刷电路基板16与层叠基板2之间的距离L2为0.3mm以上,则树脂的流动性良好,能够抑制空隙的产生。如果印刷电路基板16与层叠基板2之间的距离L2为2.0mm以下,则不发生在销的压入时销弯曲,或在传递模塑时因树脂的流动而导致销弯曲等不良情况。从印刷电路基板16到模具上壁的距离L1与印刷电路基板16和层叠基板2之间的距离L2之比可以为0.5~10。
接下来,对实施方式2的功率半导体模块12的制造方法进行说明。
如图11所示,通过焊料9将半导体芯片3接合在层叠基板2的电路板2b上,通过焊料9将金属块15接合在该半导体芯片上。可以在进行半导体芯片3向电路板2b的接合之后,再进行金属块15向半导体芯片3的接合,也可以同时进行半导体芯片3向电路板2b的接合与金属块15向半导体芯片3的接合。
接下来,对于形成有开口16d的印刷电路基板16,向该开口16d插入金属块15并使其贯穿。由此,如图9所示,形成于开口16d的舌片16e呈现出与金属块15的侧面接触且翘曲的形态。
通过包括上述制造工序,可以在印刷电路基板16相对于金属块15被定位的状态下使两者被固定为一体。因此,能够自动且精度良好地定位控制电极3b的位置和导电柱4B的一端的位置,进而能够以低成本制造可靠性高的功率半导体模块。
另外,作为本实施方式的功率半导体模块12的制造方法的变形例,可以如下改变实施方式1的功率半导体模块1的制造方法中的部件和工序。
即,采用金属块15作为第一导电部件5b。第二配线基板6(16)具备具有正面和背面的第二绝缘基板6a(16a),第二导电部件6b(16b)形成于第二绝缘基板6a(16a)的正面和背面中的至少一方,在第二绝缘基板6a(16a)上设有开口6c(16d),在开口6c(16d)处形成有由挠性材料构成的舌片(16e)。此外,在将导电柱4B的一端与控制电极3b电连接且机械连接的工序中,以与控制电极3b对置的方式配置第二配线基板6(16),且使得舌片(16e)与金属块15接触并翘曲。
为了比较,在图12中示出现有的半导体装置101的截面图,将其由XIII表示的部分的局部放大图示于图13B。图12、图13A、图13B中示出的半导体装置101具备印刷电路基板105作为配线部件。印刷电路基板105具备绝缘基板105a和铜箔105b,对于该铜箔105b来说,与半导体芯片3的主电极3a对置的部分和与控制电极3b对置的部分具有相同的厚度。因此,如果大电流从主电极3a流过印刷电路基板105,则可能导致铜箔105b发热。在增加铜箔105b的厚度的情况下,铜箔105b的发热得到了抑制,但另一方面,难以利用蚀刻方式形成用来构成与控制电极3b电连接的电路的部分。另外,即使能够进行蚀刻,由于大电流不流过控制电极3b,所以会导致厚度多余而产生的浪费。与此相对,由上述实施方式1和实施方式2可以明确,与现有的半导体装置相比,本发明的半导体装置具有优异的效果。
以上,使用附图和实施方式具体说明了本发明的半导体装置及其制造方法,但本发明的半导体装置不受实施方式和附图的记载限定,在不脱离本发明的主旨的范围内可以进行各种变形。

Claims (18)

1.一种半导体装置,其特征在于,具备:
层叠基板,其具备绝缘板和电路板;
半导体芯片,其具备正面和背面,且在所述正面具有主电极和控制电极,所述背面固定于所述电路板;
第一配线基板,其包含第一导电部件,且以与所述主电极对置的方式配置,所述主电极与所述第一导电部件电连接;
第二配线基板,其包含第二导电部件,且以与所述控制电极对置的方式配置,且具有开口;以及
导电柱,其具备一端和另一端,所述一端与所述控制电极电连接且机械连接,所述另一端与所述第二导电部件电连接且机械连接,
所述第一导电部件的厚度比所述第二导电部件的厚度更厚,
所述第一配线基板配置于所述开口的内侧。
2.根据权利要求1所述的半导体装置,其特征在于,所述第一配线基板和所述第二配线基板配置于同一面内。
3.根据权利要求1所述的半导体装置,其特征在于,所述第一配线基板与所述开口的内侧接触。
4.根据权利要求1所述的半导体装置,其特征在于,所述第一配线基板与所述第二配线基板被固定为一体。
5.根据权利要求1所述的半导体装置,其特征在于,所述第一配线基板具备具有正面和背面的第一绝缘基板,所述第一导电部件形成于所述第一绝缘基板的正面和背面中的至少一方,
所述第二配线基板具备具有正面和背面的第二绝缘基板,所述第二导电部件形成于所述第二绝缘基板的正面和背面中的至少一方,
在所述第二绝缘基板上设有所述开口。
6.根据权利要求5所述的半导体装置,其特征在于,所述第一绝缘基板的侧面与所述开口的内侧侧面对置。
7.根据权利要求1或4所述的半导体装置,其特征在于,所述第一导电部件由金属块构成。
8.根据权利要求7所述的半导体装置,其特征在于,所述第二配线基板具备具有正面和背面的第二绝缘基板,所述第二导电部件形成于所述第二绝缘基板的正面和背面中的至少一方,
在所述第二绝缘基板上设有所述开口。
9.权利要求8所述的半导体装置,其特征在于,所述金属块贯穿所述开口,使得所述导电柱的一端与所述控制电极定位于相互对置的位置。
10.根据权利要求9所述的半导体装置,其特征在于,在所述开口处形成有由挠性材料构成的舌片,所述舌片与所述金属块接触且翘曲。
11.根据权利要求10所述的半导体装置,其特征在于,在所述开口处形成有多个所述舌片,在所述第二绝缘基板与所述金属块之间具有被所述舌片限定的间隙。
12.根据权利要求11所述的半导体装置,其特征在于,所述第二绝缘基板的构成材料包含所述挠性材料。
13.根据权利要求1或4所述的半导体装置,其特征在于,在所述第二配线基板上连接有外部端子。
14.根据权利要求7所述的半导体装置,其特征在于,所述金属块在与所述半导体芯片对置的面具备销,所述销与所述主电极电连接且机械连接。
15.一种半导体装置的制造方法,其特征在于,包括:
准备如下部件的工序:
层叠基板,其具备绝缘板和电路板,
半导体芯片,其具备正面和背面,且在所述正面具有主电极和控制电极;
第一配线基板,其包含第一导电部件,
第二配线基板,其包含比所述第一导电部件薄的第二导电部件,且具有开口,以及
导电柱,其具备一端和另一端,所述另一端与所述第二导电部件电连接且机械连接;
将所述半导体芯片的背面固定到所述电路板上的工序;
以与所述主电极对置的方式配置所述第一配线基板,并将所述第一导电部件与所述主电极电连接的工序;以及
以与所述控制电极对置的方式配置所述第二配线基板,使得所述第一配线基板位于所述开口的内侧,并将所述导电柱的所述一端与所述控制电极电连接且机械连接的工序。
16.根据权利要求15所述的半导体装置的制造方法,其特征在于,所述第一配线基板具备具有正面和背面的第一绝缘基板,所述第一导电部件形成于所述第一绝缘基板的正面和背面中的至少一方,
所述第二配线基板具备具有正面和背面的第二绝缘基板,所述第二导电部件形成于所述第二绝缘基板的正面和背面中的至少一方,
在所述第二绝缘基板上设有所述开口。
17.根据权利要求15所述的半导体装置的制造方法,其特征在于,所述第一导电部件由金属块构成,
所述第二配线基板具备具有正面和背面的第二绝缘基板,所述第二导电部件形成于所述第二绝缘基板的正面和背面的至少一方,在所述第二绝缘基板上形成所述开口,在所述开口上形成由挠性材料构成的舌片,
在将所述导电柱的所述一端与所述控制电极电连接且机械连接的工序中,为使所述舌片与所述金属块接触且翘曲,而将所述第二配线基板与所述控制电极对置地配置。
18.一种半导体装置的制造方法,其特征在于,包括如下工序:在将金属块与半导体芯片的位于其正面的主电极电连接且机械连接之后,使所述金属块贯穿开口处形成有由挠性材料构成的舌片的、印刷电路基板的所述开口,以使所述舌片与所述金属块接触并翘曲。
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JP6809294B2 (ja) * 2017-03-02 2021-01-06 三菱電機株式会社 パワーモジュール
DE102017109264B3 (de) * 2017-04-28 2018-08-23 Infineon Technologies Ag Leistungshalbleiterbauelemente und ein Verfahren zum Bilden eines Leistungshalbleiterbauelements
CN111656519A (zh) * 2018-01-25 2020-09-11 三菱电机株式会社 电路装置以及电力变换装置
US11417591B2 (en) 2018-03-08 2022-08-16 Sumitomo Electric Industries, Ltd. Semiconductor module
JP7279324B2 (ja) * 2018-09-14 2023-05-23 富士電機株式会社 半導体モジュール
JP7310161B2 (ja) * 2019-02-13 2023-07-19 富士電機株式会社 半導体装置及びその製造方法
JP7101882B2 (ja) 2019-05-22 2022-07-15 三菱電機株式会社 半導体装置、電力変換装置および半導体装置の製造方法
JP6741135B1 (ja) * 2019-10-02 2020-08-19 富士電機株式会社 半導体モジュール及び半導体モジュールの製造方法
DE102019219238A1 (de) * 2019-12-10 2021-06-10 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Mehrlagiges 3D-Folienpackage
JP7562965B2 (ja) 2020-03-10 2024-10-08 富士電機株式会社 製造方法、製造装置、治具アセンブリ、半導体モジュールおよび車両
KR20210129483A (ko) * 2020-04-20 2021-10-28 현대자동차주식회사 솔더링 구조, 이를 갖는 파워 모듈 및 파워 모듈의 제조 방법
JP7512706B2 (ja) 2020-06-25 2024-07-09 富士電機株式会社 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008098585A (ja) * 2006-10-16 2008-04-24 Fuji Electric Device Technology Co Ltd 半導体装置及び半導体装置の製造方法
CN101552288A (zh) * 2008-04-01 2009-10-07 冲电气工业株式会社 半导体装置及其制造方法
CN102460693A (zh) * 2009-06-19 2012-05-16 株式会社安川电机 电力变换装置
WO2015045648A1 (ja) * 2013-09-30 2015-04-02 富士電機株式会社 半導体装置、半導体装置の組み立て方法、半導体装置用部品及び単位モジュール

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059860A (ja) * 2004-11-30 2007-03-08 Toshiba Corp 半導体パッケージ及び半導体モジュール
JP5272191B2 (ja) * 2007-08-31 2013-08-28 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP5479703B2 (ja) * 2008-10-07 2014-04-23 株式会社東芝 半導体装置及びその製造方法
JPWO2010119897A1 (ja) * 2009-04-17 2012-10-22 Hoya株式会社 骨補填材用のリン酸カルシウム系セメント組成物及びそのキット
JP5500936B2 (ja) * 2009-10-06 2014-05-21 イビデン株式会社 回路基板及び半導体モジュール
WO2011083737A1 (ja) * 2010-01-05 2011-07-14 富士電機システムズ株式会社 半導体装置用ユニットおよび半導体装置
JP5644440B2 (ja) 2010-12-03 2014-12-24 富士電機株式会社 パワー半導体モジュール
JP5962365B2 (ja) * 2012-09-13 2016-08-03 富士電機株式会社 パワー半導体モジュール
JP6004001B2 (ja) * 2012-10-29 2016-10-05 富士電機株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008098585A (ja) * 2006-10-16 2008-04-24 Fuji Electric Device Technology Co Ltd 半導体装置及び半導体装置の製造方法
CN101552288A (zh) * 2008-04-01 2009-10-07 冲电气工业株式会社 半导体装置及其制造方法
CN102460693A (zh) * 2009-06-19 2012-05-16 株式会社安川电机 电力变换装置
WO2015045648A1 (ja) * 2013-09-30 2015-04-02 富士電機株式会社 半導体装置、半導体装置の組み立て方法、半導体装置用部品及び単位モジュール

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117878072A (zh) * 2024-03-13 2024-04-12 烟台台芯电子科技有限公司 一种双面散热结构的igbt器件

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