JP6634778B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6634778B2 JP6634778B2 JP2015218622A JP2015218622A JP6634778B2 JP 6634778 B2 JP6634778 B2 JP 6634778B2 JP 2015218622 A JP2015218622 A JP 2015218622A JP 2015218622 A JP2015218622 A JP 2015218622A JP 6634778 B2 JP6634778 B2 JP 6634778B2
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- conductive member
- wiring board
- opening
- front surface
- insulating substrate
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- 239000004065 semiconductor Substances 0.000 title claims description 155
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims description 101
- 229910052751 metal Inorganic materials 0.000 claims description 73
- 239000002184 metal Substances 0.000 claims description 73
- 239000000463 material Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 10
- 210000002105 tongue Anatomy 0.000 claims 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 56
- 239000011889 copper foil Substances 0.000 description 52
- 229920005989 resin Polymers 0.000 description 26
- 239000011347 resin Substances 0.000 description 26
- 229910000679 solder Inorganic materials 0.000 description 22
- 238000007789 sealing Methods 0.000 description 16
- 239000004020 conductor Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000020169 heat generation Effects 0.000 description 5
- 230000000149 penetrating effect Effects 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000003507 refrigerant Substances 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 238000005452 bending Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000005304 joining Methods 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000002826 coolant Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- PEEHTFAAVSWFBL-UHFFFAOYSA-N Maleimide Chemical compound O=C1NC(=O)C=C1 PEEHTFAAVSWFBL-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910020935 Sn-Sb Inorganic materials 0.000 description 1
- 229910020932 Sn-Sb-Ag Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- 229910008757 Sn—Sb Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/49838—Geometry or layout
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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Description
おもて面及び裏面を備え、前記おもて面に主電極及び制御電極を有し、前記裏面が前記回路板に固定された半導体チップと、
第1の導電部材を含み、前記主電極に対向して配置され、前記主電極が前記第1の導電部材に電気的に接続された第1の配線基板と、
第2の導電部材を含み、前記制御電極に対向して配置され、開口を有する第2の配線基板と、
一端及び他端を備え、前記一端が前記制御電極に電気的かつ機械的に接続され、前記他端が前記第2の導電部材に電気的かつ機械的に接続された導電ポストと、
を備え、
前記第1の導電部材は前記第2の導電部材よりも厚く、
前記第1の配線基板が前記開口の内側に配置されていて、かつ、
前記第1の配線基板は、おもて面及び裏面を有する第1の絶縁基板を備え、前記第1の導電部材は前記第1の絶縁基板のおもて面及び裏面の少なくともいずれか一方に形成され、
前記第2の配線基板は、おもて面及び裏面を有する第2の絶縁基板を備え、前記第2の導電部材は前記第2の絶縁基板のおもて面及び裏面の少なくともいずれか一方に形成され、
前記第2の絶縁基板に前記開口が設けられている
ことを特徴とする。
以下、本発明の半導体装置の実施形態1について、図面を参照しつつ具体的に説明する。なお、本出願の記載に用いられている「電気的かつ機械的に接続されている」という用語は、対象物同士が直接接合により接続されている場合に限られず、はんだや金属焼結材などの導電性の接合材を介して対象物同士が接続されている場合も含むものとする。
図1、図2において、本実施形態の半導体装置であるパワー半導体モジュール1は、積層基板2と、半導体チップ3と、導電ポスト4と、第1の配線基板5と、第2の配線基板6とを備えている。また、パワー半導体モジュール1は、更に外部端子7A、7Bと、封止樹脂8とを備えている。
半導体チップ3は、IGBTやパワーMOSFETに限定されず、おもて面に主電極と制御電極を備え、スイッチングの動作が可能な半導体チップの一個又は複数個の組み合わせであればよい。
また、第2の配線基板6の第2の導電部材6bの厚さが、第1の配線基板5の第1の導電部材5bの厚さよりも相対的に薄いことから、数Aの電流を流す第2の導電部材6bを、第1の配線基板5の第1の導電部材5bと同等の厚さにする無駄がなく、また、電気回路を構成するために第2の導電部材6bを、エッチングにより容易に選択的に形成することができる。
なお、第1の導電部材5bの厚さは第1の絶縁基板5a及び第1の導電部材5bの積層方向の厚みである。第2の導電部材6bの厚さは第1の絶縁基板6a及び第2の導電部材6bの積層方向の厚みである。
一般に、導体に電流を流した際の発熱は、次式のジュールの法則に従う。
Q=I2・R・t
ここに、Qは熱量、Iは電流、Rは抵抗、tは通電時間である。
R=ρ・L/S
ここに、Rは抵抗、ρは電気抵抗率、Lは導体の長さ、Sは導体の断面積である。
製品設計においては、通電による発熱を、ある熱量以下に設定する必要があるが、半導体チップ3の主電流の回路の一部を構成する配線基板においては、導電部材の厚さの上限値は配線基板の製造制約で決まり、大電流化が困難な場合が生じ得る。また、導電部材の厚さを厚くできたとしても導電ポストの圧入に必要な力が増加して製造コストが高くなり、また、幅が狭い制御電極用の導電部材をエッチングにより選択的に形成するのが困難となっていた。
次に、実施形態1の半導体装置1の製造方法について、図2Cを用いて説明する。
まず、絶縁板2a及び回路板2bを備える積層基板2と、おもて面及び裏面を備え、おもて面に主電極3a及び制御電極3bを有する半導体チップ3と、第1の導電部材5bを含む第1の配線基板5と、第1の導電部材5bより薄い第2の導電部材6bを含み、開口6cを有する第2の配線基板6と、一端及び他端を備え、他端が第2の導電部材6bに電気的かつ機械的に接続された導電ポスト4Bと、を用意する(S1)。
次に半導体チップ3の裏面を回路板2bに固定し(S2)、第1の配線基板5を主電極3aに対向して配置し、第1の導電部材5bを主電極3aに電気的に接続し(S3)、第1の配線基板5が開口6cの内側に位置するように、第2の配線基板6を制御電極3bに対向して配置し、導電ポスト4Bの一端を制御電極3bに電気的かつ機械的に接続する(S4)。
このような製造方法において、好ましくは、第1の配線基板5は、おもて面及び裏面を有する第1の絶縁基板5aを備え、第1の導電部材5bは第1の絶縁基板5aのおもて面及び裏面の少なくともいずれか一方に形成されているとよい。また、第2の配線基板6は、おもて面及び裏面を有する第2の絶縁基板6aを備え、第2の導電部材6bは第2の絶縁基板6aのおもて面及び裏面の少なくともいずれか一方に形成されているとよい。さらに、第2の絶縁基板6aに開口6cが設けられているとよい。
次に、本発明の半導体装置の実施形態2について、図面を参照しつつ具体的に説明する。
図3に、本実施形態2の半導体装置であるパワー半導体モジュール11の要部を斜視図で示す。図3においては、理解を容易にするために、外部端子7A、外部端子7B及び封止樹脂8の図示を省略し、封止樹脂8により封止される前の要部の態様を図示している。なお、以下の図面において、図1及び図2に示した部材と同一の部材については同一の符号を付している。そのため、以下の説明においては、既に説明した部材については重複する説明を省略する。
2つのRC−IGBTは積層基板2上に配置され、回路板2b、金属ブロック15、リード端子7d、リード端子7e、リード端子7f及びプリント基板16に接続されてインバータ回路の上下アームを構成している。1つの積層基板2上に電気的に並列に接続された2個1組の合計2組の半導体チップ3を配置して、インバータ回路を構成する一相における上アーム及び下アームを構成してもよい。
なお、ピン部15bの各ピンの形状は特に図示した円柱状のものに限られず、角柱状のものであってもよく、フィン状であってもよい。
また、本実施形態の金属ブロック15の変形例としては、ピン部15bがない金属ブロックが挙げられる。換言すれば、ベース部15aのみの、板状の金属ブロックであってもよい。この場合、板状の金属ブロックに、その厚さ方向に貫通する孔を有しているものも、本実施形態の金属ブロック15の変形例である。
第1の銅箔部分16bは、開口16d近傍で第2の銅箔部分16cに干渉しない範囲かつ、舌片16eの変形を妨げない範囲でフレキシブル絶縁板16a上に形成されている。第1の銅箔部分16bにより、プリント基板16の変形が抑制され、また、電磁シールド性が向上する。
また、プリント基板16の第1の銅箔部分16bの厚さが、金属ブロック15のベース部15aの厚さほどには厚くなく、一例では第1の銅箔部分16bの厚さは、0.1〜0.3mm程度である。第1の銅箔部分16bの厚さが0.1mm以上であると、制御用の電流を流すことができれば足りる、必要十分な厚さの第2の銅箔部分16cを形成できる。また、第1の銅箔部分16bの厚さが0.3mm以下であると、電気回路を構成するため第1の銅箔部分16bと同時に形成する第2の銅箔部分16cを、エッチングにより容易に選択的に形成することができる。
また、舌片16eが形成されていることにより、大きさの異なる複数種類の金属ブロック15に対して、舌片16eを反らせて、一つのプリント基板で位置決め、固定することも可能になる。
図11に示すように、積層基板2の回路板2b上ではんだ9により半導体チップ3を接合し、この半導体チップ上ではんだ9により金属ブロック15を接合する。回路板2bに対する半導体チップ3の接合の後に、半導体チップ3に対する金属ブロック15の接合を行ってもよいし、回路板2bに対する半導体チップ3の接合と、半導体チップ3に対する金属ブロック15の接合とを同時に行ってもよい。
かかる製造工程を含むことにより、プリント基板16が金属ブロック15に対して位置決めされた状態で一体的に固定される。よって、制御電極3bの位置と、導電ポスト4Bの一端の位置とを、自動的かつ精度よく位置合わせすることができ、ひいては信頼性が高いパワー半導体モジュールを低コストで製造することができる。
また、本実施形態のパワー半導体モジュール12の製造方法の変形例として、実施形態1の半導体装置1の製造方法を、部材及び工程を次のとおり変更して適用してもよい。
すなわち、第1の導電部材5として金属ブロック15が採用される。第2の配線基板6(16)は、おもて面及び裏面を有する第2の絶縁基板6a(16a)を備え、第2の導電部材6b(16b)は第2の絶縁基板6a(16a)のおもて面及び裏面の少なくともいずれか一方に形成され、第2の絶縁基板6a(16a)に開口6c(16d)が設けられており、開口6c(16d)に可撓性材料よりなる舌片(16e)が形成されている。さらに、導電ポスト4Bの一端を制御電極3bに電気的かつ機械的に接続する工程において、舌片(16e)が金属ブロック15に接しながら反るように、第2の配線基板6(16)を制御電極3bに対向して配置する。
2 積層基板
2a 絶縁板
2b 回路板
2c 金属板
3 半導体チップ
3a 主電極
3b 制御電極
4 導電ポスト
5 第1の配線基板
6 第2の配線基板
15 金属ブロック
16 プリント基板
Claims (14)
- 絶縁板及び回路板を備える積層基板と、
おもて面及び裏面を備え、前記おもて面に主電極及び制御電極を有し、前記裏面が前記回路板に固定された半導体チップと、
第1の導電部材を含み、前記主電極に対向して配置され、前記主電極が前記第1の導電部材に電気的に接続された第1の配線基板と、
第2の導電部材を含み、前記制御電極に対向して配置され、開口を有する第2の配線基板と、
一端及び他端を備え、前記一端が前記制御電極に電気的かつ機械的に接続され、前記他端が前記第2の導電部材に電気的かつ機械的に接続された導電ポストと、
を備え、
前記第1の導電部材は前記第2の導電部材よりも厚く、
前記第1の配線基板が前記開口の内側に配置されていて、かつ、
前記第1の配線基板は、おもて面及び裏面を有する第1の絶縁基板を備え、前記第1の導電部材は前記第1の絶縁基板のおもて面及び裏面の少なくともいずれか一方に形成され、
前記第2の配線基板は、おもて面及び裏面を有する第2の絶縁基板を備え、前記第2の導電部材は前記第2の絶縁基板のおもて面及び裏面の少なくともいずれか一方に形成され、
前記第2の絶縁基板に前記開口が設けられている
ことを特徴とする半導体装置。 - 前記第1の配線基板及び前記第2の配線基板が同一面内に配置されている請求項1記載の半導体装置。
- 前記第1の配線基板が前記開口の内側に接している請求項1記載の半導体装置。
- 前記第1の配線基板と前記第2の配線基板とが一体的に固定された請求項1記載の半導体装置。
- 前記第1の絶縁基板の側面が前記開口の内側側面に対向している請求項1記載の半導体装置。
- 絶縁板及び回路板を備える積層基板と、
おもて面及び裏面を備え、前記おもて面に主電極及び制御電極を有し、前記裏面が前記回路板に固定された半導体チップと、
第1の導電部材を含み、前記主電極に対向して配置され、前記主電極が前記第1の導電部材に電気的に接続された第1の配線基板と、
第2の導電部材を含み、前記制御電極に対向して配置され、開口を有する第2の配線基板と、
一端及び他端を備え、前記一端が前記制御電極に電気的かつ機械的に接続され、前記他端が前記第2の導電部材に電気的かつ機械的に接続された導電ポストと、
を備え、
前記第1の導電部材は前記第2の導電部材よりも厚く、
前記第1の配線基板が前記開口の内側に配置されていて、かつ、
前記第1の導電部材が、金属ブロックよりなり、
前記第2の配線基板は、おもて面及び裏面を有する第2の絶縁基板を備え、前記第2の導電部材は前記第2の絶縁基板のおもて面及び裏面の少なくともいずれか一方に形成され、
前記第2の絶縁基板に前記開口が設けられていて、
前記金属ブロックが前記開口を貫通しており前記導電ポストの一端と前記制御電極とが互いに対向する位置に位置合わせされていて、
前記開口に可撓性材料よりなる舌片が形成されており、前記舌片が前記金属ブロックに接しながら反っている
ことを特徴とする半導体装置。 - 前記第1の配線基板と前記第2の配線基板とが一体的に固定された請求項6記載の半導体装置。
- 前記開口に前記舌片が複数形成されており、前記第2の絶縁基板と前記金属ブロックとの間に前記舌片により規定される隙間を有する請求項6記載の半導体装置。
- 前記第2の絶縁基板が前記可撓性材料を含む請求項8記載の半導体装置。
- 前記第2の配線基板に外部端子が接続された請求項1、4、6又は7記載の半導体装置。
- 前記金属ブロックが、前記半導体チップと対向する面にピンを備え、前記ピンが前記主電極に電気的かつ機械的に接続されている請求項6記載の半導体装置。
- 絶縁板及び回路板を備える積層基板と、
おもて面及び裏面を備え、前記おもて面に主電極及び制御電極を有する半導体チップと、
第1の導電部材を含み、おもて面及び裏面を有する第1の絶縁基板を備え、前記第1の導電部材は前記第1の絶縁基板のおもて面及び裏面の少なくともいずれか一方に形成される第1の配線基板と、
前記第1の導電部材より薄い第2の導電部材を含み、開口を有し、おもて面及び裏面を有する第2の絶縁基板を備え、前記第2の導電部材は前記第2の絶縁基板のおもて面及び裏面の少なくともいずれか一方に形成され、前記第2の絶縁基板に前記開口が設けられている第2の配線基板と、
一端及び他端を備え、前記他端が前記第2の導電部材に電気的かつ機械的に接続された導電ポストと、
を用意する工程と、
前記半導体チップの裏面を前記回路板に固定する工程と、
前記第1の配線基板を前記主電極に対向して配置し、前記第1の導電部材を前記主電極に電気的に接続する工程と、
前記第1の配線基板が前記開口の内側に位置するように、前記第2の配線基板を前記制御電極に対向して配置し、前記導電ポストの前記一端を前記制御電極に電気的かつ機械的に接続する工程と、
を備える半導体装置の製造方法。 - 絶縁板及び回路板を備える積層基板と、
おもて面及び裏面を備え、前記おもて面に主電極及び制御電極を有する半導体チップと、
第1の導電部材を含み、前記第1の導電部材が、金属ブロックよりなる第1の配線基板と、
前記第1の導電部材より薄い第2の導電部材を含み、開口を有し、おもて面及び裏面を有する第2の絶縁基板を備え、前記第2の導電部材は前記第2の絶縁基板のおもて面及び裏面の少なくともいずれか一方に形成され、前記第2の絶縁基板に前記開口が設けられており、前記開口に可撓性材料よりなる舌片が形成されている第2の配線基板と、
一端及び他端を備え、前記他端が前記第2の導電部材に電気的かつ機械的に接続された導電ポストと、
を用意する工程と、
前記半導体チップの裏面を前記回路板に固定する工程と、
前記第1の配線基板を前記主電極に対向して配置し、前記第1の導電部材を前記主電極に電気的に接続する工程と、
前記第1の配線基板が前記開口の内側に位置するように、前記第2の配線基板を前記制御電極に対向して配置し、前記導電ポストの前記一端を前記制御電極に電気的かつ機械的に接続する工程と、
を備え、
前記導電ポストの前記一端を前記制御電極に電気的かつ機械的に接続する工程において、前記舌片が前記金属ブロックに接しながら反るように、前記第2の配線基板を前記制御電極に対向して配置する半導体装置の製造方法。 - 金属ブロックを半導体チップのおもて面の主電極と電気的かつ機械的に接続した後、可撓性材料よりなる舌片が開口に形成されたプリント基板の前記開口に前記金属ブロックを貫通させて前記舌片を前記金属ブロックに接触させて反らす工程を含むことを特徴とする半導体装置の製造方法。
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