CN105981168B - 功率半导体模块 - Google Patents

功率半导体模块 Download PDF

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Publication number
CN105981168B
CN105981168B CN201580008212.7A CN201580008212A CN105981168B CN 105981168 B CN105981168 B CN 105981168B CN 201580008212 A CN201580008212 A CN 201580008212A CN 105981168 B CN105981168 B CN 105981168B
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power semiconductor
bus unit
circuit board
terminal
units
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CN105981168A (zh
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崛元人
高桥良和
望月英司
西村芳孝
池田良成
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

功率半导体模块具备冷却器、在冷却器上并列固定的多个功率半导体单元、以及将功率半导体单元电连接的母线单元。功率半导体单元具备依次层叠了电路板、绝缘板以及金属板而成的层叠基板；固定于电路板的半导体元件；具有印刷电路基板和多个导电柱的布线部件；与电路板电连接且机械连接的外部端子；以及绝缘性的密封材料。母线单元具备将各功率半导体单元的外部端子相互连接的多个母线。

Description

功率半导体模块
技术领域
本发明涉及适用于车载用和/或工业用等的功率半导体模块。
背景技术
以往的功率半导体模块具有开关元件为一个的一合一、开关元件为两个的二合一、开关元件为六个的六合一等，分别具有不同的外形。另外，对于功率半导体模块，顾客所要求的额定的电流和/或电压也是多种多样的。因此，基于额定的电流和/或电压单独地设计并制造产品。
图12中以剖视图示出了以往的功率半导体模块的一个例子。功率半导体模块101在冷却器110的翅片底座111上具备层叠基板121。层叠基板121具备在绝缘板121a的正面固定有电路板121b，在绝缘板121a的背面固定有金属板121c的层叠结构。层叠基板121通过接合材料122、例如焊料固定于翅片底座111。半导体芯片123通过导电性的接合材料124、例如焊料而接合在电路板121b上。
在层叠基板121的周围设置有壳体125，收纳层叠基板121和半导体芯片123。在壳体125的上端设置有盖125a。一端在壳体125的内侧露出、另一端从壳体125的上端突出的外部端子126一体地安装于壳体125。半导体芯片123彼此，以及半导体芯片123和外部端子126之间通过键合线127电连接。为了对层叠基板121、半导体芯片123以及键合线127进行绝缘，壳体125内例如通过由绝缘性树脂构成的密封材料128密封。作为壳体125的安装单元，在设置于壳体125的端部的贯通孔安装金属环129。并且，以穿通金属环129的方式设置有螺钉130，该螺钉130与翅片底座111螺纹结合。另外，壳体125的底面和翅片底座111之间通过粘接剂131而固定。
冷却器110具备翅片底座111、安装于翅片底座111的翅片112、收纳翅片112且在翅片底座111的周边进行密闭的壳体113。在壳体113内形成有流路，通过在该流路中流通冷却液，对从半导体芯片123产生且通过层叠基板121而传导到翅片112的热进行冷却。
以往的功率半导体模块由于例如根据半导体芯片的既定个数、额定电流、额定电压单独地设计并制造产品，所以耗时耗力。并且，功率半导体模块在车载用等的用途中，要求薄型化、小型化。
关于功率半导体模块的小型化，提出了具备叠层母线(Laminated Busbar)，在该叠层母线的两面分别安装半导体模块和冷却器的方法(专利文献1)。然而，专利文献1中记载的功率半导体模块，为了在各半导体模块中使用键合线而使制造过程耗时耗力。另外，由于在两面分别具备半导体模块和冷却器，所以包含了冷却器的外形的薄型化不充分。
现有技术文献
专利文献
专利文献1：日本特开2007-273884号公报
发明内容
技术问题
本发明有利地解决了上述的问题，目的在于提供能够减少基于既定的电路构成、额定电流、额定电压的多种功率半导体模块的制造过程的工夫和/或时间，迅速且低成本地进行制造，并且能够薄型化的功率半导体模块。
技术方案
本发明的功率半导体模块具备冷却器、在该冷却器上并列固定的多个功率半导体单元、以及将该功率半导体单元电连接的母线单元。并且，该功率半导体单元具备：层叠基板，依次层叠电路板、绝缘板以及金属板而成；半导体元件，在正面具有电极，背面固定于该电路板；布线部件，具有印刷电路基板和多个导电柱，该印刷电路基板与该半导体元件的正面和该电路板对置，该导电柱的一端与该印刷电路基板连接，该导电柱的另一端与该半导体元件的该电极或者该电路板电连接且机械连接；外部端子，与该电路板电连接且机械连接；以及绝缘性的密封材料，将该层叠基板、半导体元件、布线部件以及外部端子密封。另外，该母线单元具备将各该功率半导体单元的该外部端子相互连接的多个母线。
发明效果
根据本发明的功率半导体模块，能够减少多种功率半导体模块的制造过程的工夫和/或时间，迅速且低成本地进行制造，并且能够进一步薄型化。
附图说明
图1是表示本发明的一个实施方式的功率半导体模块的立体图。
图2是图1的功率半导体模块的分解立体图。
图3是功率半导体单元的剖视图。
图4是功率半导体单元、冷却器以及母线单元的剖视图。
图5是母线单元的立体图。
图6是从下侧向上观察母线单元的立体图。
图7是从下侧向上观察功率半导体单元和母线单元的立体图。
图8是母线单元的例子的立体图。
图9是功率半导体模块的另一实施方式的立体图。
图10是功率半导体模块的另一实施方式的立体图。
图11是功率半导体模块的另一实施方式的立体图。
图12是以往的功率半导体模块的一个例子的剖视图。
符号说明
1、2、3、4：功率半导体模块
10：冷却器
20：功率半导体单元
20a：突起
20b：槽
21：层叠基板
21a：绝缘板
21b：电路板
21c：金属板
22：半导体芯片
23：布线部件
23a：印刷电路基板
23b：导电柱
24：外部端子
25：密封材料
30、31、32、33、34、35：母线单元
30a：端子连接部
30b：连结部
30c：端子基部
35a：电流传感器
40：控制基板
具体实施方式
以下，参照附图对本发明的功率半导体模块的实施方式具体进行说明。应予说明，本申请中使用的“电连接且机械连接”的用语不限于对象物彼此通过直接接合而连接的情况，还包括经由焊料和/或金属烧结件等导电性的接合材料而将对象物彼此连接的情况。
(实施方式1)
图1是本发明的一个实施方式的功率半导体模块的立体图，图2是图1的功率半导体模块的分解立体图。本发明的实施方式1的功率半导体模块1具备冷却器10、多个功率半导体单元20以及母线单元30。并且，多个功率半导体单元20以在冷却器10上并列的方式设置，母线单元30将各功率半导体单元20电连接。
冷却器10具备冷却液的入口14和出口15，连接到未图示的冷却系统而使冷却液从入口14导入到冷却器10内，并从出口15排出。冷却器10的内部结构如后所述。
图3中示出功率半导体单元20的剖视图。功率半导体单元20是称为所谓二合一的单元，具有将开关元件和回流二极管反向并联而构成上臂和下臂的电路。功率半导体单元20具备层叠基板21、半导体芯片22、布线部件23、外部端子24、密封材料25。
层叠基板21由绝缘板21a、设置于绝缘板21a的正面的电路板21b、和设置于绝缘板21a的背面的金属板21c构成。即，电路板21b、绝缘板21a以及金属板21c依次层叠而成。绝缘板21a例如由氮化铝、氮化硅和/或氧化铝等绝缘性陶瓷构成，电路板21b、金属板21c例如由铜等金属构成。另外，电路板21b形成为预定的电路图案。层叠基板21例如可使用DCB(Direct Copper Bonding：直接铜键合)基板和/或AMB(Active MetalBlazing：活性金属钎)基板等。
半导体芯片22在正面具有未图示的电极，背面通过未图示的接合材料、例如焊料固定于电路板21b。在本实施例中，半导体芯片22是在正面和背面均配置有电极的纵向型的半导体芯片，背面的电极与电路板21b电连接且机械连接。另外，半导体芯片22不限于纵向型，也可以是在半导体芯片22的正面配置有多种电极的横向型的半导体芯片。
半导体芯片例如为功率MOSFET、二极管和/或IGBT(绝缘栅双极型晶体管)。半导体芯片可以是硅半导体，也可以是碳化硅(SiC)半导体。在半导体芯片22为IGBT的情况下，背面的电极为集电极，正面的电极为发射极和栅极。在半导体芯片22为功率MOSFET的情况下，背面的电极为漏极，正面的电极为源极和栅极。由SiC构成的半导体芯片(例如SiC-MOSFET)与由硅构成的半导体芯片相比耐压高，且能够进行高频率的开关。由此，最合适作为本实施方式的功率半导体模块的半导体芯片22。然而，半导体芯片22不限于IGBT和/或功率MOSFET，只要是能够进行开关动作的一个半导体元件或者多个半导体元件的组合即可。
布线部件23具有印刷电路基板23a和多个导电柱23b。印刷电路基板23a具有金属层和绝缘层，且以与半导体芯片22的正面电极和层叠基板21的电路板21b对置的方式设置。导电柱23b的一端通过软钎焊或硬钎焊与半导体芯片22的正面电极或者层叠基板21的电路板21b电连接且机械连接。并且，导电柱23b的另一端通过软钎焊、硬钎焊或者铆接与印刷电路基板23a的金属层电连接且机械连接。
通过布线部件23，例如半导体芯片22的正面电极和电路板21b电连接。在本实施方式中，布线部件23不是键合线，而是由印刷电路基板23a和导电柱23b构成。由此，能够制成对因半导体芯片22的重复发热而导致的热循环可靠性高的功率半导体单元。另外，通过使布线部件23由印刷电路基板23a和导电柱23b构成，从而与使用了键合线的情况相比，功率半导体单元20能够更加薄型化。另外，导电柱23b与键合线相比，即使正面的电极的面积小也能够可靠地进行连接。并且，由于导电柱与导线相比，施加到半导体芯片22的应力小，所以可靠性高，能够使接合材料的厚度变薄，因而对导电、导热有利。
在半导体芯片22为开关元件的情况下，印刷电路基板23a优选是与配置于其正面的栅极和源极对应地具有多层的金属层的构成。印刷电路基板23a的金属层和/或导电柱23b由导电性好的金属、例如由铜构成。另外，印刷电路基板23a和/或导电柱23b可以根据需要对表面实施电镀。印刷电路基板23a可以是绝缘层由玻璃环氧树脂材料等构成的刚性基板，另外，可以为绝缘层由聚酰亚胺材等构成的可挠性软性基板，进而还可以为绝缘层由陶瓷构成的基板。导电柱23b的外形可以为圆柱形、矩形等形状，但没有特别限制。导电柱23b的底面是比半导体芯片22的正面的电极小的大小。另外，导电柱23b的针对一个半导体芯片22的设置个数为任意数，还可以在一个正面电极接合多个导电柱23b。
在组装功率半导体单元20时，印刷电路基板23a和导电柱23b可以预先一体化而制成布线部件23。通过使用布线部件23，从而能够使功率半导体单元20的制造工序与使用键合线相比更加简单化。
外部端子24的一端与层叠基板21的电路板21b电连接且机械连接。对于外部端子24，当是由铜板等构成的导线时可流通大电流，所以优选。电路板21b与外部端子24的连接可使用焊料等接合材料(未图示)和/或超声波接合等。
外部端子24的另一端以成为与功率半导体单元20的底面平行的方式被折弯。在图3中所示的例中，作为外部端子24，设置有P端子24A、N端子24B以及U端子(或者V端子、W端子)24C。
利用由绝缘性的热固化性树脂构成的密封材料25，将作为功率半导体单元20的各部件的层叠基板21、半导体芯片22、布线部件23、以及外部端子24密封。应予说明，层叠基板21的金属板21c的底面和外部端子24的另一端从密封材料25向外部露出。由热固化性树脂构成的密封材料由于耐热性、耐压性比由凝胶构成的密封材料高，所以优选用于密封材料25。密封材料25具体而言可以使用环氧树脂。并且，为了提高散热性，还优选在树脂中添加导热性好的材料的填料而成的密封材料。填料例如可应用氧化铝和/或氮化硼等。
通过密封材料25的模塑成型，形成功率半导体单元20的外形。在本实施方式中，由密封材料25构成功率半导体单元20的壳体，不另外具备壳体。模塑成型可以使用传递模塑法，但并不限于传递模塑法。例如也可以通过树脂的灌封而成形。另外，功率半导体单元20还可以是具备另外的壳体的构成。
图4中示出了功率半导体单元20、冷却器10以及母线单元30的剖视图。功率半导体单元20内的金属板21c通过未图示的焊料等接合材料固定于冷却器10的翅片底座11。另外，功率半导体单元20的密封材料25的底面部分通过未图示的粘接剂与冷却器10的翅片底座11固定在一起。应予说明，功率半导体单元20和冷却器10的固定并不限于上述的接合材料和粘接剂。例如，可以在金属板21c与翅片底座11之间涂布导热膏等散热材料，将螺钉插通到另外设置于功率半导体单元的贯通孔，将功率半导体单元与翅片底座11螺纹固定连接。从散热性的观点出发，优选通过接合材料和粘接剂而固定，从制造成本的观点出发，优选通过螺纹连接而固定。
冷却器10具备翅片底座11、一体地安装于翅片底座11的翅片12、以及收纳翅片12且配置于翅片底座11的周边的壳体13。在壳体13内构成流路，且通过在该流路流通冷却液，从而对由半导体芯片22产生并通过层叠基板21传导到翅片12的热进行散热。由于功率半导体模块1具备冷却器10，因此即使功率半导体单元20薄型化也能够充分地冷却半导体芯片22。即，能够使功率半导体单元20薄型化。因此，例如对于配置的空间不充裕的车载用途来说，增加了设置功率半导体模块的位置的自由度。另外，本发明的功率半导体模块1既可以横向设置也可以纵向设置。
作为外部端子24的P端子24A和N端子24B在功率半导体单元20的上侧露出。P端子24A和N端子24B与母线单元30的母线电连接。为了容易地设置母线单元30，在功率半导体单元20的上侧，设置有突起20a和槽20b。
母线单元30是分别与多个功率半导体单元20的P端子24A和N端子24B电连接并构成有共用的P端子和N端子的单元。图5中示出母线单元30的立体图。图5的母线单元30可以将三个二合一的功率半导体单元20相互电连接，构成六合一的功率半导体模块1。
母线单元30内置2个母线。一个母线与各功率半导体单元20的P端子24A连接并延伸至共用的P端子。另一个母线与各功率半导体单元20的N端子24B连接并延伸至共用的N端子。并且，利用绝缘性树脂进行模塑成型而成为图示的外形。通过用树脂覆盖母线进行模塑成型，从而在两个母线之间保持规定的间隔，并且确保彼此之间的绝缘。进而防止母线的腐蚀。
母线单元30一体形成，具有端子连接部30a、连结部30b以及端子基部30c。端子连接部30a与各功率半导体单元20的P端子24A和N端子24B连接。连结部30b连结各端子连接部。在端子基部30c，设置有功率半导体模块1的共用端子。
在端子连接部30a中，母线单元30内的母线与功率半导体单元20的P端子24A或者N端子24B通过螺纹结合、螺栓结合、焊料接合或者激光焊接等方法而固定。并且，母线单元30内的母线与功率半导体单元20的P端子24A或者N端子24B电连接。为了与功率半导体单元20的端子电连接，内置的母线在母线单元30的端子连接部30a的背面露出。另外，在使用螺纹结合、螺栓结合或者激光焊接的情况下，可以在端子连接部30a的正面形成开口，使母线露出。
母线单元30如图5所示，与端子连接部30a的宽度W1相比，连结部30b的宽度W2窄。因此，在相邻的端子连接部30a之间形成有空间。可以将该空间形成为用于配置组装于控制基板(参照图11)的部件，控制基板以层叠在功率半导体模块1上的方式设置。因此，能够降低控制基板层叠在功率半导体模块1上时的高度。因此，即使在功率半导体模块1需要控制基板的情况下，也能够使整个功率半导体模块薄型化。
母线单元30的上表面是平坦的。这是为了在母线单元30上需要控制基板的情况下，尽可能地不与控制基板和/或安装在其上的电子部件发生物理上的干扰。这有助于使安装有控制基板的整个功率半导体模块薄型化。在母线单元30中，连结部30b的厚度T2比端子连接部30a的厚度T1更大。这是由于在端子连接部30a中内置有一个母线，而在连结部30b中重叠地内置有两个母线。在连结部30b中，通过重叠地内置极性不同的两个母线，能够使母线的布线的电感低。
图6中示出了从下侧向上观察母线单元30的立体图。母线单元30的连结部30b向下侧突出。连结部30b与设置于功率半导体单元20的上侧的槽20b嵌合。另外，端子连接部30a与设置于功率半导体单元20的上侧的突起20a嵌合。因此，通过将母线单元30的连结部30b与功率半导体单元20的槽20b配合，另外将端子连接部30a与突起20a配合，从而能够将母线单元30容易地设置于功率半导体单元20。
在母线单元30的端子基部30c，设置有与外部连接的P端子和N端子。在图5、图6中所示的例子中，在一个母线单元30，分别设置有两个端子基部30c。这是为了避免电流集中在一个端子基部30c。通过设置有两个端子基部30c，在端子基部30c的P端子或者N端子流通的电流分流为两支。其中，端子基部30c的个数可以为一个，也可以为三个以上。
图7中示出了从下侧向上观察将功率半导体单元20和母线单元30组合的构成的立体图。如图7所示，母线单元30的端子基部30c优选设置成位于相邻的功率半导体单元20之间。由此，能够将端子基部30c配置在较低的位置，由此能够使功率半导体模块1薄型化。
图8(a)～(c)中示出了两个端子基部30c的间隔不同的母线单元31～33的例子的立体图。图8(a)示出了基准间隔的母线单元31，图8(b)示出了间隔比基准间隔宽的母线单元32，图8(c)示出了间隔比基准间隔窄的母线单元33。如此地，母线单元中的端子基部30c的形状、位置、个数等为任意值。由此，功率半导体模块1的P端子和N端子在仅改变母线单元30的情况下就可以灵活地变更。
本实施方式的功率半导体模块1是将相同形状、相同规格的二合一的三个功率半导体单元20并列配置在冷却器10上，通过在母线单元30电连接而构成的六合一功率半导体模块。因此，与单独设计并制造二合一的功率半导体模块和六合一的功率半导体模块的情况下相比，设计、制造都不耗时也不耗力。因此，能够迅速且低成本地制造多种功率半导体模块。
上述的六合一的功率半导体模块是本发明的例示。作为其他的例子，通过使用将三个功率半导体单元20电并联的母线单元30，能够制造三个并列的二合一的功率半导体模块。这样即使在组合了三个功率半导体单元20和冷却器10的情况下，仅变更母线单元30，就能够制造不同的功率半导体模块。
(实施方式2)
图9中示出了本发明的另一实施方式的功率半导体模块2的立体图。应予说明，在以下的实施方式中，与实施方式1的功率半导体模块1相同的部件标记了相同的符号。因此，在以下的说明中省略对各部件的重复的说明。
功率半导体模块2是在冷却器10上设置六个相同种类的功率半导体单元20，并通过母线单元34电连接这些功率半导体单元20而成的半导体模块。母线单元34是将六个功率半导体单元20电并联的母线单元。使用上述的二合一的功率半导体单元20，将已设置的母线单元变更为具有与功率半导体单元20的个数对应的长度的母线单元34，仅改变冷却器10的长度，构成六个并列的二合一的功率半导体模块。
由图1和图9可以理解，根据本发明的实施方式，通过变更功率半导体单元20的个数和母线单元30的构成，从而能够制造多种功率半导体模块。还可以基于顾客的需求灵活地迅速且低成本地制造功率半导体模块。
(实施方式3)
对功率半导体模块的另一的实施方式进行说明。
在本实施方式中，母线单元30在端子基部30c或者其他位置内置有电容器等电子部件。在制造母线单元30时，电子部件与母线一起被绝缘性树脂覆盖。
通过将电子部件内置于母线单元30，从而能够将以往安装于控制基板的电子部件的一部分或者全部设置于母线单元30。由此能够使功率半导体模块1兼备控制基板所具备的功能的一部分或者全部。
(实施方式4)
图10是功率半导体模块的另一实施方式的立体图。
图10所示的功率半导体模块3的母线单元35具备传感器。更具体而言，在母线单元35的端子基部30c安装有电流传感器35a。即，通过将功率半导体模块3的已设置的母线单元变更为母线单元35，仅利用功率半导体模块3就能够测定电流。这样，通过本实施方式，能够对功率半导体模块赋予新功能。
不限于图10所示的电流传感器35a，可以作为传感器而将例如温度传感器、例如热敏电阻安装于母线单元30。安装温度传感器的位置可以任意，例如可以是与电流传感器35a相同的位置。
(实施方式5)
图11示出了功率半导体模块的另一实施方式的立体图。
在本实施方式的功率半导体模块4的母线单元30上设置有控制基板40。安装于该控制基板40的电子部件如以上所述可以配置于母线单元30的相邻的端子连接部30a之间的空间。因此，对整个功率半导体模块的薄型化来说优选。
控制基板40的种类、用途不限。例如，可以将控制基板40和功率半导体单元20的控制端子(未图示)电连接而使功率半导体模块4为智能功率模块(IPM)。由此，能够进行更为高级的控制。
(实施方式6)
作为功率半导体模块的另一实施方式，还可以是在冷却器10的两面分别固定功率半导体单元20和母线单元30的构成。由于本发明的功率半导体模块为薄型，所以即使在冷却器10的两面分别固定功率半导体单元20和母线单元30，也具有充分薄的外形。
以上，虽然使用附图和实施方式具体说明了本发明的功率半导体模块，但本发明的功率半导体模块并不限于实施方式和附图中的记载，在不脱离本发明的主旨的范围内，能够进行多种变形。

Claims (11)

1.一种功率半导体模块，其特征在于，具备冷却器、在所述冷却器上并列固定的多个功率半导体单元、以及将所述功率半导体单元电连接的母线单元，
所述功率半导体单元具备：
层叠基板，依次层叠电路板、绝缘板以及金属板而成；
半导体元件，在正面具有电极，背面固定于所述电路板；
布线部件，具有印刷电路基板和多个导电柱，所述印刷电路基板与所述半导体元件的正面和所述电路板对置，所述导电柱的一端与所述印刷电路基板连接，所述导电柱的另一端与所述半导体元件的所述电极或者所述电路板电连接且机械连接；
外部端子，与所述电路板电连接且机械连接；以及
绝缘性的密封材料，将所述层叠基板、所述半导体元件、所述布线部件以及所述外部端子密封，
所述母线单元具备将各所述功率半导体单元的所述外部端子相互连接的多个母线，
所述母线单元具备与所述功率半导体单元的所述外部端子连接的端子连接部，将各所述端子连接部连结的连结部，以及设置有共用端子的端子基部，
所述母线单元的上表面是平坦的，所述连结部向下侧突出，
所述功率半导体单元在上侧具有嵌合于所述连结部的槽。
2.根据权利要求1所述的功率半导体模块，其中，
所述连结部的宽度比所述端子连接部的宽度窄。
3.根据权利要求1或2所述的功率半导体模块，其中，
在所述母线单元上，进一步设置有控制基板。
4.根据权利要求2所述的功率半导体模块，其中，
所述母线单元的所述端子基部位于相邻的所述功率半导体单元之间。
5.根据权利要求1所述的功率半导体模块，其中，
所述母线单元具有与所述功率半导体单元的个数对应的长度。
6.根据权利要求1所述的功率半导体模块，其中，
所述母线单元具备传感器。
7.根据权利要求1所述的功率半导体模块，其中，
所述母线单元内置有电子部件。
8.根据权利要求1所述的功率半导体模块，其中，
所述功率半导体单元的所述外部端子由导线构成。
9.根据权利要求1所述的功率半导体模块，其中，
所述功率半导体单元的所述外部端子和所述母线单元通过选自螺纹结合、螺栓结合、焊接以及利用接合材料进行的结合中的一种方法而固定。
10.根据权利要求1所述的功率半导体模块，其中，
所述功率半导体单元的所述金属板和所述冷却器通过接合材料而固定。
11.根据权利要求1所述的功率半导体模块，其中，
所述半导体元件由SiC半导体构成。
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015033724A1 (ja) * 2013-09-05 2015-03-12 富士電機株式会社 電力用半導体モジュール
JP6455364B2 (ja) * 2015-08-28 2019-01-23 三菱電機株式会社 半導体装置、インテリジェントパワーモジュールおよび電力変換装置
JP6436353B2 (ja) * 2015-11-16 2018-12-12 株式会社オートネットワーク技術研究所 回路構成体および電気接続箱
JP2019207897A (ja) * 2016-09-29 2019-12-05 三菱電機株式会社 パワーモジュール、その製造方法および電力変換装置
WO2018096735A1 (ja) * 2016-11-24 2018-05-31 住友電気工業株式会社 半導体モジュール
US11063004B2 (en) * 2016-11-29 2021-07-13 Mitsubishi Electric Corporation Semiconductor device, control device, and method for manufacturing semiconductor device
JP6884624B2 (ja) 2017-04-05 2021-06-09 富士電機株式会社 半導体装置、半導体装置の製造方法及びインターフェースユニット
DE112018000105T5 (de) * 2017-04-27 2019-05-29 Fuji Electric Co., Ltd. Elektronisches bauelement und leistungsumwandlungseinrichtung
JP2019033624A (ja) * 2017-08-09 2019-02-28 株式会社デンソー 電力変換装置
US10292316B2 (en) * 2017-09-08 2019-05-14 Hamilton Sundstrand Corporation Power module with integrated liquid cooling
JP7027751B2 (ja) * 2017-09-15 2022-03-02 富士電機株式会社 半導体モジュール
KR102008278B1 (ko) * 2017-12-07 2019-08-07 현대오트론 주식회사 파워칩 통합 모듈과 이의 제조 방법 및 양면 냉각형 파워 모듈 패키지
US11343942B2 (en) * 2018-05-14 2022-05-24 Mitsubishi Electric Corporation Power conversion device including cooling components
RU184560U1 (ru) * 2018-05-16 2018-10-30 Публичное акционерное общество "Научно-производственное объединение "ЭНЕРГОМОДУЛЬ" Силовой полупроводниковый модуль
US20190357386A1 (en) * 2018-05-16 2019-11-21 GM Global Technology Operations LLC Vascular polymeric assembly
JP7238353B2 (ja) * 2018-11-15 2023-03-14 富士電機株式会社 半導体モジュールおよびそれを用いた半導体装置
US11129310B2 (en) * 2018-11-22 2021-09-21 Fuji Electric Co., Ltd. Semiconductor module, vehicle and manufacturing method
JP7368450B2 (ja) * 2019-03-05 2023-10-24 ローム株式会社 半導体装置および接合方法
JP7215273B2 (ja) * 2019-03-22 2023-01-31 三菱マテリアル株式会社 接合構造体
US11758697B2 (en) * 2019-09-26 2023-09-12 Ohio State Innovation Foundation Low inductance power module with vertical power loop structure and insulated baseplates
JP7209615B2 (ja) * 2019-11-13 2023-01-20 三菱電機株式会社 半導体装置
JP7351209B2 (ja) 2019-12-17 2023-09-27 富士電機株式会社 半導体装置
JP7484156B2 (ja) 2019-12-18 2024-05-16 富士電機株式会社 半導体装置
EP3872854A1 (en) * 2020-02-27 2021-09-01 Littelfuse, Inc. Power module housing with improved protrusion design
KR20210129483A (ko) * 2020-04-20 2021-10-28 현대자동차주식회사 솔더링 구조, 이를 갖는 파워 모듈 및 파워 모듈의 제조 방법
JP7353233B2 (ja) * 2020-05-14 2023-09-29 三菱電機株式会社 半導体装置
JP7422646B2 (ja) * 2020-11-27 2024-01-26 三菱電機株式会社 半導体装置および半導体装置の製造方法
DE102020132689B4 (de) * 2020-12-08 2022-06-30 Semikron Elektronik Gmbh & Co. Kg Leistungselektronisches System mit einer Schalteinrichtung und mit einer Flüssigkeitskühleinrichtung

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101622779A (zh) * 2007-02-22 2010-01-06 丰田自动车株式会社 半导体电力变换装置及其制造方法
JP5241177B2 (ja) * 2007-09-05 2013-07-17 株式会社オクテック 半導体装置及び半導体装置の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4052205B2 (ja) * 2003-08-22 2008-02-27 株式会社デンソー 電力変換装置
JP4680816B2 (ja) 2006-03-31 2011-05-11 三菱電機株式会社 半導体装置
JP5527330B2 (ja) * 2010-01-05 2014-06-18 富士電機株式会社 半導体装置用ユニットおよび半導体装置
JP5537224B2 (ja) * 2010-03-30 2014-07-02 トヨタ自動車株式会社 電流センサ組立体およびその組立方法
CN103098363A (zh) * 2010-09-30 2013-05-08 日立汽车系统株式会社 电力转换装置
JP5644440B2 (ja) * 2010-12-03 2014-12-24 富士電機株式会社 パワー半導体モジュール
EP3573096B1 (en) * 2011-06-27 2022-03-16 Rohm Co., Ltd. Semiconductor module
JP6010942B2 (ja) * 2012-03-15 2016-10-19 富士電機株式会社 半導体装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101622779A (zh) * 2007-02-22 2010-01-06 丰田自动车株式会社 半导体电力变换装置及其制造方法
JP5241177B2 (ja) * 2007-09-05 2013-07-17 株式会社オクテック 半導体装置及び半導体装置の製造方法

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