CN108695177B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN108695177B
CN108695177B CN201810263524.8A CN201810263524A CN108695177B CN 108695177 B CN108695177 B CN 108695177B CN 201810263524 A CN201810263524 A CN 201810263524A CN 108695177 B CN108695177 B CN 108695177B
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jig
semiconductor chip
lead frame
manufacturing
positioning portion
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CN108695177A (zh
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川岛崇功
大野裕孝
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Denso Corp
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Denso Corp
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Abstract

本发明提供一种半导体装置及其制造方法，良好地进行引线框与半导体芯片的定位。是通过使用夹具将半导体芯片连接于引线框来制造半导体装置的方法。所述半导体芯片在一个面上具有主电极。所述引线框具有接合用凸部和在所述接合用凸部的周围配置的由凸形状或凹形状构成的定位部。所述制造方法包括：以在所述接合用凸部与所述夹具之间空出间隔的状态使所述夹具卡合于所述定位部的工序；使所述夹具卡合于所述半导体芯片的工序；及在使所述定位部和所述半导体芯片卡合于所述夹具的状态下，将所述接合用凸部经由焊料连接于所述半导体芯片的所述主电极的工序。

Description

半导体装置及其制造方法
技术领域
本说明书公开的技术涉及半导体装置及其制造方法。
背景技术
专利文献1公开了引线框具有接合用凸部且接合用凸部连接于半导体芯片的主电极连接的半导体装置。通过引线框的接合用凸部，能确保用于设置信号配线的空间。通过向引线框插入定位用的销，来抑制半导体芯片与引线框之间的位置偏离。
【现有技术文献】
【专利文献】
【专利文献1】日本特开2009-146950号公报
发明内容
【发明要解决的问题】
在如专利文献1那样采用具有接合用凸部的引线框的情况下，在主电极上钎焊接合用凸部时，存在产生位置偏离的情况。当相对于半导体芯片的主电极而引线框的接合用凸部的位置偏离时，难以从半导体芯片向引线框传递热量。因此，半导体装置的散热性下降。在专利文献1的方法中，需要用于向引线框插入销的孔，在孔的位置会阻碍散热。因此，在本说明书中，提供一种不阻碍散热而能够进行引线框与半导体芯片的定位的技术。
【用于解决问题的手段】
本说明书公开的半导体装置的制造方法中，使用夹具将半导体芯片连接于引线框。所述半导体芯片在一个面上具有主电极。所述引线框具有接合用凸部和在所述接合用凸部的周围配置的由凸形状或凹形状构成的定位部。所述制造方法包括：以在所述接合用凸部与所述夹具之间空出间隔的状态使所述夹具卡合于所述定位部的工序；使所述夹具卡合于所述半导体芯片的工序；及在所述夹具卡合于所述定位部和所述半导体芯片的状态下，将所述接合用凸部经由焊料连接于所述半导体芯片的所述主电极的工序。
在该制造方法中，由于夹具卡合于引线框的定位部，因此能抑制引线框与夹具的位置偏离。而且，由于夹具卡合于半导体芯片，因此能抑制半导体芯片与夹具的位置偏离。因此，经由夹具将引线框与半导体芯片定位。因此，能抑制引线框与半导体芯片之间的位置偏离。在这样经由夹具定位后的状态下将半导体芯片的主电极经由焊料接合于引线框的接合用凸部。因此，能抑制接合用凸部相对于主电极发生位置偏离，能够防止半导体装置的散热性的下降。而且，在该方法中，定位部由凸形状或凹形状构成，因此定位部不会阻碍散热。因此，根据该制造方法，能够稳定地制造出散热性高的半导体装置。
另外，本说明书提供一种散热性高的半导体装置。该半导体装置具有：在一个面上具有主电极的半导体芯片；和引线框。所述引线框具有接合用凸部和在所述接合用凸部的周围配置的由凸形状或凹形状构成的定位部。所述接合用凸部经由焊料而连接于所述主电极。
该半导体装置能够通过上述的本说明书公开的制造方法而制造。该半导体装置中，由于定位部由凸形状或凹形状构成，因此定位部不会阻碍散热而散热性高。
附图说明
图1是引线框的立体图。
图2是引线框的主端子的放大俯视图。
图3是图1、2的III-III线的剖视图。
图4是图1、2的IV-IV线的剖视图。
图5是安装有夹具的状态的引线框的立体图。
图6是安装有夹具的状态的主端子的与图2对应的放大俯视图。
图7是安装有夹具的状态的引线框的与图3对应的剖视图。
图8是安装有夹具的状态的引线框的与图4对应的剖视图。
图9是定位后的半导体芯片和引线框的与图2对应的放大俯视图。
图10是定位后的半导体芯片和引线框的与图3对应的剖视图。
图11是定位后的半导体芯片和引线框的与图4对应的剖视图。
图12是回流焊后的半导体芯片和引线框的与图3对应的剖视图。
图13是回流焊后的半导体芯片和引线框的与图4对应的剖视图。
图14是连接了集电极端子之后的半成品的与图3对应的剖视图。
图15是形成了绝缘树脂层之后的半成品的与图3对应的剖视图。
图16是形成有绝缘树脂层之后的半成品的俯视图。
图17是通过实施方式的制造方法制造的半导体装置的俯视图。
图18是以往的制造方法的说明图。
图19是以往的制造方法的说明图。
图20是通过以往的制造方法制造的半导体装置的俯视图。
图21是表示位置偏离大时的焊料层的剖视图。
图22是表示变形例的定位用凸部的俯视图。
图23是表示变形例的定位用凸部的剖视图。
图24是表示变形例的定位用凸部的剖视图。
图25是表示变形例的定位用凸部的剖视图。
图26是表示变形例的定位用凸部的俯视图。
图27是表示变形例的定位用凸部的俯视图。
图28是表示变形例的定位用凸部的俯视图。
图29是表示变形例的定位用凸部的俯视图。
图30是表示变形例的定位用凸部的俯视图。
图31是表示变形例的定位用凸部的俯视图。
图32是表示变形例的定位用凸部的俯视图。
图33是表示变形例的定位用凸部的俯视图。
图34是表示变形例的定位用凸部的俯视图。
图35是表示变形例的定位用凹部的剖视图。
【符号说明】
12：引线框
14：裸片焊盘
16：散热板
18：定位用凸部
20：接合用凸部
22：系杆
23：悬吊引线
26：信号端子
28a～28c：主端子
30：夹具
40：半导体芯片
42：半导体基板
44：发射极
46：信号电极
48：集电极
50：焊料层
60：集电极端子
70：绝缘树脂层
具体实施方式
对实施方式的半导体装置的制造方法进行说明。图1～4示出在实施方式的制造方法中使用的引线框12。引线框12是与半导体芯片连接用的多个端子相互连接的部件。引线框12具备2个裸片焊盘14、主端子28a～28c以及多个信号端子26。对于各裸片焊盘14连接1个半导体芯片。主端子28a、28c连接于对应的裸片焊盘14。主端子28b是与后述的集电极端子60连接的端子。需要说明的是，2个裸片焊盘14的构造及使用方法大致相等，因此以下，以一方的裸片焊盘14(图1的右侧的裸片焊盘14)为中心进行说明。
裸片焊盘14具有散热板16、定位用凸部18以及接合用凸部20。需要说明的是，在图2及其以后的放大俯视图中，通过斜线阴影表示定位用凸部18，通过点状阴影表示接合用凸部20。散热板16是厚度比引线框12的其他部分厚的板状的部分。以下，将散热板16的厚度方向称为z方向，将与z方向正交的一方向称为x方向，将与x方向和z方向正交的方向称为y方向。定位用凸部18是从散热板16的上表面向上侧突出的部分。如图2所示，定位用凸部18在沿z方向观察时，具有大致四边形的形状。接合用凸部20是从定位用凸部18的上表面进一步向上侧突出的部分。如图2所示，接合用凸部20在沿z方向观察时具有四边形的形状。如图2、3所示，在接合用凸部20的侧方配置有多个信号端子26。各信号端子26沿x方向较长地延伸，并沿y方向空出间隔地排列。各信号端子26的一方的端部配置在散热板16的上部。在信号端子26与裸片焊盘14之间设有间隔。如图1所示，各信号端子26通过系杆22而相互连接。而且，各信号端子26通过系杆22及悬吊引线23而连接于裸片焊盘14。如图2所示，定位用凸部18未配置在与信号端子26相对的位置。定位用凸部18除了与信号端子26相对的位置之外，以包围接合用凸部20的周围的方式配置。
在本实施方式的制造方法中，首先，实施夹具安装工序。在夹具安装工序中，如图5～8所示，向引线框12安装夹具30。夹具30具有截面为四边形的筒形状。如图6所示，以夹具30的内周面30a紧贴于定位用凸部18的外周面18a的方式将夹具30卡合于定位用凸部18。由此，将夹具30准确地定位于引线框12。需要说明的是，如图5、7所示，在夹具30的下表面的一部分设有切口部30b。在将夹具30安装于引线框12时，切口部30b配置在与多个信号端子26对应的位置。由于设有切口部30b，因此夹具30与各信号端子26不接触。如图6所示，在夹具30与接合用凸部20之间设有间隔。如图7、8所示，夹具30的高度比接合用凸部20的高度高。
接下来，实施半导体芯片配置工序。在半导体芯片配置工序中，如图9～11所示，在夹具30的内部配置半导体芯片40。即，使夹具30与半导体芯片40卡合。首先，说明半导体芯片40。如图10、11所示，半导体芯片40具有半导体基板42、发射极44、信号电极46以及集电极48。在半导体基板42的内部形成有IGBT(Insulated Gate Bipolar Transistor)。发射极44和信号电极46设置于半导体基板42的第一表面(在图10、11中为下侧的面)。需要说明的是，在图10中图示出单一的信号电极46，但是半导体芯片40具有与信号端子26对应的个数(例如，5个)信号电极46。信号电极46配置在与发射极44相邻的位置。发射极44远大于各信号电极46。信号电极46是IGBT的栅电极、温度检测用的电极、电流检测用的电极、电压检测用的电极等。向信号电极46施加以发射极44的电位为基准电位的信号。因此，信号电极46与发射极44之间的电位差小。集电极48覆盖半导体基板42的第二表面(第一表面的相反侧的表面，在图10、11中为上侧的面)的整体。
在半导体芯片配置工序中，以发射极44朝向下侧的朝向，将半导体芯片40从上侧插入于夹具30。由此，将半导体芯片40配置在夹具30的内部。在此，如图10所示，以发射极44配置在接合用凸部20上且各信号电极46配置在对应的信号端子26的端部上的方式，安设半导体芯片40。此时，在发射极44与接合用凸部20之间、及各信号电极46与对应的信号端子26之间介有焊料层50。如图9所示，在沿z方向观察时，半导体芯片40的轮廓比定位用凸部18的轮廓(即，外周面18a)稍小。因此，半导体芯片40比夹具30的内周面30a稍小。因此，在夹具30的内部配置半导体芯片40时，能抑制从夹具30向半导体芯片40施加高载荷。由此，能抑制半导体基板42产生破裂、缺欠。在半导体芯片配置工序中，半导体芯片40的外周面由夹具30的内周面30a引导，因此半导体芯片40相对于夹具30被定位。即，经由夹具30，半导体芯片40相对于引线框12被定位。在图9中，通过虚线表示接合用凸部20和发射极44。如图9所示，在沿z方向观察时，接合用凸部20的上表面整体配置在发射极44的轮廓的内侧。通过使用夹具30，如图9所示能够将发射极44和接合用凸部20准确地定位。
接下来，实施回流焊工序。在回流焊工序中，使如图9～11所示组装的层叠体通过回流焊炉。由此，层叠体暂时被加热，然后，层叠体被冷却至常温。当层叠体被加热时，焊料层50熔融。然后，当层叠体冷却时，焊料层50凝固。于是，如图12、13所示，通过焊料层50，将发射极44连接于接合用凸部20，并将信号电极46连接于对应的信号端子26。在实施了回流焊工序之后，将夹具30从引线框12及半导体芯片40拆卸。
接下来，如图14所示，在半导体芯片40上配置集电极端子60，通过焊料层52将集电极48连接于集电极端子60。集电极端子60是与集电极48连接的配线，并且也是用于从集电极48进行散热的散热板。而且，此时，图1的主端子28b连接于集电极端子60。
接下来，如图15、16所示，通过注塑成型来形成将半导体芯片40覆盖的绝缘树脂层70。与各端子的半导体芯片40连接的部分也被绝缘树脂层70覆盖。各信号端子26及各主端子28a～28c从绝缘树脂层70向外侧突出。
接下来，在绝缘树脂层70的外部将引线框12切断，由此将图16中的斜线阴影的部分(系杆22、悬吊引线23等)除去。由此，信号端子26相互分离，并且信号端子26从裸片焊盘14分离。而且，主端子28a～28c相互分离。其结果是，图17所示的半导体装置完成。
接下来，说明以往的半导体装置的制造方法。在以往的制造方法中，如图18所示，使用集电极用的裸片焊盘160与信号端子126一体化后的引线框112。首先，如图18所示，在第一夹具191上安装引线框112。向设于引线框112的孔112a插入第一夹具191的销191a，由此将引线框112相对于第一夹具191进行定位。接下来，在引线框112上安装第二夹具192。向第二夹具192的孔192a插入第一夹具191的销191a，由此第二夹具192相对于第一夹具191被定位。接下来，在第二夹具192的筒状部192b的内部配置半导体芯片140。半导体芯片140具有半导体基板142、发射极144、信号电极146、集电极148。在此，以集电极148朝向下侧的方式配置半导体芯片140。然后，经由焊料层150将集电极148接合于裸片焊盘160。在将集电极148接合于裸片焊盘160之后，将第一夹具191和第二夹具192拆卸。
接下来，通过引线接合，将半导体芯片140的各信号电极146连接于引线框112的对应的信号端子126。
接下来，如图19所示，在第三夹具193安设发射极端子114。第三夹具193具有凹部193a，在该凹部193a内配置发射极端子114。通过凹部193a，将发射极端子114相对于第三夹具193定位。接下来，将半导体芯片140与引线框112连接后的部件安装于第三夹具193。在此，将半导体芯片140的发射极144配置在发射极端子114的接合用凸部114a上。在此，将第三夹具193的销193b向引线框112的孔112a插入，由此将引线框112相对于第三夹具193进行定位。然后，经由焊料层152将发射极144接合于接合用凸部116a。然后，如图20所示，利用绝缘树脂层170将半导体芯片140密封。在绝缘树脂层170的形成后，在绝缘树脂层170的外部将引线框112切断，由此将图20中的斜线阴影的部分(系杆、悬吊引线等)除去。由此，使各端子相互分离。通过以上的工序，基于以往的方法的半导体装置的制造完成。
在以往的方法中，在发射极144与接合用凸部116a之间产生第一夹具191与引线框112的位置偏离、第一夹具191与第二夹具192的位置偏离、第二夹具192与半导体芯片140的位置偏离、第三夹具193与发射极端子114的位置偏离、及第三夹具193与引线框112的位置偏离所累积的位置偏离。由于位置偏离原因多，因此发射极144与接合用凸部116a的位置偏离容易变大。当发射极144与接合用凸部116a的位置偏离大时，在半导体芯片140的一部分难以向发射极端子114传递热量，半导体芯片140的一部分有时会局部性地成为高温。此外，在发射极144与接合用凸部114a的位置偏离极大时，如图21所示，存在接合用凸部114a伸出至发射极144的外侧的情况。这种情况下，焊料层152扩展至比发射极144靠外侧处，焊料层152成为悬垂状。在该结构中，绝缘树脂层170进入焊料层152与半导体基板142之间的间隙。在该构造中，由于焊料层152与半导体基板142之间的绝缘树脂层170的热膨胀而向焊料层152施加极高的应力，因此焊料层152的可靠性极度下降。
相对于此，在实施方式的方法中，夹具30与引线框12的位置偏离、及夹具30与半导体芯片40的位置偏离会影响发射极44与接合用凸部20的位置偏离。由于位置偏离原因少，因此能够抑制发射极44与接合用凸部20的位置偏离。因此，在半导体装置的量产时，能够使散热性稳定。能够防止制造出散热性差的半导体装置的情况。尤其是在实施方式的方法中，如图9所示，发射极44比接合用凸部20大，因此能够更可靠地防止图21所示那样的事态。因此，能够确保焊料层50的可靠性。
另外，在以往的方法中，使用集电极用的裸片焊盘160与信号端子126一体化后的引线框112。在将引线框112(即，图20的斜线部)切断之后，如图20所示，在从绝缘树脂层170露出的位置残存有悬吊引线的残存部160a。悬吊引线的残存部160a连接于集电极用的裸片焊盘160，因此在信号端子126(与发射极为大致相同电位)与残存部160a(与集电极为相同电位)之间产生极大的电位差。因此，在信号端子126与残存部160a之间容易产生沿面放电。因此，在以往的方法中，为了防止沿面放电，而需要在残存部160a与信号端子126之间的绝缘树脂层170的侧面设置切口部180(用于拉长残存部160a与信号端子126之间的沿面距离的凹部)。然而，当设置切口部180时，存在绝缘树脂层170的内部应力增大而绝缘树脂层170的对于裂纹等的耐性下降的问题。
相对于此，在实施方式的方法中，使用发射极用的裸片焊盘14与信号端子26一体化后的引线框12。在将引线框12(即，图16的斜线部)切断之后，如图17所示，在从绝缘树脂层70露出的位置残存有悬吊引线23的残存部23a。残存部23a连接于发射极用的裸片焊盘14，因此信号端子26(与发射极为大致相同电位)与残存部23a(与发射极为相同电位)之间的电位差极小。因此，在残存部23a与信号端子26之间不易产生沿面放电。因此，在它们之间的绝缘树脂层70的侧面不需要切口部。因此，绝缘树脂层70的对于裂纹的耐性提高。而且，由于不需要切口部，从而不需要信号端子26与信号电极46的y方向的补偿。由此，能够在信号端子26的两侧设置悬吊引线23，信号端子26和半导体芯片40的位置精度提高。
另外，在实施方式的制造方法中，如图10所示，接合用凸部20从散热板16的上表面向上侧突出，且在接合用凸部20与夹具30之间设有间隔，因此在信号电极46与散热板16之间能够确保空间。因此，在该空间能够配置相对于信号电极46的配线(即，信号端子26)。因此，能够良好地设置相对于信号电极46的配线。
需要说明的是，在上述的实施方式中，在将夹具30安装于引线框12之后，在夹具30的内部配置半导体芯片40。然而，也可以在夹具30的内部配置了半导体芯片40之后，将夹具30安装于引线框12。但是，实施方式的顺序多是容易稳定实施各工序的情况。
另外，在上述的实施方式中，接合用凸部20与定位用凸部18连结。然而，也可以如图22、23所示将定位用凸部18配置在从接合用凸部20分离的位置。
另外，在上述的实施方式中，接合用凸部20比定位用凸部18高，但也可以如图24、图25所示，接合用凸部20与定位用凸部18为相同高度。
另外，在上述的实施方式中，定位用凸部18沿着接合用凸部20的周围配置。然而，也可以如图26～29所示，将定位用凸部18离散地设置在接合用凸部20的周围。只要能够将夹具30定位即可，定位用凸部18可以任意配置。
另外，在上述的实施方式中，夹具30具有筒形状。然而，也可以如图30～33所示，夹具30具有筒形状以外的形状。需要说明的是，图33示出利用夹具30将2个半导体芯片20定位的结构。在上述的结构中，通过将夹具30卡合于引线框12的定位部和半导体芯片40这两方，也能够将引线框12和半导体芯片40定位。而且，如图34所示，夹具30可以是在板状的构件设有四边形的孔的结构。
另外，在上述的实施方式中，定位用凸部18的上表面整体接合于焊料层50。然而，也可以对定位用凸部18的上表面的外周部实施不具有焊料浸润性的表面处理(例如，粗糙化处理等)。在该结构中，定位用凸部18的上表面的一部分(中央部)接合于焊料层50。这种情况下，定位用凸部18的上表面的具有焊料浸润性的部分(即，连接于焊料的区域)优选比发射极44小。
另外，在上述的实施方式中，通过定位用凸部18将夹具30定位。然而，也可以如图35所示，取代定位用凸部18而设置定位用凹部19。通过使夹具30的外周面30c与定位用凹部19的侧面接触，能够将夹具30定位。
以下列举本说明书公开的技术要素。需要说明的是，以下的各技术要素分别是独立有用的要素。
在本说明书公开的一例的制造方法中，可以是，定位部为凸形状。而且，可以是，在使夹具卡合于定位部的工序中，使夹具的内周面与凸形状的侧面接触。
在本说明书公开的另一例的制造方法中，可以是，定位部为凹形状。而且，可以是，在使夹具卡合于定位部的工序中，使夹具的外周面与凹形状的侧面接触。
在本说明书公开的一例的制造方法中，可以是，在夹具卡合于定位部和半导体芯片的状态下，在沿着半导体芯片与引线框的层叠方向观察时，接合用凸部的与焊料连接的区域整体配置在主电极的轮廓的内侧。
根据该结构，能够防止将主电极与接合用凸部连接的焊料成为悬垂状的情况。
在本说明书公开的一例的制造方法中，可以是，在使夹具卡合于定位部的工序之后，实施使夹具卡合于半导体芯片的工序。
在本说明书公开的一例的制造方法中，可以是，主电极是发射极。而且，可以是，半导体芯片具有：信号电极，设置在与发射极相同的面上；和集电极，设置在位于所述发射极的相反侧的背面。而且，可以是，引线框具有：具有接合用凸部和定位部的主体部；和从主体部延伸出的信号端子。可以是，该制造方法还包括：在集电极连接集电极端子的工序；将信号端子连接于信号电极的工序；形成将半导体芯片覆盖的绝缘树脂的工序；以及在绝缘树脂的形成后将信号端子从主体部切离的工序。
在该制造方法中，在将信号端子和主体部切离之后，信号端子和主体部向绝缘树脂的外部露出。然而，信号端子(即，信号电极)与主体部(即，发射极)之间的电位差小，因此在它们之间不易产生沿面放电。
以上，详细地说明了实施方式，但是它们只不过是例示，并不对权利要求书进行限定。权利要求书记载的技术包括对以上例示的具体例进行了各种变形、变更的技术。本说明书或附图说明的技术要素单独或者通过各种组合来发挥技术有用性，并不限定为申请时权利要求记载的组合。而且，本说明书或附图例示的技术是同时实现多个目的的技术，实现其中的1个目的情况自身具有技术有用性。

Claims (6)

1.一种制造方法，是通过使用夹具将半导体芯片连接于引线框来制造半导体装置的方法，其中，
所述半导体芯片在一个面上具有主电极，
所述引线框具有接合用凸部和在所述接合用凸部的周围配置的由凸形状或凹形状构成的定位部，
所述制造方法包括：
以在所述接合用凸部与所述夹具之间空出间隔的状态使所述夹具卡合于所述定位部的工序；
使所述夹具卡合于所述半导体芯片的工序；及
在所述夹具卡合于所述定位部和所述半导体芯片的状态下，将所述接合用凸部经由焊料连接于所述半导体芯片的所述主电极的工序。
2.根据权利要求1所述的制造方法，其中，
所述定位部为所述凸形状，
在使所述夹具卡合于所述定位部的所述工序中，使所述夹具的侧面与所述凸形状的侧面接触。
3.根据权利要求1所述的制造方法，其中，
所述定位部为所述凹形状，
在使所述夹具卡合于所述定位部的所述工序中，使所述夹具的侧面与所述凹形状的侧面接触。
4.根据权利要求1～3中任一项所述的制造方法，其中，
在所述夹具卡合于所述定位部和所述半导体芯片的状态下，在沿所述半导体芯片与所述引线框的层叠方向观察时，所述接合用凸部的与所述焊料连接的区域整体配置在所述主电极的轮廓的内侧。
5.根据权利要求1～3中任一项所述的制造方法，其中，
在使所述夹具卡合于所述定位部的所述工序之后，实施使所述夹具卡合于所述半导体芯片的所述工序。
6.根据权利要求1～3中任一项所述的制造方法，其中，
所述主电极为发射极，
所述半导体芯片具有：信号电极，设置在与所述发射极相同的面上；和集电极，设置在位于所述发射极的相反侧的背面，
所述引线框具有：主体部，具有所述接合用凸部和所述定位部；和信号端子，从所述主体部延伸出，
所述制造方法还包括：
将所述信号端子连接于所述信号电极的工序；
在所述集电极连接集电极端子的工序；
在将所述接合用凸部、所述信号端子及所述集电极端子连接于所述半导体芯片之后，形成覆盖所述半导体芯片的绝缘树脂层的工序；及
在形成了所述绝缘树脂层之后，将所述信号端子从所述主体部切离的工序。
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