CN104867898A - 具有镀覆的引线框架的半导体器件及其制造方法 - Google Patents
具有镀覆的引线框架的半导体器件及其制造方法 Download PDFInfo
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- CN104867898A CN104867898A CN201510087951.1A CN201510087951A CN104867898A CN 104867898 A CN104867898 A CN 104867898A CN 201510087951 A CN201510087951 A CN 201510087951A CN 104867898 A CN104867898 A CN 104867898A
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Abstract
本发明的各个实施例涉及具有镀覆的引线框架的半导体器件及其制造方法。提供了一种具有各自用于接收和承载半导体芯片的多个插口的载体衬底。半导体芯片布置在插口中,并且在插口中镀覆金属以在半导体芯片上形成与该半导体芯片接触的金属结构。对载体衬底进行切割以形成单独的半导体器件。
Description
技术领域
在本文中描述的各个实施例涉及具有镀覆的引线框架的半导体器件及制造半导体器件的方法。
背景技术
在半导体材料上形成金属层,以提供至半导体材料的良好欧姆接触,并且在集成在半导体材料中的半导体器件的操作期间对在半导体材料中生成的热进行散热。取决于半导体器件的操作,热脉冲可能会发生,需要有效地对热脉冲进行散热。
厚的金属化层的制造可能会带来问题,这是因为常用的沉积技术仅仅允许以低速率进行沉积,这就导致长的制造时间。由于金属与薄半导体材料的热膨胀系数不同的影响,厚金属化层也可能会导致机械应力。此外,需要将沉积的金属化层图案化,这包括附加的制造工艺。
鉴于上述情况,需要进行改进。
发明内容
根据实施例,一种用于制造半导体器件的方法包括:提供具有第一侧、第二侧和各自用于接收和承载半导体芯片的多个插口的载体衬底,插口从载体衬底的第一侧延伸至载体衬底的第二侧;将各自具有第一侧和第二侧的半导体芯片放置在插口中,其中插口使半导体芯片的第一侧的和第二侧的至少部分暴露出来;将金属镀覆在插口中以在半导体芯片的第二侧形成与半导体芯片的第二侧接触的金属结构;以及切断载体衬底以形成单独的半导体器件。
根据实施例,一种用于制造半导体器件方法包括:提供具有第一侧、第二侧和各自用于接收和承载半导体芯片的多个插口的载体衬底,插口从载体衬底的第一侧延伸至载体衬底的第二侧;将各自具有第一侧和第二侧的半导体芯片放置在插口中,其中插口使半导体芯片的第一侧的和第二侧的至少部分暴露出来;提供具有第一侧、第二侧和从第一侧延伸至第二侧的多个开口的覆盖衬底;将覆盖衬底的第二侧与载体衬底的第一侧接合(join)并且与半导体芯片的第一侧接合,其中覆盖衬底的开口使半导体芯片的第一侧的一部分暴露出来;以及将金属镀覆在插口和开口中,以至少在半导体芯片的第一侧形成与半导体芯片的第一侧接触的第一金属结构,以及在半导体芯片的第二侧形成与半导体芯片的第二侧接触的第二金属结构。
根据实施例,一种半导体器件包括由绝缘无机材料制成的绝缘载体结构。载体结构包括至少一个插口。具有第一侧、第二侧和横向边缘的半导体芯片设置在插口中,其中载体结构横向地围绕半导体芯片和横向边缘。金属结构布置在半导体芯片的第二侧与第二侧接触并且嵌入在载体结构中。
在阅读以下详细说明并且在查看对应附图之后,本领域的技术人员将认识到附加的特征和优点。
附图说明
在附图中的部件并不一定按照比例绘制而成,而是将重点放在图示本发明的原理上。而且,在附图中,相同的附图标记指相应的部件。
图1A至图1E图示了根据实施例的在用于制造半导体器件的方法中的工艺步骤。
图2A至图2M图示了根据实施例的在用于制造半导体器件的方法中的工艺步骤。
图3图示了根据实施例的半导体器件。
图4A至图4B图示了根据实施例的在用于制造半导体器件的方法中的工艺步骤。
具体实施方式
在以下详细说明中对附图进行参考,这些附图构成本说明书的一部分,以及在附图中以图示的方式示出了可以实践本发明的各个具体实施例。在这点上,参考所描述的一个或多个附图的取向来使用定向术语,诸如“顶”、“底”、“前”、“后”、“首”、“尾”、“横向”、“垂直”等。因为实施例的部件可以定位在多个不同的取向上,所以定向术语的使用是出于图示之目的,而绝非限制。要理解,在不脱离本发明的范围的情况下,也可以使用其他实施例,而且可以做出结构上或者逻辑上的改变。因此,以下详细说明不应被视为具有限制意义,并且本发明的范围由所附权利要求书定义。所描述的实施例使用了具体的语言,但是该具体语言不应被解释为是对所附权利要求书的范围的限制。
在本说明书中,半导体衬底的第二表面被认为是由半导体衬底的下表面或者背侧表面形成,而第一表面则被认为是由半导体衬底的上表面、前表面或者主表面形成。因此,在本说明书中使用的术语“上方”和“下方”描述了结构特征对于另一结构特征的考虑到该取向的相对位置。
术语“电连接”和“电连接至”描述了在两个元件之间的欧姆连接。
接下来参考图1A至图1E对实施例进行描述。本实施例包括,形成具有嵌入在绝缘载体衬底中的镀覆的引线框架的半导体器件。
参考图1A至图1B,提供了具有第一侧101以及与第一侧101相对的第二侧102的载体衬底100,如在图1B中最佳示出的(bestshown),该图1B图示了图1A的放大的部分。
载体衬底100包括多个插口105。每个插口105的大小和形状设计用于接收和承载半导体芯片。插口105从载体衬底100的第一侧101延伸至载体衬底100的第二侧102,并且通过在载体衬底100中的开口形成。
载体衬底100可以是晶片,以允许如下文所描述的,关于一个单个的半导体芯片,同时处理独立的半导体芯片。因此,以下说明并不限于单个半导体芯片,并且也包含对在载体衬底100的相应插口105中的多个半导体芯片的同时处理。
在图1C中最佳示出的进一步工艺中,将具有第一侧201、第二侧202和横向边缘203的半导体芯片200放置在插口105中。如图1C所图示的,插口105包括用于保持和承载半导体芯片200的外围阶形部103。通常,每个插口105接收单个半导体芯片200。插口105使半导体芯片200的第一侧201的和第二侧202的至少部分不被覆盖。
半导体芯片200可以由适用于制造半导体部件的任何半导体材料制成。这类材料的示例包括但是不限于,基本的半导体材料(诸如,硅(Si))、Ⅳ族化合物半导体材料(诸如,碳化硅(SiC)或者硅锗(SiGe))、二元、三元或者四元Ⅲ-Ⅴ族半导体材料(诸如,砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、氮化镓(GaN)、氮化铝镓(AlGaN)、磷化铟镓(InGaP)或者砷磷化铟镓(InGaAsP))、以及二元或者三元Ⅱ-Ⅵ族半导体材料(诸如,碲化镉(CdTe)和碲化汞镉(HgCdTe)),仅举几例。上面所提及的半导体材料也称为同质结半导体材料。当结合两种不同的半导体材料时,形成异质结半导体材料。异质结半导体材料的示例包括但是不限于,硅(SixC1-x)和SiGe异质结半导体材料。对于功率半导体应用,目前主要使用Si、SiC和GaN材料。
在如图1D所示的进一步的工艺中,将金属镀覆在载体衬底100的第二侧102的插口105中,以在半导体芯片200的第二侧202形成与第二侧202接触的金属结构152。通常,金属结构152与载体衬底100的第二侧102齐平。由于金属在镀覆时可以生长在载体衬底100的第二侧102之上,所以可以通过对载体衬底100和金属结构152进行研磨来获得平整表面。
在进一步工艺中,例如通过锯180或者激光对载体衬底100进行切割以形成单独的半导体器件600。其他切割工艺,例如划片和裂片等,也适用。切割线与相应芯片200的横向边缘203间有距离,从而使得未切割到半导体芯片200。由于仅仅对载体衬底100进行切割,所以可以使用适应于载体衬底100的材料的切割工具,这改进了切割质量。未切割到半导体芯片200。可以避免载体衬底100的碎裂和对半导体芯片200的污染。此外,半导体芯片200的横向边缘203也保持嵌入在载体衬底100中。如图1E所示,在切割之后,玻璃衬底100横向地围绕半导体芯片200,并且保护半导体芯片200的横向边缘203。
此外,由切割后的载体衬底100和芯片200形成的混合结构为芯片200提供了充足的机械稳定性。由此,可以可靠地处理薄的芯片200。
载体衬底200可以是无机绝缘材料。合适的无机绝缘材料是非晶或者多晶的绝缘材料。例如玻璃衬底和陶瓷。
如图1D所图示的,每个芯片200独立地设置有单独的金属结构152。本工艺也可以称为独立芯片200的直接金属化。独立芯片200与晶片不同,这是因为芯片200是通过切割具有多个独立半导体部件的半导体晶片材料而形成的。沿着在相邻半导体部件之间延伸的线对晶片进行切割,以形成各自包括半导体部件的单独的半导体芯片。
根据实施例,通过对半导体晶片进行处理以形成多个半导体部件,并且通过对半导体晶片进行切割以形成其中每个包括半导体部件的单独的半导体芯片,来形成半导体芯片。
金属结构152形成嵌入在载体衬底100中的“原位”镀覆的引线框架,这是因为引线框架被载体衬底100横向地围绕。由此,载体衬底100提供了,在使金属结构152的底表面暴露出来的同时、横向地围绕半导体芯片200和金属材料152的电绝缘。可以在金属结构152的底表面上设置至半导体芯片200和集成在半导体芯片200中的半导体部件的电连接。
通过镀覆在半导体芯片200上直接形成引线框架,避免了通常用于将单独形成的引线框架与半导体芯片的背侧接合的焊接工艺。由此,可以避免与焊接相关联的问题,诸如受焊剂污染、蠕变焊料(creeping solder)、或者在焊料层中形成空隙(void)。这改进了在由金属结构152形成的引线框架与半导体芯片200之间的电接触和热接触。此外,也可以避免在焊接期间发生的热机械应力。
与常见方法不同,由金属结构形成的引线框架一体地形成在半导体芯片200上,在半导体芯片200与引线框架152之间无任何焊料接口。
由于在每个独立芯片200上进行了镀覆,因为芯片200的大小比半导体晶片的大小小得多,所以可以减少或者完全避免芯片200的弯曲。这也有利于进一步的工艺。
在本文中描述的工艺使得能够形成具有在不使用焊接工艺的情况下与引线框架一体地形成的薄芯片的封装。由金属结构152形成的引线框架直接形成在半导体芯片200的背侧金属化上。通常,集成在半导体芯片200中的每个半导体部件均设置有背侧金属化,以及也设置有前侧金属化。背侧金属化和前侧金属化中的每一个形成在晶片级、在通过切割半导体晶片将半导体芯片200分开之前。背侧金属化和前侧金属化可以具有例如在0.5μm至3μm,尤其在1μm至2μm范围内的厚度。背侧金属化和/或前侧金属化可以是单个金属层或者金属层堆叠。例如AlTiAg,其中Ag是金属层堆叠的暴露金属层或者上金属层。
镀覆的金属结构152可以具有在大约30μm至大约500μm范围内的厚度,例如,在大约30μm或者50μm与300μm之间,或者在30μm与100μm之间。镀覆的金属结构152的厚度通常大于30μm。在进一步实施例中,镀覆的金属结构152的厚度通常大于或者等于300μm。
背侧金属化与金属结构152之间的最终厚度比可以在大约1:50至大约1:300之间。这样的厚度比可以通过最终机械加工步骤来调节,该最终机械加工步骤可以包括:对载体衬底100和金属结构152进行研磨以产生平面的金属和载体衬底表面,或者将金属结构152和载体衬底100减薄以产生特定的堆叠厚度。
这样的厚金属结构152通常不形成在晶片级,这是因为厚金属结构能够导致晶片的明显弯曲。与此不同,由于芯片横向上比晶片小得多,所以避免了芯片200的弯曲。
取决于集成在半导体芯片200中的半导体部件的额定阻断电压,半导体芯片200的厚度有所变化。例如,半导体芯片200可以具有在大约50μm至150μm范围内的厚度,通常为小于或等于70μm 70μm。
载体衬底100通常具有比金属结构152的最终厚度更大的厚度。载体衬底100的厚度可以在例如200μm至500μm范围内并且通常在300μm至400μm范围内,以提供充足的空间,用于接收半导体芯片200以及用于形成嵌入式金属结构152。此外,给定的厚度还提供了充足的机械稳定性。
载体衬底100的插口105可以形成为,使得半导体芯片200的相对侧201、202,或者侧201、202中的仅一侧,相对于载体衬底100的侧101、102凹进。载体衬底100的侧101、102,或者侧101、102中的至少一侧,突出半导体芯片200的相应侧201、202,以提供充足的内部空间用于形成金属结构152。
图1A至图1E示出了单独的金属结构152的形成,其中每一个金属结构152用于独立半导体芯片200。根据实施例,也可以为一组独立芯片200形成公共金属结构,以形成包括至少两个单独的芯片200的电路。由此,可以形成混合电路布置,诸如逆变器。混合电路布置可以包括至少两个芯片200,其中每一个包括诸如功率晶体管和功率二极管的半导体部件。在独立芯片200之间的电连接可以通过公共金属结构(其也用作公共引线框架)形成。
在半导体芯片200上直接形成引线框架或者公共引线框架,改进了中长加热脉冲的散热。通常,在短加热脉冲、中加热脉冲与长期(permanent)加热脉冲之间有所区别。
短加热脉冲发生在大约3μs与10μs之间的短击穿期间。由短击穿生成的加热脉冲通常可以被半导体材料吸收。然后,随后将热分散至引线框架及其周围。直接形成的或者原位形成的金属结构152在此处用作附加的热电容器,并且在无任何焊料的情况下附着至热源,例如,半导体芯片200的漏极。
中加热脉冲发生在大约1ms与100ms之间的中击穿期间。由中击穿生成的加热脉冲需要由引线框架吸收,这是因为由于薄半导体芯片的较小体积的影响半导体材料的热容太小。由于没有通过引线框架的直接形成而形成焊接接口,所以改进了半导体芯片200的热导出(de-heating)。由此,引线框架的整个体积都可以促进散热。
长期生热发生在半导体芯片的操作期间并且必须被有效地传输至周围环境。针对持续加热,如在本文中描述的直接形成的引线框架方便散热,这是由于焊接接口不阻碍热传输。
参考图2A至图2M对更加详细的实施例进行了阐释。使用了针对也在图1A至图1E中示出的相应部件的相同的附图标记。
在以下说明中,载体衬底100由第一玻璃衬底100形成,但是不限于玻璃材料。通常,使用具有至少400μm的厚度的玻璃晶片。
仅仅出于更好进行图示之目的,图2A仅仅图示了第一玻璃衬底100的单个插口105,第一玻璃衬底100通常包括多个插口105。
根据实施例,提供了具有插口105的第一玻璃衬底100,如图2A所图示的。插口105例如可以通过使用形成在第一玻璃衬底100的第一侧101的第一掩模191和形成在第一玻璃衬底100的第二侧102的第二掩模192进行湿法化学蚀刻来形成。掩模191、192中的每一个限定出待形成在第一玻璃衬底100中的开口或者空腔106、107的大小和位置。第一和第二掩模191、192的开口彼此对准,使得在第一和第二掩模191、192中的相应开口彼此重叠。当从垂直投影方向向第一玻璃衬底100的第二侧102看去时,在第一掩模191中的开口大于在第二掩模192中的开口,并且完全覆盖第二掩模192中的开口。在第一掩模191中的开口的大小适应为,大于半导体芯片的大小,以便可以将半导体芯片200放置到插口105中。不同于此,在第二掩模192中的开口的大小小于半导体芯片200的大小。
然后,将第一和第二掩模191、192用作蚀刻掩模对第一玻璃衬底100进行蚀刻。例如,可以使用HF进行湿法化学蚀刻。可以使用碱性溶液从第一玻璃衬底100去除第一和第二掩模191、192。
从第一玻璃衬底100的相对侧101、102形成的开口106、107,一起形成插口105。由于在第一和第二掩模191、192中的开口的大小不同的影响,在推进的蚀刻前沿回合之处形成台阶103。通常,首先从一侧蚀刻第一玻璃衬底100,然后从另一侧蚀刻第一玻璃衬底100。蚀刻的顺序不受限制。单独的蚀刻工艺,使得能够对开口107和106中的每一个的蚀刻深度进行独立调节,由此对台阶103的相对于第一玻璃衬底100的厚度方向的垂直位置进行独立调节。作为替代方案,可以在单个蚀刻步骤中从两侧101、102蚀刻第一玻璃衬底100。
台阶103形成插口105的外围阶形区域103。台阶103是开口106和107的不同的大小所导致的。
作为替代方案,可以使用激光铣削(laser milling)为插口105提供外围阶形区域103。
由此,对第一玻璃衬底100进行双侧处理以形成各自具有外围阶形部103的插口105。
在如图2B所图示的进一步工艺中,提供了覆盖衬底(coversubstrate)110,其具有第一侧111、第二侧112、和从第一侧111延伸至第二侧112的多个开口115、116。覆盖衬底110可以是与第一玻璃衬底100相同的材料,诸如玻璃或者陶瓷。在下文中,覆盖衬底110称为第二玻璃衬底110。
第二玻璃衬底110可以具有在至少300μm至550μm范围内的厚度,以便机械稳定。第二玻璃衬底110的大小可以近似等于第一玻璃衬底100的大小。图2B仅仅示出了第二玻璃衬底110的一部分,该第二玻璃衬底110通常是具有多个开口115、116的玻璃晶片。开口115、116由第二玻璃衬底110的部分117分开。
开口115、116的大小可以不同,因为它们用于形成与相应半导体芯片200的不同区域电接触的不同厚度的金属结构。在进一步实施例中,第二玻璃衬底110针对每个半导体芯片200仅仅具有一个开口,例如在集成到半导体芯片200中的功率二极管的情况下。
第二玻璃衬底110的开口115、116也可以通过使用掩模湿法化学来形成。作为替代方案,可以使用激光铣削。
与第一玻璃衬底100不同,对第二玻璃衬底110进行单侧处理,这是由于此处不需要阶形部。然而,若需要,双侧处理也是可以的。
在如图2C所图示的进一步工艺中,至少在第一玻璃衬底100的第一侧101和在插口105的侧壁上形成导电种子层120。种子层120是使得种子层120的所有部分电连接的连接层,并且用于稍后的镀覆工艺。
种子层120可以例如通过物理汽相沉积(PVD)或者化学汽相沉积(CVD)形成。可以将单个金属层或者金属层堆叠用作种子层120。例如Ti/Ag堆叠。
在如图2D所图示的进一步工艺中,将具有第一侧201、第二侧202、横向边缘203、和在横向边缘203处的外围区域208的半导体芯片200,放置或者容纳在插口105中。将半导体芯片200布置为,外围区域208与在插口105的外围阶形区域103中的种子层120接触。
插口105使半导体芯片200的第一侧201的和第二侧202的至少部分暴露出来。在图2D的实施例中,第一侧201保持完全暴露出来,而第二侧202除了外围区域208之外保持暴露出来。
然后,将第二玻璃衬底110的第二侧112与第一玻璃衬底100的第一侧101接合,其中种子层120在第一和第二玻璃衬底100、110之间,如图2E所图示的。使开口115和116与形成在半导体芯片200的第一侧210的相应金属化区域对准,以保持这些金属化区域暴露出来。这将结合图3进行更加详细的阐释。
为了将第一和第二玻璃衬底100、110接合,在接合工艺之前,也可以形成由粘合材料130形成的粘合键合层。例如,可以使用市售的并且大体上耐受恒温T<205℃的环氧树脂。可以将树脂印刷或者滚(roll)到第一玻璃衬底100的第一侧101和/或第二玻璃衬底110的第二侧112上。也可以使用玻璃焊料,例如可以通过孔版印刷工艺涂敷的玻璃料。玻璃焊料大体上可以耐受温度T<400℃。
如图2F所图示的,然后将接合的第一和第二玻璃衬底100、110的布置,其也可以称为复合衬底或者复合晶片,上下颠倒。然后,施加适度的机械压力和温度,以在第一和第二玻璃衬底100、110之间建立坚固的键合。
也可以将半导体芯片200轻轻按压,倚靠着第二玻璃衬底110的待与第二玻璃衬底110接合的第二侧112。由于施加了压力,所以将在第一和第二玻璃衬底100、110之间的粘合材料130压入到形成在第一玻璃衬底100的阶形部103与第二玻璃衬底110的部分之间的开放空间中,该开放空间覆盖半导体衬底200的边缘203。该开放空间形成周围凹槽(circumferential groove)109。除了将部件固定在一起之外,粘合材料130也充当电绝缘,并且保护半导体芯片200的横向边缘203。这将在下文进一步进行描述。粘合材料130可以部分地或者全部地填充周围凹槽109。
图2F示出了第二玻璃衬底110的开口115、116的外边缘相对于第一玻璃衬底100的外围阶形部103并且也相对于半导体芯片200的边缘203向内凹进。由此,周围凹槽109由第二玻璃衬底100和第一玻璃衬底100的外围阶形部103一起形成。半导体芯片200沿着半导体芯片200的外围区域208与周围凹槽109啮合。由此,半导体芯片200沿着其外围区域208被第一和第二玻璃衬底100、110围起。
接合的第一和第二玻璃衬底100、110形成晶片堆叠,通常是玻璃晶片堆叠,其中每个半导体芯片200固定在插口105的周围凹槽109中。第一玻璃衬底100的第二侧102形成晶片堆叠的第二侧,而第一玻璃衬底100的第一侧111形成晶片堆叠的第一侧。晶片堆叠也可以被描述为,用于承载半导体芯片200的绝缘的载体结构或者复合结构。
在如图2G所图示的进一步工艺中,将由此形成的具有接合的第一和第二玻璃衬底100、110和半导体芯片200的绝缘载体结构翻转过来,使得半导体衬底200的第一侧201重新朝上。至少在第二玻璃衬底110的开口115、116的侧壁上和在半导体芯片200的第一侧201的暴露部分上,形成另外的导电种子层125。可以通过与用于种子层120的相同的工艺和材料来形成另外的种子层125。
图2H图示了进一步的工艺,其包括:在第二玻璃衬底110的第一侧111形成绝缘层140以覆盖另外的种子层125,而使在开口115、116的侧壁上和在半导体芯片200的第一侧201的另外的种子层125暴露出来。
可以通过任何其他涂敷工艺,将绝缘层140印刷或者滚到或者施加到第二玻璃衬底110的第一侧111的平面表面上。绝缘层140覆盖第二玻璃衬底110的平面部以防止将金属镀覆在这些区域上。
在进一步工艺中,将金属镀覆在插口105中,以在半导体芯片200的第二侧202形成与第二侧202接触的金属结构152。通常使用电镀,这是由于其允许仅仅在具有电连接种子层的表面上选择性地进行镀覆。对于电镀,使部分地布置在第一和第二玻璃衬底100、110之间的种子层120在所选区域处被电接触(electrically contacted),例如在由第一和第二玻璃衬底100、110形成的晶片堆叠的外边缘处。在图21中的170处示意性地示出了至种子层120的电接触。在图171图示了对电极。
在镀覆工艺开始时,虽然电接触了在外区域上的种子层120,但是仅仅在第一玻璃衬底100的第二侧102处、在插口的阶形部103上和的内壁部上沉积了金属,这是由于半导体芯片200通过粘合材料130保持与种子层120电绝缘。结果,形成了初始镀覆层或者第一镀覆层152a。在图2I中通过箭头指示了在镀覆工艺开始时的主生长方向。
当初始镀覆层152a生长并且接触到半导体芯片200的暴露的第二侧202时,半导体芯片200的背侧金属化变为与种子层120电连接,并且在半导体芯片200的第二侧202上沉积金属开始形成主镀覆层或者第二镀覆层152b。这在图2J中进行了图示。主生长方向反转,并且在图2J中金属结构152从半导体芯片200向下生长。由于晶片堆叠在金属镀覆期间的取向可以与在图2J中图示的取向不同,所以向下生长仅仅指示朝着晶片堆叠的第二侧102的生长方向。该工艺也可以被描述为背侧镀覆工艺。
由此产生的金属结构152由初始镀覆层152a和主镀覆层152b形成。由于生长是一个连续的工艺,所以在这些镀覆层之间可能观察不到接口。
若需要,镀覆金属可以过度生长第二侧102至给定程度,并且可以通过在此后的工艺中的机械研磨或者抛光被平面化。
例如,镀覆金属可以是Cu和/或Ni。镀覆金属结构152的厚度可以是至少30μm,如上面描述的。通常镀覆Cu,这是由于Cu在导电和导热方面有优越性。
电镀允许按照比常见沉积工艺更高的沉积速率形成金属结构152。而且,可以通过仅仅提供给具有在其处应该形成有金属区域的种子层的那些区域,来控制沉积。此外,电镀将仅仅发生在被电接触的种子层上。因此,通过电镀来沉积金属,能够图案式地镀覆(pattern plating)。此外,不需要随后对金属区域152进行结构化。
图2K图示了在玻璃衬底110的第一侧111处至相应开口115、116中的、和在半导体芯片200的暴露部分上的镀覆工艺。镀覆使得在半导体芯片(200)的第一侧201上形成与第一侧201接触的另外的金属结构151、153。可以使用相同的材料进行该前侧镀覆工艺。对于该前侧镀覆工艺,另外的种子层125在175所指示的所选区域处电连接,该所选区域通常布置在由第一和第二玻璃衬底100、110形成的晶片堆叠的外围区域中。对电极在172处图示。
图2J至图2K示出了在半导体芯片200的第一和第二侧201、202处的顺序的镀覆。镀覆工艺的顺序也可以相反。此外,可以在两侧同时执行镀覆。在这种情况下,种子层120和另外的种子层125两者都被电接触。
镀覆工艺也对在玻璃衬底100、110与半导体芯片之间的间隙进行填充,这有利于包封半导体芯片200。这也改进了机械稳定性和散热。通常,在金属结构152和另外的金属结构151和153中未留下空隙。
在进一步的工艺中,如图2L所图示的,第二玻璃衬底110的第一侧111和/或第一玻璃衬底100的第二侧102接地。研磨可以包括:对相应玻璃衬底100、110和相应金属结构151、152、153进行研磨,以例如去除在相邻金属结构之间形成暂时电连接的过度生长的材料。
也可以采用研磨来将晶片堆叠减薄。此外,在使用例如具有减少的孔堵塞的多孔磨料的共用机械研磨工艺中,玻璃材料和金属两者都可以接地。合适的磨轮可以得自例如日本的DISCO集团。
晶片堆叠的厚度可以减少至大约500μm,这仍然足够厚到可以机械稳定。在研磨之后,半导体芯片200的背侧金属化和/或前侧金属化与相应金属结构151、152、153之间的最终厚度比可以在大约1:50至大约1:300范围内。
对晶片堆叠的两侧的研磨或者机械处理导致晶片堆叠的经处理的第一侧111a和晶片堆叠的经处理的第二侧102a。
在进一步工艺中,如图2M所图示的,沿着在相邻半导体芯片200之间或者(若需要包括至少两个单独的半导体芯片200的混合器件)在半导体芯片组之间延伸的切割线,对晶片堆叠进行切割。在图2M中通过断线160对该切割进行了图示。也可以使用锯切或者激光切割来替代划片和裂片。
图3图示了通过上述工艺中的任何工艺形成的半导体器件300。器件300包括由如下各项形成的晶片堆叠:接合的第一和第二玻璃衬底100、119;和被容纳在形成在第一和第二玻璃衬底100、110之间的环形凹槽109中的单个半导体芯片200。
半导体芯片200包括半导体部件,该半导体部件在本实施例中是功率FET,但是不限于此。
半导体部件通常可以是诸如双端子部件或者三端子部件的功率半导体部件。双端子器件的示例是pn二极管和肖特基二极管,而三端子器件的示例是FET和IGBT。这些部件通常是垂直部件,具有由在半导体芯片200的第一侧202上的第一金属化251形成的至少一个电极、和由在半导体芯片200的第二侧202上的第二金属化252形成的至少另一电极。半导体芯片200的第一侧201可以是例如半导体部件的前侧,在其处布置有例如FET的源极区域。半导体芯片200的第二侧202可以是例如半导体部件的背侧,在其处布置有例如FET的漏极区域。
虽然图3示出了朝上的第一侧201,但是也可以使半导体芯片200的取向相反。
半导体芯片包括具有漂移区域223的半导体材料210。源极区域221和体区域222形成在半导体材料210的第一侧211处,而漏极区域224和在漏极区域224与漂移区域221之间的可选场停止区域形成在半导体材料210的第二侧212处。源极和主体区域221、220形成功率FET的相应单元220。
漏极金属化252形成在半导体材料210的与漏极区域224接触的第二侧212。此处漏极金属化252形成背侧金属化。
源极金属化251和栅极金属化253形成在半导体材料210的第一侧211上。源极金属化251通过源极塞232与源极区域221电连接。栅极金属化253与栅极电极结构231电连接。电绝缘由布置在栅极电极结构231与半导体衬底210的第一侧211之间的栅极电介质241以及由绝缘层或者层堆叠242提供。此处源极和栅极金属化251、253形成半导体芯片200的前侧金属化的单独部分。
如图3进一步所图示的,漏极金属化252、源极金属化251和栅极金属化253分别暴露在半导体芯片200的第二侧和第一侧202、201。第二玻璃衬底110的开口115和116适应于源极金属化251和栅极金属化253的大小并且与其对准。通常,开口115和116小于栅极金属化253和源极金属化251的横向延伸,以补偿在第二玻璃衬底110与半导体芯片200之间的任何未对准。金属结构151、153形成为通过另外的种子层125与这些金属化251、253直接接触。分别在金属结构252、251与源极金属化和栅极金属化251、253之间无焊接层形成。
金属结构152与漏极金属化252直接接触,这是由于在半导体芯片200的第二侧202尚未形成种子层。因此,漏极金属化252的上层和暴露层通常适应于促进镀覆。例如,可以将Ag层用作暴露层。
图3还图示了,粘合材料130可以部分地覆盖半导体芯片200的在外围区域208中的第二侧202。由于粘合材料130在按压第一玻璃衬底100和第二玻璃衬底110时被驱入周围凹槽109中,所以这类覆盖可以发生。这改进了半导体芯片200的机械固定并且改进了横向边缘203的绝缘。
图4A和图4B图示了工艺的变型,其包括:形成电桥以将金属结构电连接。电桥与金属结构一体地形成。
工艺与上面描述的基本相同,除了第一玻璃衬底400附加地包括形成在第一玻璃衬底400的第二侧402处在所选插口405之间的沟槽408。沟槽408的底部从第一玻璃衬底400的第二侧402凹进。可以通过湿法化学蚀刻或者激光铣削来形成沟槽408。
图4A图示了在镀覆之后的晶片堆叠,而图4B图示了在研磨和使用切割工具480进行切割之后的晶片堆叠。如图4B所示,相邻半导体芯片200的金属结构152通过与相应金属结构152一体地形成的电桥或者连接154来保持电连接。桥154与金属结构152一起形成嵌入在第一玻璃衬底400中的引线框架。引线框架在晶片堆叠的经处理的第二侧402a暴露。
如图4B进一步所示,由桥154电连接的半导体芯片200不通过切割彼此分开,并且在一起形成包括电连接以形成电路的至少两个(通常是给定数量的)半导体芯片200的半导体器件500。切割线在由单独的半导体芯片200形成的组之间延伸。由此形成具有一体地或者原位地形成的引线框架的混合电路。例如IGBT与形成IGBT的体二极管的二极管的结合。
在进一步变型中,电桥也可以形成在晶片堆叠的第一侧处在另外的金属结构151与153之间。这允许在无任何键合接线或者焊接工艺的情况下形成电路。在半导体芯片200的两侧都有较厚金属结构151、152、153附加地改进了散热,原因在于它们一起形成用于对热脉冲进行吸收和散热的大体积。
根据实施例,半导体器件包括由绝缘无机材料制成的绝缘载体结构100、110。载体结构100包括至少一个插口105。将具有第一侧201、第二侧202和横向边缘203的半导体芯片200设置在插口105中,其中绝缘载体结构100、110横向地围绕半导体芯片200的横向边缘203。将金属结构152布置在半导体芯片200的第二侧202上并且与第二侧202接触,并且嵌入在绝缘载体结构100、110中。
根据进一步实施例,绝缘载体结构100、110包括周围凹槽109,该周围凹槽109包围了半导体芯片200的外围区域208。半导体芯片200可以通过粘合剂而固定在周围凹槽109中。
根据实施例,半导体芯片200包括:半导体材料210,具有形成在半导体材料210的第一侧211处在半导体材料210中的第一掺杂区域221、和形成在半导体材料210的第二侧212处在半导体材料中210中的第二掺杂区域。第一掺杂区域221与形成在半导体材料210的第一侧211上的第一金属化251电连接。第二掺杂区域224与形成在半导体材料210的第二侧212上的第二金属化252电连接。第二金属化252被金属结构152覆盖并且与金属结构152电接触。
根据实施例,第一金属化251被另外的金属结构151覆盖并且与另外的金属结构151电接触。
根据实施例,半导体器件包括至少两个插口405,其中每一个插口405支持单独的半导体芯片200。每个半导体芯片200设置有在晶片堆叠的第二侧处的金属结构152。半导体器件进一步包括由嵌入在绝缘载体结构中的金属桥154形成的电连接。金属桥154将单独的半导体芯片200的金属结构152电连接,并且与金属结构152一起形成公共引线框架。
在本文中描述了用于制造包括由载体衬底或者绝缘载体结构保持的半导体芯片的器件的工艺。该器件进一步包括与半导体芯片接触的、原位形成的引线框架。将引线框架嵌入在载体衬底或者绝缘载体结构中。
可以对单独的半导体芯片进行共同地处理,以在不需要单独的键合工艺的情况下,为每个半导体芯片一体地形成引线结构和其他金属结构。
为了制造具有两个或者更多个单独的半导体芯片200的半导体器件,将半导体芯片200放置在载体衬底400或者绝缘载体结构400、110的插口405中。在该阶段中,半导体芯片200彼此不电连接,并且通过载体衬底400(绝缘载体结构400、111)彼此隔开并且电绝缘。通过将金属镀覆到形成在载体衬底400的一侧或者两侧的沟槽408和插口405中,在半导体芯片200之间的电连接154与金属结构152在一起形成。金属结构152和电连接154一起形成公共引线框架。半导体芯片200的类型可以是相同的或者不同的。例如,可以将功率二极管和功率FET结合在单个半导体器件中。
如本文中描述的,根据实施例,提供了具有各自用于接收和承载半导体芯片的多个插口105、405的载体衬底100。将半导体芯片200布置在插口105、405中,并且将金属镀覆在插口105中以在半导体芯片200上形成与半导体芯片200接触的相应金属结构152。对载体衬底100进行切割以形成单独的半导体器件300、500、600。
使用“下面”、“之下”、“下”、“之上”、“上”等与空间相关的术语是出于方便说明之目的,用于阐释一个元件相对于第二个元件的定位。这些术语旨在涵盖除了在图中所描绘的取向之外的装置的不同取向。进一步地,诸如“第一”、“第二”等术语还可以用于描述各种元件、区域和部分等,而非旨在构成限制。贯穿本说明,类似的术语表示类似的元件。
如在本文中使用的,“具有”、“包含”、“包括”等术语为开放性术语,表示存在所陈述的元件或者特征,但也不排出存在其它的元件或者特征。冠词“一”、“一个”和“该”旨在包括单数形式和复数形式,除非本文另有明确说明。
考虑到上述变化和应用的范围,应明白,本发明不受前述说明的限制,也不受附图的限制。而是,本发明仅受以下权利要求书及其法律等同物的限制。
Claims (20)
1.一种用于制造半导体器件的方法,包括:
提供载体衬底,所述载体衬底具有第一侧、第二侧和多个插口,其中每个插口用于接收和承载半导体芯片,所述插口从所述载体衬底的所述第一侧延伸至所述第二侧;
将半导体芯片放置在所述插口中,所述半导体芯片中的每一个具有第一侧和第二侧,其中所述插口使所述半导体芯片的所述第一侧的至少部分和所述第二侧的至少部分暴露出来;
在所述插口中电镀金属,以在所述半导体芯片的所述第二侧上形成与所述半导体芯片的所述第二侧接触的金属结构;以及
切割通过所述载体衬底,以形成单独的半导体器件。
2.根据权利要求1所述的方法,其中每个半导体芯片包括外围区域,并且其中相应的所述半导体芯片放置为,使所述外围区域与相应的所述插口的外围阶形区域接触。
3.根据权利要求1所述的方法,进一步包括:
至少在所述载体衬底的所述第二侧上并且在所述插口的侧壁上,形成种子层。
4.根据权利要求1所述的方法,其中提供所述载体衬底包括:
通过湿法化学蚀刻和激光铣削中的至少一种,形成所述插口。
5.根据权利要求1所述的方法,其中提供所述载体衬底包括:
在所述载体衬底的所述第二侧中、在所选的插口之间,形成沟槽。
6.根据权利要求1所述的方法,其中通过粘合键合,将所述半导体芯片固定在所述插口中。
7.根据权利要求1所述的方法,其中所述载体衬底包括玻璃和陶瓷中的至少一种。
8.根据权利要求1所述的方法,进一步包括:
提供覆盖衬底,所述覆盖衬底包括第一侧、第二侧、和从所述第一侧延伸至所述第二侧的多个开口;
使所述覆盖衬底的所述第二侧与所述载体衬底的所述第一侧接合并且与所述半导体芯片的所述第一侧接合,其中所述覆盖衬底的所述开口使得所述半导体芯片的所述第一侧的部分暴露出来;
在所述覆盖衬底的所述开口中电镀金属,以至少在所述半导体芯片的所述第一侧上形成与所述半导体芯片的所述第一侧接触的另外的金属结构;以及
切割通过所述覆盖衬底和所述载体衬底,以形成所述单独的半导体器件。
9.根据权利要求8所述的方法,进一步包括:
在镀覆所述金属之前,至少在所述覆盖衬底的所述开口的侧壁上并且在所述半导体芯片的所述第一侧的暴露的所述部分上,形成种子层。
10.根据权利要求9所述的方法,进一步包括:
在所述覆盖衬底的所述第一侧上形成绝缘层,以覆盖所述种子层,同时使在所述开口的所述侧壁上和在所述半导体芯片的所述第一侧上的所述种子层暴露出来。
11.根据权利要求8所述的方法,进一步包括:
研磨所述覆盖衬底的所述第一侧和所述载体衬底的所述第二侧中的至少一个。
12.根据权利要求8所述的方法,其中所述覆盖衬底包括玻璃和陶瓷中的至少一种。
13.根据权利要求3所述的方法,其中镀覆金属包括:在所述种子层上形成第一镀覆层,以及当所述第一镀覆层与所述半导体芯片的所述第二侧接触时,在所述半导体芯片的所述第二侧上形成第二镀覆层,其中所述第一镀覆层和所述第二镀覆层一起形成所述金属结构。
14.一种用于制造半导体器件的方法,包括:
提供载体衬底,所述载体衬底具有第一侧、第二侧和多个插口,所述多个插口中的每一个用于接收和承载半导体芯片,所述插口从所述载体衬底的所述第一侧延伸至所述第二侧;
将半导体芯片放置在所述插口中,所述半导体芯片中的每一个具有第一侧和第二侧,其中所述插口使所述半导体芯片的所述第一侧的至少部分和所述第二侧的至少部分暴露出来;
提供覆盖衬底,所述覆盖衬底包括第一侧、第二侧、和从所述第一侧延伸至所述第二侧的多个开口;
使所述覆盖衬底的所述第二侧与所述载体衬底的所述第一侧接合并且与所述半导体芯片的所述第一侧接合,其中所述覆盖衬底的所述开口使所述半导体芯片的所述第一侧的相应的部分暴露出来;以及
在所述插口和所述开口中电镀金属,以至少在所述半导体芯片的所述第一侧上形成与所述半导体芯片的所述第一侧接触的第一金属结构,并且在所述半导体衬底的所述第二侧上形成与所述半导体芯片的所述第二侧接触的第二金属结构。
15.根据权利要求13所述的方法,其中提供所述载体衬底包括:
在所述载体衬底的所述第二侧中、在所选的插口之间,形成沟槽,其中所述沟槽连接所选的插口并且填充有金属以在所选的所述半导体芯片的相应的所述第二金属结构之间,形成电连接。
16.一种半导体器件,包括:
绝缘载体结构,由绝缘无机材料组成,所述载体结构包括至少一个插口;
半导体芯片,包括第一侧、第二侧和横向边缘,所述半导体芯片设置在所述插口中,其中所述载体结构横向地围绕所述半导体芯片和所述横向边缘;以及
金属结构,在所述半导体芯片的所述第二侧上,与所述第二侧接触,并且嵌入到所述载体结构中。
17.根据权利要求16所述的半导体器件,其中所述金属结构具有在大约30μm至大约500μm范围内的厚度。
18.根据权利要求16所述的半导体器件,其中所述绝缘载体结构包括:载体衬底、和通过粘合键合与所述载体衬底接合的覆盖衬底。
19.根据权利要求16所述的半导体器件,其中所述绝缘载体结构包括周围凹槽,所述周围凹槽包围所述半导体芯片的外围区域。
20.根据权利要求16所述的半导体器件,其中所述半导体芯片包括:半导体材料,包括第一掺杂区域和第二掺杂区域,所述第一掺杂区域形成在所述半导体材料的第一侧处、在所述半导体材料中,所述第二掺杂区域形成在所述半导体材料的第二侧处、在所述半导体材料中,其中所述第一掺杂区域与形成在所述半导体材料的所述第一侧上的第一金属化电连接,并且其中所述第二掺杂区域与形成在所述半导体材料的所述第二侧上的第二金属化电连接,其中所述第二金属化被所述金属结构覆盖并且与所述金属结构电接触。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108695177A (zh) * | 2017-03-29 | 2018-10-23 | 丰田自动车株式会社 | 半导体装置及其制造方法 |
CN111081667A (zh) * | 2018-10-19 | 2020-04-28 | 现代自动车株式会社 | 半导体子组件和半导体功率模块 |
CN113257679A (zh) * | 2020-01-28 | 2021-08-13 | 英飞凌科技股份有限公司 | 具有由功率半导体管芯的负载端子接合焊盘形成的可焊接接触焊盘的半导体封装及制造方法 |
CN113257678A (zh) * | 2020-01-28 | 2021-08-13 | 英飞凌科技股份有限公司 | 半导体封装及其制造方法 |
TWI784400B (zh) * | 2020-01-30 | 2022-11-21 | 日商大口電材股份有限公司 | 引線框架 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10163675B2 (en) | 2016-06-24 | 2018-12-25 | Invensas Corporation | Method and apparatus for stacking devices in an integrated circuit assembly |
KR102163662B1 (ko) * | 2018-12-05 | 2020-10-08 | 현대오트론 주식회사 | 양면 냉각 파워 모듈 및 이의 제조방법 |
US10892209B2 (en) * | 2019-03-25 | 2021-01-12 | Texas Instruments Incorporated | Semiconductor device with metal die attach to substrate with multi-size cavity |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1222252A (zh) * | 1996-04-18 | 1999-07-07 | 德塞拉股份有限公司 | 制造半导体封装的方法 |
US20030143776A1 (en) * | 2002-01-31 | 2003-07-31 | Serafin Pedron | Method of manufacturing an encapsulated integrated circuit package |
CN1601772A (zh) * | 2004-09-22 | 2005-03-30 | 邹庆福 | 阵列式发光二极管的模组化结构及其封装方法 |
CN102376852A (zh) * | 2010-08-13 | 2012-03-14 | 金龙国际公司 | 发光二极管封装的基板结构及其制造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19856331B4 (de) * | 1998-12-07 | 2009-01-02 | Robert Bosch Gmbh | Verfahren zur Eingehäusung elektronischer Bauelemente |
DE10238523B4 (de) * | 2002-08-22 | 2014-10-02 | Epcos Ag | Verkapseltes elektronisches Bauelement und Verfahren zur Herstellung |
TW567566B (en) * | 2002-10-25 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Window-type ball grid array semiconductor package with lead frame as chip carrier and method for fabricating the same |
US20060238274A1 (en) * | 2005-04-22 | 2006-10-26 | Ycl Electronics Co., Ltd. | Surface acoustic wave device |
TWI276208B (en) * | 2005-10-21 | 2007-03-11 | Advanced Semiconductor Eng | Semiconductor package having an optical device and the method of making the same |
US8310060B1 (en) * | 2006-04-28 | 2012-11-13 | Utac Thai Limited | Lead frame land grid array |
US20090127677A1 (en) * | 2007-11-21 | 2009-05-21 | Gomez Jocel P | Multi-Terminal Package Assembly For Semiconductor Devices |
US20100087024A1 (en) * | 2008-06-19 | 2010-04-08 | Noureddine Hawat | Device cavity organic package structures and methods of manufacturing same |
US9502612B2 (en) * | 2009-09-20 | 2016-11-22 | Viagan Ltd. | Light emitting diode package with enhanced heat conduction |
US8202786B2 (en) | 2010-07-15 | 2012-06-19 | Infineon Technologies Austria Ag | Method for manufacturing semiconductor devices having a glass substrate |
US8865522B2 (en) | 2010-07-15 | 2014-10-21 | Infineon Technologies Austria Ag | Method for manufacturing semiconductor devices having a glass substrate |
US8552829B2 (en) | 2010-11-19 | 2013-10-08 | Infineon Technologies Austria Ag | Transformer device and method for manufacturing a transformer device |
JP5558595B2 (ja) * | 2012-03-14 | 2014-07-23 | 株式会社東芝 | 半導体装置及び半導体装置の製造方法 |
JP6166525B2 (ja) * | 2012-06-18 | 2017-07-19 | 太陽誘電株式会社 | 電子部品の製造方法 |
US8956918B2 (en) * | 2012-12-20 | 2015-02-17 | Infineon Technologies Ag | Method of manufacturing a chip arrangement comprising disposing a metal structure over a carrier |
US9117801B2 (en) | 2013-05-15 | 2015-08-25 | Infineon Technologies Ag | Semiconductor devices having a glass substrate, and method for manufacturing thereof |
-
2014
- 2014-02-26 US US14/190,952 patent/US9847235B2/en active Active
-
2015
- 2015-02-25 CN CN201510087951.1A patent/CN104867898B/zh active Active
- 2015-02-25 DE DE102015102718.6A patent/DE102015102718B4/de active Active
-
2017
- 2017-10-26 US US15/794,155 patent/US10748787B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1222252A (zh) * | 1996-04-18 | 1999-07-07 | 德塞拉股份有限公司 | 制造半导体封装的方法 |
US20030143776A1 (en) * | 2002-01-31 | 2003-07-31 | Serafin Pedron | Method of manufacturing an encapsulated integrated circuit package |
CN1601772A (zh) * | 2004-09-22 | 2005-03-30 | 邹庆福 | 阵列式发光二极管的模组化结构及其封装方法 |
CN102376852A (zh) * | 2010-08-13 | 2012-03-14 | 金龙国际公司 | 发光二极管封装的基板结构及其制造方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108695177A (zh) * | 2017-03-29 | 2018-10-23 | 丰田自动车株式会社 | 半导体装置及其制造方法 |
CN108695177B (zh) * | 2017-03-29 | 2021-11-02 | 株式会社电装 | 半导体装置及其制造方法 |
CN111081667A (zh) * | 2018-10-19 | 2020-04-28 | 现代自动车株式会社 | 半导体子组件和半导体功率模块 |
CN113257679A (zh) * | 2020-01-28 | 2021-08-13 | 英飞凌科技股份有限公司 | 具有由功率半导体管芯的负载端子接合焊盘形成的可焊接接触焊盘的半导体封装及制造方法 |
CN113257678A (zh) * | 2020-01-28 | 2021-08-13 | 英飞凌科技股份有限公司 | 半导体封装及其制造方法 |
CN113257679B (zh) * | 2020-01-28 | 2024-08-20 | 英飞凌科技股份有限公司 | 具有由功率半导体管芯的负载端子接合焊盘形成的可焊接接触焊盘的半导体封装及制造方法 |
TWI784400B (zh) * | 2020-01-30 | 2022-11-21 | 日商大口電材股份有限公司 | 引線框架 |
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