CN111081667A - 半导体子组件和半导体功率模块 - Google Patents

半导体子组件和半导体功率模块 Download PDF

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CN111081667A
CN111081667A CN201910987632.4A CN201910987632A CN111081667A CN 111081667 A CN111081667 A CN 111081667A CN 201910987632 A CN201910987632 A CN 201910987632A CN 111081667 A CN111081667 A CN 111081667A
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electrode
semiconductor
terminal
chip
electrode terminal
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日吉道明
朴星珉
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Hyundai Motor Co
Kia Corp
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Hyundai Motor Co
Kia Motors Corp
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Publication of CN111081667A publication Critical patent/CN111081667A/zh
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Abstract

本发明涉及半导体子组件和半导体功率模块，其能够具有减小的芯片厚度和减小的热阻。该半导体子组件包括单个或多个半导体芯片，所述半导体芯片具有形成在其下表面上的第一电极，形成在其上表面上的第二电极以及形成在其上表面的一个端部处的多个芯片侧信号电极焊垫。半导体芯片嵌入在嵌入式结构中，并且多个扩展信号电极焊垫相应地连接至芯片侧信号电极焊垫。当在平面上观察时，扩展信号电极焊垫以大于芯片侧信号电极焊垫的尺寸形成在嵌入式基板上。

Description

半导体子组件和半导体功率模块
技术领域
本发明涉及一种半导体子组件和半导体功率模块，更具体地，涉及一种能够最小化和减小热阻的半导体子组件以及具有该半导体子组件的半导体功率模块。
背景技术
半导体功率模块的散热性能正在得到改善，此外，发展趋势是减小安装的半导体芯片。例如，在双侧冷却封装件中，可以利用大约单侧冷却封装件一半的尺寸来获得等效的冷却性能。另外，在作为功率半导体示例的碳化硅(SiC)功率器件中，期望可以利用尺寸为传统芯片1/5的芯片来获得等效的性能。同时，在双侧冷却封装件中，具有信号端子的连接结构成为减小尺寸的障碍。随着芯片尺寸的减小，芯片表面的信号电极焊垫也减小，这使得用于连接的导线更小是合理的，但是机械强度和可靠性存在问题。
一种开发的技术公开了一种能够双侧冷却的半导体功率模块的内部结构。接合布线用于连接至信号端子。考虑到布线空间，布线键合(wire bonding)连接需要确保半导体封装件内部的绝缘空间。
然而，布线键合连接具有大量的组装操作。代替焊线连接，存在使用球栅阵列(ball grid array，BGA)的手动连接的示例，但是在双侧冷却封装件的情况下，封装件和芯片的位置匹配精度较低。因此，优选这样的一种半导体芯片的封装结构，其可以代替布线键合连接，对应于减小尺寸的信号电极焊垫，并减小热阻。
图6为根据现有技术的功率半导体1的封装的传统示例。具体地，功率半导体1是绝缘栅双极型晶体管(IGBT)。IGBT被称为绝缘栅双极型晶体管，并且用于操作三相交流(AC)电机等。IGBT具有集电极C、发射极E和栅极G三个端子。图1A所示的IGBT的半导体芯片1a以平面图(俯视图)示出，发射极E的第二电极3(3b)在其表面上呈矩形。集电极C的第一电极3(3a)在背面的下表面上。IGBT的半导体芯片1a具有例如五个芯片侧信号电极焊垫2。这包括栅极G的控制线、在其中制备的温度传感器(例如，二极管)的输入/输出线等。
如图6所示，IGBT的半导体功率模块200封装在封装件9中，并且具有IGBT的半导体芯片1a、直接铜键合(direct copper bonding，DCB)基板4、4'、多个外部信号端子8、间隔件7、第一外部电极端子22和第二外部电极端子23。IGBT的半导体芯片1a设置在其中心，导电间隔件7焊接在半导体芯片1a上，DCB基板4'连接至导电间隔件7。DCB基板4也连接至IGBT的半导体芯片1a的下侧。
DCB基板具有将铜板4b直接接合到陶瓷板4a的上下侧的每侧的三层结构。IGBT的半导体芯片1a的上下两侧分别接合为使半导体芯片1a插置在两个DCB基板4、4'(例如，第一直接铜键合基板和第二直接铜键合基板)之间。从其上部的DCB基板4'引出第二外部电极端子23，从其下部的DCB基板4引出第一外部电极端子22。从图6的右侧可以看出，外部信号端子8被引出到外部。外部信号端子8通过布线键合连接6连接至IGBT的半导体芯片1a。在这样的传统结构中，由于间隔件7的热阻，温度可能升高，并且还需要用于布线键合连接的空间，因此半导体功率模块200难以具有较薄的厚度。
公开于本部分的上述信息仅仅用于加深对本发明背景的理解，因此其可以包含的信息并不构成在本国已为本领域技术人员所公知的现有技术。
发明内容
本发明提供了一种半导体子组件和半导体功率模块，其能够具有减小的芯片厚度和减小的热阻。
根据本发明示例性实施方案的半导体子组件可以包括：单个或多个半导体芯片1a、嵌入式基板12以及多个扩展信号电极焊垫11，所述单个或多个半导体芯片1a具有形成在其下表面上的第一电极3a、形成在其上表面上的第二电极3b以及形成在其上表面的一端处的多个芯片侧信号电极焊垫2；所述嵌入式基板12中嵌入有半导体芯片1a；所述多个扩展信号电极焊垫11相应地连接至芯片侧信号电极焊垫2，当在平面上观察时，扩展信号电极焊垫11可以以大于芯片侧信号电极焊垫2的尺寸形成在嵌入式基板12上。
另外，在根据本发明示例性实施方案的半导体子组件中，用于容纳半导体芯片的开口19可以形成在嵌入式基板12中；第一电极3a可以电连接且热连接至安装在嵌入式基板12的整个下表面上的第一电极焊垫13；第二电极3b可以暴露于半导体芯片1a的上表面；芯片侧信号电极焊垫2可以通过安装在嵌入式基板12的上表面的连接布线连接至扩展信号电极焊垫11；第一电极焊垫13和扩展信号电极焊垫11可以通过金属电镀形成；半导体芯片1a的多个芯片侧信号电极焊垫2中的至少一对相邻的芯片侧信号电极焊垫2可以具有连接至包括在形成于嵌入式基板12上的第一布线层15中的连接布线17的第一侧、连接至包括在形成于第一布线层15上的第二布线层16中的连接布线18的第二侧，第一布线层和第二布线层之间插置有绝缘层，包括在第一布线层15中的连接布线17和包括在第二布线层16中的连接布线18形成为具有在竖直方向上彼此重叠的区域。
在根据本发明示例性实施方案的半导体子组件中，当多个半导体芯片1a并联连接时，半导体芯片1a的芯片侧信号电极焊垫2的对应信号电极可以彼此连接，并且可以连接至对应的扩展信号电极焊垫11。
此外，根据本发明示例性实施方案的半导体功率模块是其中利用了半导体子组件100的半导体功率模块，半导体子组件的第一电极焊垫13可以连接至安装在第一电极焊垫13下侧的DCB基板4的第一电极端子20；第一外部电极端子22可以连接至第一电极端子20；半导体芯片1a的第二电极3b可以连接至安装在第二电极3b上侧的DCB基板4'的第二电极端子21；第二外部电极端子23可以连接至第二电极端子21；连接至半导体芯片1a的芯片侧信号电极焊垫2的多个扩展信号电极焊垫11可以连接至多个外部信号端子8。当在平面上观察时，可以通过在第二电极端子21与扩展信号电极焊垫11之间绝缘以及在第二电极端子21与外部信号端子8之间绝缘来确保绝缘距离。
另外，在根据本发明示例性实施方案的半导体功率模块中，第一电极焊垫13与第一电极端子20的连接、第二电极3b与第二电极端子21的连接以及扩展信号电极焊垫11与外部信号端子8的连接可以通过焊接进行。
根据本发明的半导体子组件：
(a)可以在嵌入有半导体芯片1a的嵌入式基板12上形成具有更大尺寸的扩展信号电极焊垫11，并连接扩展信号电极焊垫11和半导体芯片1a的芯片侧信号电极焊垫2，从而在不依赖于布线键合连接的情况下，将信号外部端子连接至扩展信号电极焊垫11。
(b)可以省略布线键合连接，从而使芯片具有较薄的厚度。
(c)另外，可以省略间隔件，从而将两次焊接过程减少到一次。
(d)另外，可以省略间隔件，从而通过减薄使热阻改善约20％。
(e)另外，可以省略间隔件，从而使第一外部电极端子22和第二外部电极端子23彼此接近以实现低电感。
另外，可以在嵌入式基板12的整个下表面上制备金属镀层的第一电极焊垫13，从而通过焊接将半导体芯片1a的第一电极3a良好地接合到第一电极焊垫13的第一侧表面，并且将DCB基板4的第一电极端子20接合在第二侧表面上。半导体芯片1a的第二电极3b可以在其中插置金属镀层的第二电极焊垫14，从而通过焊接将其良好地接合到DCB基板4'的第一电极端子20。
芯片侧信号电极焊垫2和扩展信号电极焊垫11可以通过两层连接布线连接，并且第一层连接布线和第二层连接布线可以在竖直方向上彼此重叠，从而减小电感。换句话说，与信号端子的栅极/源极布线对应的两条线可以平行且在竖直方向上彼此重叠，从而减小电感。
此外，在并联连接的情况下，例如，可以将子组件中的对应信号电极彼此连接，从而使用一个G端子操作两个SiC-MOSFET。可以极大地缩短半导体芯片之间的信号电极。
根据本发明的半导体功率模块，可以通过在第二电极端子21与扩展信号电极焊垫11之间绝缘以及在第二电极端子21与外部信号端子8之间绝缘来确保绝缘距离，从而提供了用于抑制对第二电极端子21的信号端子影响的绝缘空间。另外，可以省略诸如布线键合之类的沿高度方向的空间，从而减小半导体功率模块的厚度。
此外，可以通过焊接进行第一电极焊垫13和第一电极端子20的连接、第二电极3b和第二电极端子21的连接以及扩展信号电极焊垫11和外部信号端子8的连接，从而提高可靠性。
附图说明
现在将参考说明附图的示例性实施方案来详细描述本发明的上述和其它特征，下文给出的附图仅用于说明，因此对本发明是非限制性的，其中：
图1A至图1D为示出根据本发明示例性实施方案的半导体功率模块的示意图，图1D为IGBT的符号；
图2A和图2B为示出根据本发明示例性实施方案的半导体子组件的示意图；
图3为示出根据本发明示例性实施方案的用于温度分析的半导体功率模块模型的示意图；
图4A和图4B为示出根据本发明示例性实施方案的半导体功率模块和传统的半导体功率模块的温度分布的比较图；
图5A和图5B为示出在根据本发明示例性实施方案的一个子组件上安装多个功率半导体的示例的示意图；以及
图6为示出根据现有技术的传统的功率半导体的封装的示例的示意图。
应当理解，附图不一定是按照比例绘制，而是呈现各种特征的简化表示，以对本发明的基本原理进行说明。本文所公开的本发明的具体设计特征(包括例如，具体尺寸、方向、位置和形状)将部分地由具体目标应用和使用的环境来确定。在这些图形中，贯穿附图的多幅图形，附图标记表示本发明的相同的或等同的部分。
具体实施方式
应当理解，本文中所使用的术语“车辆”或“车辆的”或其它类似术语一般包括机动车辆，例如包括运动型多用途车辆(SUV)、大客车、大货车、各种商用车辆的乘用汽车，包括各种舟艇、船舶的船只，航空器等等，并且包括混合动力车辆、电动车辆、插电式混合动力电动车辆、氢动力车辆以及其它替代性燃料车辆(例如源于非石油能源的燃料)。正如本文所提到的，混合动力车辆是具有两种或更多动力源的车辆，例如汽油动力和电力动力两者的车辆。
本文所使用的术语仅为了描述特定实施方案的目的，并非旨在限制本发明。正如本文所使用的，单数形式“一”、“一个”和“所述”旨在也包括复数形式，除非上下文另有清楚的说明。还将进一步理解，当在本说明书中使用术语“包括”和/或“包括了”时，指明存在所述特征、数值、步骤、操作、元件和/或组件，但是不排除存在或加入一种或多种其它的特征、数值、步骤、操作、元件、组件和/或其群组。正如本文所使用的，术语“和/或”包括一种或多种相关列举项目的任何和所有组合。
除非特别声明或者从上下文显而易见的，本文所使用的术语“大约”被理解为在本领域的正常公差范围内，例如在平均2个标准差内。“大约”可被理解为在指定值的10％、9％、8％、7％、6％、5％、4％、3％、2％、1％、0.5％、0.1％、0.05％或0.01％之内。除非从上下文清楚的知道，本文提供的所有数值由术语“大约”修饰。
下面将参考所附附图对根据本发明的半导体子组件和半导体功率模块进行描述。
图1A至图1D为示出根据本发明的半导体功率模块200的示意图。具体地，功率半导体1是IGBT的半导体芯片1a，并且IGBT的符号如图1D所示。图1A是平面图，第二电极3b可以形成在半导体芯片1a的上表面，第一电极3a可以形成在其背面。五个芯片侧信号电极焊垫2可以形成在半导体芯片1a的右侧。具体地，其中有栅极G的控制线或者制备的两个温度传感器元件的输入/输出线。
图1B是半导体子组件100的平面图。如图1B所示，可以将用于嵌入半导体芯片1a的开口19安装在嵌入式基板12中。在将半导体芯片1a嵌入其中后，可以通过金属镀层在嵌入式基板12的底部形成第一电极焊垫13。因此，可以将半导体芯片1a背面的第一电极3a和第一电极焊垫13电连接地且热连接地接合。类似地，可以通过金属镀层形成嵌入式基板12的五个芯片侧信号电极焊垫2。
图1C为示出半导体功率模块200的内部结构的示意图，在金属电镀之后，可以安装半导体子组件100以形成半导体功率模块200。可以通过焊接将半导体子组件100的第一电极焊垫13连接至安装在其下部的DCB基板4的第一电极端子20。另外，第一电极端子20具有预先连接在其一个端部处的第一外部电极端子22。
可以通过焊接10将半导体芯片1a的第二电极3b，即形成在第二电极3b上的第二电极焊垫14连接至安装在其上部的DCB基板4'的第二电极端子21。另外，第二电极端子21可以包括预先连接在其一个端部处的第二外部电极端子23。结果，将半导体芯片1a的下表面上的第一电极3a引出至半导体功率模块200的第一外部电极端子22，将半导体芯片1a的上表面上的第二电极3b引出至半导体功率模块200的第二外部电极端子23。
可以通过焊接10将扩展信号电极焊垫11连接至外部信号端子8。结果，可以通过插置扩展信号电极焊垫11将半导体芯片1a的五个芯片侧信号电极焊垫2引出到半导体功率模块200的第二外部电极端子23。另外，可以通过在第二电极端子21与扩展信号电极焊垫11之间绝缘以及在第二电极端子21与外部信号端子8之间绝缘来确保绝缘距离。
图2A和图2B为示出根据本发明的半导体子组件100的示意图。图2A为半导体子组件100的平面图，图2B为沿图2A的线A-A截取的截面图。半导体芯片1a的芯片侧信号电极焊垫2和扩展信号电极焊垫11之间的连接可以在两层金属镀层的布线层中进行。该布线层可以包括第一布线层15和第二布线层16。
如图2A所示，与半导体芯片1a间隔开的三个右侧扩展信号电极焊垫11可以形成在其下部的第一布线层15上，与半导体芯片1a相邻的两个左侧扩展信号电极焊垫11可以形成在其上部的第二布线层16上。芯片侧信号电极焊垫2和三个右侧扩展信号电极焊垫11的连接可以通过其下部的第一布线层15的连接布线17来进行。芯片侧信号电极焊垫2和两个左侧扩展信号电极焊垫11的连接可以通过其上部的第二布线层16的连接布线18来进行。这里，包括在第一布线层15中的连接布线17可以形成为具有较宽的宽度(例如，大约1mm)，并且具有与包括在第二布线层16中的连接布线18在竖直方向上重叠的区域。结果，当将电流的方向施加至相反方向的两条布线时，可以减小电感。
如图2B所示，第一电极3a可以通过安装在嵌入式基板12的整个下表面上的金属镀层而电连接地且热连接地连接至第一电极焊垫13。半导体芯片1a的第二电极3b可以暴露在半导体芯片1a的上表面上(具有约250微米的厚度)，金属镀层的第二电极焊垫14可以在第二电极3b的表面上薄薄地形成。高热阻高绝缘树脂24可以用于嵌入式基板12(具有约150微米的厚度)。
图3为示出根据本发明的用于温度分析的半导体功率模块200的模型的示意图。半导体芯片1a可以嵌入半导体子组件100中，并且可以由在竖直方向上插置在陶瓷DCB基板4和4'(例如，第一和第二)之间的结构组成。L1和L2是电源层或信号层。
图4A和图4B为示出根据本发明的半导体功率模块200和传统的半导体功率模块的温度分布的比较图。另外，半导体芯片的尺寸为大约12mm×12mm的正方形，并且进行了双侧冷却。
在图4A和图4B中，比较了在施加50W时的芯片温度Rth。如图4A所示，在传统结构中，Rth计算为0.1℃/W，如图4B所示，在本发明的图3所示的结构中，Rth计算为0.08℃/W。这些图表明热阻可以改善约20％。当50W乘以Rth时，在传统结构中为5℃，在本发明的结构中为4℃，因此，可以将温度降低约1℃。
图5A和图5B为示出在一个子组件上安装多个功率半导体的示例的示意图。SiC-MOSFET当前约为5mm×5mm，并且SiC-SBD也是一样。如图5A和图5B所示，由于与IGBT相比，SiC-MOSFET尺寸小且速度高，而每个芯片的电流容量小，所以可以在并联电路中布置多个芯片，从而增加电流容量。在该并联电路中，二极管和晶体管并联连接，使得连接至S端子和D端子的第一电极焊垫13和第二电极焊垫14可以共用。另外，两个G端子还可以将第一布线层15的对应的连接布线17彼此连接，从而共用一个扩展信号电极焊垫11。
本发明非常适合作为紧凑且可以减小热阻的半导体子组件以及安装有该半导体子组件的半导体功率模块。

Claims (9)

1.一种半导体子组件，其包括：
单个或多个半导体芯片，所述单个或多个半导体芯片具有形成在其下表面上的第一电极、形成在其上表面上的第二电极以及形成在其上表面的一个端部处的多个芯片侧信号电极焊垫；
嵌入式基板，在所述嵌入式基板中嵌入有所述半导体芯片；以及
多个扩展信号电极焊垫，所述多个扩展信号电极焊垫相应地连接至芯片侧信号电极焊垫；
其中，当在平面上观察时，扩展信号电极焊垫以大于芯片侧信号电极焊垫的尺寸形成在嵌入式基板上。
2.根据权利要求1所述的半导体子组件，其中，
用于容纳半导体芯片的开口形成在嵌入式基板中；
第一电极电连接地且热连接地连接至安装在嵌入式基板的整个下表面上的第一电极焊垫，第二电极暴露于半导体芯片的上表面；
芯片侧信号电极焊垫通过安装在嵌入式基板的上表面上的连接布线连接至扩展信号电极焊垫；
第一电极焊垫和扩展信号电极焊垫通过金属电镀形成；
半导体芯片的多个芯片侧信号电极焊垫中的至少一对相邻的芯片侧信号电极焊垫具有连接至包括在形成于嵌入式基板上的第一布线层中的连接布线的第一侧、连接至包括在形成于第一布线层上的第二布线层中的连接布线的第二侧，第一布线层和第二布线层之间插置有绝缘层，包括在第一布线层中的连接布线和包括在第二布线层中的连接布线形成为具有在竖直方向上彼此重叠的区域。
3.根据权利要求1所述的半导体子组件，其中插置，当多个半导体芯片并联连接时，第一电极和第二电极是共用的。
4.一种半导体功率模块，其具有权利要求1所述的半导体子组件，其中：
半导体子组件的第一电极焊垫连接至安装在第一电极焊垫下侧的第一直接铜键合基板的第一电极端子；
第一外部电极端子连接至第一电极端子；
半导体芯片的第二电极连接至安装在第二电极上侧的第二直接铜键合基板的第二电极端子；
第二外部电极端子连接至第二电极端子；
连接至半导体芯片的芯片侧信号电极焊垫的多个扩展信号电极焊垫连接至多个外部信号端子；
当在平面上观察时，通过在第二电极端子与扩展信号电极焊垫之间绝缘以及在第二电极端子与外部信号端子之间绝缘来确保绝缘距离。
5.根据权利要求4所述的半导体功率模块，其中，第一电极焊垫与第一电极端子的连接、第二电极与第二电极端子的连接以及扩展信号电极焊垫与外部信号端子的连接均通过焊接进行。
6.一种半导体功率模块，其具有权利要求2所述的半导体子组件，其中：
半导体子组件的第一电极焊垫连接至安装在第一电极焊垫下侧的第一直接铜键合基板的第一电极端子；
第一外部电极端子连接至第一电极端子；
半导体芯片的第二电极连接至安装在第二电极上侧的第二直接铜键合基板的第二电极端子；
第二外部电极端子连接至第二电极端子；
连接至半导体芯片的芯片侧信号电极焊垫的多个扩展信号电极焊垫连接至多个外部信号端子；
当在平面上观察时，通过在第二电极端子与扩展信号电极焊垫之间绝缘以及在第二电极端子与外部信号端子之间绝缘来确保绝缘距离。
7.根据权利要求6所述的半导体功率模块，其中，第一电极焊垫与第一电极端子的连接、第二电极与第二电极端子的连接以及扩展信号电极焊垫与外部信号端子的连接均通过焊接进行。
8.一种半导体功率模块，其具有权利要求3所述的半导体子组件，其中：
半导体子组件的第一电极焊垫连接至安装在第一电极焊垫下侧的第一直接铜键合基板的第一电极端子；
第一外部电极端子连接至第一电极端子；
半导体芯片的第二电极连接至安装在第二电极上侧的第二直接铜键合基板的第二电极端子；
第二外部电极端子连接至第二电极端子；
连接至半导体芯片的芯片侧信号电极焊垫的多个扩展信号电极焊垫连接至多个外部信号端子；
当在平面上观察时，通过在第二电极端子与扩展信号电极焊垫之间绝缘以及在第二电极端子与外部信号端子之间绝缘来确保绝缘距离。
9.根据权利要求8所述的半导体功率模块，其中，第一电极焊垫与第一电极端子的连接、第二电极与第二电极端子的连接以及扩展信号电极焊垫与外部信号端子的连接均通过焊接进行。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116847534A (zh) * 2022-05-19 2023-10-03 上海沛塬电子有限公司 一种电源变换器、内埋集成器件单元、高散热高频功率模组及其制作方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110178202B (zh) * 2017-01-13 2023-10-27 三菱电机株式会社 半导体装置及其制造方法
JP7176397B2 (ja) * 2018-12-21 2022-11-22 株式会社デンソー 半導体装置とその製造方法
KR20240149253A (ko) * 2023-04-05 2024-10-14 주식회사 엘엑스세미콘 전력반도체 모듈과 이를 포함하는 전력변환 장치 및 전력반도체 모듈의 제조방법

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162246A (ja) * 1995-12-08 1997-06-20 Hitachi Cable Ltd Ｔａｂテープの接続構造及び接続方法
TW200824071A (en) * 2006-11-16 2008-06-01 Nan Ya Printed Circuit Board Corp Embedded chip package with improved heat dissipation performance and method of making the same
WO2011077781A1 (ja) * 2009-12-21 2011-06-30 株式会社日立製作所 半導体装置及びその製造方法
US20130020694A1 (en) * 2011-07-19 2013-01-24 Zhenxian Liang Power module packaging with double sided planar interconnection and heat exchangers
CN103515260A (zh) * 2012-06-27 2014-01-15 英飞凌科技奥地利有限公司 封装内封装及其形成方法
CN104867898A (zh) * 2014-02-26 2015-08-26 英飞凌科技股份有限公司 具有镀覆的引线框架的半导体器件及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009125779A1 (ja) * 2008-04-09 2009-10-15 富士電機デバイステクノロジー株式会社 半導体装置及び半導体装置の製造方法
US8569892B2 (en) * 2008-10-10 2013-10-29 Nec Corporation Semiconductor device and manufacturing method thereof
CN102484109B (zh) * 2009-08-03 2014-12-10 株式会社安川电机 电力变换装置
JP5381926B2 (ja) * 2010-07-27 2014-01-08 株式会社デンソー 半導体装置
JP6344215B2 (ja) 2014-11-21 2018-06-20 株式会社デンソー 半導体装置及びパワーモジュール
JP6364543B2 (ja) * 2015-03-30 2018-07-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2018107481A (ja) * 2018-04-09 2018-07-05 ローム株式会社 パワーモジュール半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162246A (ja) * 1995-12-08 1997-06-20 Hitachi Cable Ltd Ｔａｂテープの接続構造及び接続方法
TW200824071A (en) * 2006-11-16 2008-06-01 Nan Ya Printed Circuit Board Corp Embedded chip package with improved heat dissipation performance and method of making the same
WO2011077781A1 (ja) * 2009-12-21 2011-06-30 株式会社日立製作所 半導体装置及びその製造方法
US20130020694A1 (en) * 2011-07-19 2013-01-24 Zhenxian Liang Power module packaging with double sided planar interconnection and heat exchangers
CN103515260A (zh) * 2012-06-27 2014-01-15 英飞凌科技奥地利有限公司 封装内封装及其形成方法
CN104867898A (zh) * 2014-02-26 2015-08-26 英飞凌科技股份有限公司 具有镀覆的引线框架的半导体器件及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116847534A (zh) * 2022-05-19 2023-10-03 上海沛塬电子有限公司 一种电源变换器、内埋集成器件单元、高散热高频功率模组及其制作方法
WO2023221999A1 (zh) * 2022-05-19 2023-11-23 上海沛塬电子有限公司 一种电源变换器、内埋集成器件单元、高散热高频功率模组及其制作方法

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