CN110178202B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN110178202B
CN110178202B CN201780082643.7A CN201780082643A CN110178202B CN 110178202 B CN110178202 B CN 110178202B CN 201780082643 A CN201780082643 A CN 201780082643A CN 110178202 B CN110178202 B CN 110178202B
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semiconductor device
electrode
plating
gate wiring
electrodes
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CN110178202A (zh
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中田洋辅
赤尾真哉
原田健司
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

半导体衬底(1)具有彼此相对的表面以及背面。栅极配线(2)以及第1及第2表面电极(3、4)形成于半导体衬底(1)的表面。第1及第2表面电极(3、4)通过栅极配线(2)而彼此分割开。绝缘膜(7)覆盖栅极配线(2)。电极层(8)跨过栅极配线(2)而形成于绝缘膜(7)以及第1及第2表面电极(3、4)之上。背面电极(9)形成于半导体衬底(1)的背面。第1镀敷电极(10)形成于电极层(8)之上。第2镀敷电极(11)形成于背面电极(9)之上。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
公开了在半导体衬底的两面通过镀敷法而同时形成电极的半导体装置的制造方法(例如，参照专利文献1)。另外，为了实现均匀的动作，将半导体衬底的表面的电极通过栅极配线分切为梳齿状(例如，参照专利文献2)。另一方面，通常，半导体衬底的背面的电极呈与半导体衬底相同的形状。
专利文献1：日本特开2007-5368号公报
专利文献2：日本特开2003-92406号公报
发明内容
以往的半导体装置在半导体衬底的表面和背面，电极的形状不同。因此，如果通过湿式镀敷法而在半导体衬底的两面形成相同材质的镀敷电极，则在表面和背面，镀敷电极的膜应力产生差异。其结果，存在以下问题，即，半导体衬底以向表面侧凸出的方式翘曲，半导体装置的组装时的成品率下降，组装后的热阻不均匀等。
本发明就是为了解决上述这样的课题而提出的，其目的在于得到能够改善组装时的成品率和组装后的热阻的均匀性的半导体装置及其制造方法。
本发明涉及的半导体装置的特征在于，具备：半导体衬底，其具有彼此相对的表面以及背面；栅极配线，其形成于所述半导体衬底的所述表面；第1及第2表面电极，它们形成于所述半导体衬底的所述表面，通过所述栅极配线而彼此分割开；绝缘膜，其覆盖所述栅极配线；电极层，其跨过所述栅极配线而形成于所述绝缘膜以及所述第1及第2表面电极之上；第1镀敷电极，其形成于所述电极层之上；背面电极，其形成于所述半导体衬底的所述背面；以及第2镀敷电极，其形成于所述背面电极之上。
发明的效果
在本发明中，在通过栅极配线而彼此分割开的第1及第2表面电极之上形成有电极层，分别在电极层和背面电极之上形成有第1及第2镀敷电极。由此，半导体衬底的两面的电极形状接近，因此两面的电极的膜应力差减小，半导体衬底的翘曲减小。由此，能够改善半导体装置的组装时的成品率和组装后的热阻的均匀性。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。
图2是沿着图1的I-II的剖面图。
图3是表示使用了本发明的实施方式1涉及的半导体装置的半导体封装件的俯视图。
图4是沿着图3的I-II的剖面图。
图5是表示对比例涉及的半导体装置的俯视图。
图6是沿着图5的I-II的剖面图。
图7是表示本发明的实施方式2涉及的半导体装置的剖面图。
具体实施方式
参照附图，对本发明的实施方式涉及的半导体装置及其制造方法进行说明。对相同或相应的结构要素标注相同的标号，有时省略重复说明。
实施方式1.
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。图2是沿着图1的I-II的剖面图。该半导体装置是IGBT或者MOSFET等电力用半导体装置。
半导体衬底1具有彼此相对的表面以及背面。栅极配线2以及表面电极3、4形成于半导体衬底1的表面。为了使半导体装置均匀地动作，表面电极3、4由栅极配线2彼此分割开，局部地连接。栅极配线2具有与控制用导线连接的焊盘5。
为了保持半导体装置的耐压，在半导体衬底1的终端区域形成有多个终端构造配线6。终端构造配线6例如是保护环等耐压保持构造，由多根配线构成。栅极配线2、表面电极3、4、终端构造配线6例如是由以铝为主要成分的材料通过溅射法等气相沉积法而统一地成膜，通过照相制版工序和蚀刻工序而分别分切，图案化为所期望的形状。
绝缘膜7覆盖栅极配线2。绝缘膜7例如能够由以硅氮化膜为主要成分的材料形成。绝缘膜7例如是在堆叠了硅氮化膜，经过照相制版工序和蚀刻工序，从而图案化为所期望的形状。电极层8跨过栅极配线2而形成于绝缘膜7以及表面电极3、4之上。
背面电极9形成于半导体衬底1的背面。背面电极9与半导体衬底1的外形同尺寸。镀敷电极10形成于电极层8之上，镀敷电极11形成于背面电极9之上。镀敷电极10、11的厚度和材质彼此相同。
图3是表示使用了本发明的实施方式1涉及的半导体装置的半导体封装件的俯视图。图4是沿着图3的I-II的剖面图。引线框12通过接合材料13而与镀敷电极10接合，与镀敷电极10电连接、机械连接。导体基板14通过接合材料15而与镀敷电极11接合，与镀敷电极11电连接、机械连接。接合材料13、15例如是以锡为主要成分的材料的焊料，由此能够容易地接合。焊盘5与外部信号端子通过例如以铝为主要成分的材料的导线而连接。
接合材料13形成于避开了栅极配线2的区域。因此，能够防止在冷热循环时来自接合材料13的应力施加至栅极配线2，栅极配线2受到损伤而与周边电极短路这一情况。另一方面，为了尽可能大，半导体衬底1的背面的接合材料15是以与半导体衬底1相同的形状而形成的。由此，能够将来自半导体装置的发热高效地向导体基板14散热。
包覆膜16包覆镀敷电极10的焊料接合区域的外周。因此，能够抑制在镀敷电极10的上表面焊料超出预想地润湿扩散。其结果，能够防止与其它部件之间的短路，提高成品率和可靠性。包覆膜16只要是包含聚酰亚胺的材料，则能够可靠地阻碍焊料润湿。包覆膜16能够通过在镀敷电极10之上将聚酰亚胺前驱体溶液描绘涂敷为所期望的形状，然后进行固化而形成。
封装材料17包覆半导体衬底1、接合材料13、15、引线框12以及导体基板14等的至少一部分。由此，能够降低电气损耗，实现可靠性高的半导体装置。封装材料17例如是灌封树脂或者传递模塑树脂。
接着，对本实施方式涉及的半导体装置的制造方法进行说明。在半导体衬底1的表面形成栅极配线2以及通过栅极配线2而彼此分割开的表面电极3、4。形成覆盖栅极配线2的绝缘膜7。跨过栅极配线2而在绝缘膜7以及表面电极3、4之上形成电极层8。在半导体衬底1的背面形成背面电极9。
通过湿式镀敷法而分别在电极层8之上形成镀敷电极10，在栅极配线2的开口部分形成焊盘5，在背面电极9形成镀敷电极11。通过将它们同时形成，从而能够抑制镀敷工序的工艺成本。另外，由于同时形成，因此镀敷电极10、11与焊盘5的厚度和材质彼此相同。
镀敷电极10、11和焊盘5例如由以镍为主要成分的材料构成，能够通过使用了锌酸盐处理的工艺而形成。由于优选在焊料接合之后还残存有镀敷电极10、11，因此优选镀敷电极10、11的厚度大于或等于1μm。为了抑制镀敷工序的工艺成本增加，并且确保切割工序的成品率，优选镀敷电极10、11的厚度小于或等于10μm。
电极层8例如能够由以铝为主要成分的材料形成。在将栅极配线2和电极层8由铝等相同的材料形成的情况下，为了防止栅极配线2的焊盘5被蚀刻，优选在对铝进行蚀刻的工艺以外将电极层8图案化。例如，越过在电极层形成区域具有开口的有机抗蚀膜，通过溅射法等而进行电极层8的气相沉积，之后，喷出对有机抗蚀层进行溶解的剥离液，从而通过仅将有机抗蚀层之上的电极层8选择性地去除的剥离法而将电极层8图案化。或者，也可以越过在电极层形成区域具有开口的掩模，将电极层8通过溅射法等进行气相沉积，由此将电极层8图案化。由此，能够容易地图案化，能够降低对表面电极3、4的损伤。
另外，通过将聚酰亚胺前驱体溶液向镀敷电极10之上喷出、进行描绘而形成图案，进行固化，由此形成包覆膜16。由此，无需照相制版即可容易地将包覆膜16图案化。
接着，与对比例进行比较，对本实施方式的效果进行说明。图5是表示对比例涉及的半导体装置的俯视图。图6是沿着图5的I-II的剖面图。对比例的半导体衬底1的表面的镀敷电极10a、10b与背面的镀敷电极11的形状不同。因此，存在以下问题，即，半导体衬底1以向表面侧凸出的方式翘曲，半导体装置的组装时的成品率下降，组装后的热阻不均匀等。
另一方面，在本实施方式中，在通过栅极配线2而彼此分割开的表面电极3、4之上形成有电极层8，分别在电极层8和背面电极9之上形成有镀敷电极10、11。由此，半导体衬底1的两面的电极形状接近，因此两面的电极的膜应力差减小，半导体衬底的翘曲减小。由此，能够改善半导体装置的组装时的成品率和组装后的热阻的均匀性。
终端构造配线6通过与表面电极3、4相同的工艺而形成，通过蚀刻等加工工艺而图案化，因此具有与表面电极3、4相同的厚度。因此，如果使表面电极3、4厚膜化，则终端构造配线6也厚膜化。如果终端构造配线6变厚，则从封装材料等受到的应力变大，因此可靠性下降。因而，通过不将电极层8形成于终端区域，从而能够避免终端构造配线6过度地厚膜化。
另外，终端构造配线6负责分担电场，不流过大电流，因此不需要厚膜化而降低电阻值。另一方面，表面电极3、4对应于大电流的通电，缓和由于焊料的膨胀收缩而产生的应力，因此优选尽可能厚膜化。根据本实施方式，能够抑制终端构造配线6的厚度，并且使电极的厚度变厚，因而能够形成可靠性更高的半导体装置。例如设计为，表面电极3、4和终端构造配线6的厚度小于或等于1.5μm，表面电极3、4和电极层8的合计厚度大于或等于3μm。
绝缘膜7还设置在表面电极3、4与电极层8之间。因此，即使在半导体装置受到来自外部的应力的情况下，也能够防止配线裂纹等损伤到达表面电极3、4。
在绝缘膜7设置有多个通孔，穿过多个通孔，表面电极3、4与电极层8机械连接、电连接。另一方面，在栅极配线2的焊盘5之上，在绝缘膜7设置有开口。栅极配线2的其它部分由绝缘膜7包覆，确保了栅极配线2与表面电极3、4之间的绝缘性。
绝缘膜7覆盖多个终端构造配线6，使多个终端构造配线6之间的电场分布均等。即，绝缘膜7是对终端区域进行保护的保护膜延展至动作单元区域而得到的。这样，通过将绝缘膜7与保护膜共通化，从而能够形成绝缘膜7而无需追加加工工艺。
表面电极3、4以及终端构造配线6的厚度比电极层8的厚度薄。由此，能够确保终端构造的可靠性，同时确保对焊料接合性以及导线键合性做贡献的动作单元之上的电极厚度，能够提高可靠性以及生产率。
表面电极3、4以及背面电极9由包含铝的材料形成。因此，能够容易地形成、加工为半导体装置的电极，通电时的电阻也低，能够形成机械上稳定的接合界面。
电极层8由包含铝的材料形成。因此，能够容易地形成镀敷电极10，通电时的电阻也低，能够得到与由包含铝的材料形成的表面电极3、4在机械上稳定的接合界面。另外，由于是与背面电极9相同材质的材料，因此能够通过湿式镀敷法容易地形成镀敷电极10、11。另外，绝缘膜7包含氮化硅。氮化硅作为保护膜而起作用，并且与表面电极3、4的铝相容性也良好，因而能够得到电气以及机械上稳定的构造。
镀敷电极10、11包含镍或者铜，因此容易与焊料接合，能够形成电气及机械上稳定的接合界面。另外，优选在镀敷电极10、11的最表面形成有包含金的材料。由此，在与焊料接合之前，能够防止底层的焊料接合用电极被氧化而使焊料润湿性下降。
另外，也可以将以Ag为主要成分的材料的微粒烧结而将导体基板14与镀敷电极11接合。但是，在将由以Ag为主要成分的材料构成的微粒烧结而接合的情况下，通常对半导体衬底1进行加压而接合。但是，有时由于在半导体衬底1因外压而弯曲时所产生的应力或者与外部夹具之间的摩擦，在半导体衬底1产生损伤。与此相对，在本实施方式中，能够避免半导体衬底1翘曲，因而能够降低加压时在半导体衬底1产生的损伤。
实施方式2.
图6是表示本发明的实施方式2涉及的半导体装置的剖面图。在绝缘膜7之上形成有有机膜18。由此，能够防止由于冷热循环时的应力而使栅极配线2与表面电极3、4或者电极层8短路。
优选有机膜18与绝缘膜7是相同的形状，并且与绝缘膜7重叠。考虑到与照相制版时的光晕(halation)的重合精度，优选重叠量大于或等于10μm。并且，只要有机膜18包含聚酰亚胺，则能够容易地形成、加工为半导体装置的绝缘膜。
此外，半导体衬底1不限于由硅形成，也可以由与硅相比带隙大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或者金刚石。由上述宽带隙半导体衬底形成的半导体装置的耐电压性、容许电流密度高，所以能够小型化。通过使用该小型化的元件，从而能够使组装有该装置的半导体模块也小型化。另外，由于装置的耐热性高，所以能够使散热器的散热鳍片小型化，因此能够进一步将半导体模块小型化。另外，由于元件的电力损耗低且高效，因此能够使半导体模块高效化。
标号的说明
1半导体衬底，2栅极配线，3、4表面电极，5焊盘，6终端构造配线，7绝缘膜，8电极层，9背面电极，10、11镀敷电极，12引线框，13、15接合材料，14导体基板，16包覆膜，17封装材料，18有机膜。

Claims (23)

1.一种半导体装置，其特征在于，具备：
半导体衬底，其具有彼此相对的表面以及背面；
栅极配线，其形成于所述半导体衬底的所述表面；
第1及第2表面电极，它们形成于所述半导体衬底的所述表面，通过所述栅极配线而彼此分割开；
绝缘膜，其覆盖所述栅极配线；
电极层，其跨过所述栅极配线而形成于所述绝缘膜以及所述第1及第2表面电极之上；
背面电极，其形成于所述半导体衬底的所述背面；
第1镀敷电极，其形成于所述电极层之上；
第2镀敷电极，其形成于所述背面电极之上；
引线框，其通过第1接合材料而与所述第1镀敷电极接合；
导体基板，其通过第2接合材料而与所述第2镀敷电极接合；以及
封装材料，其包覆所述半导体衬底、所述引线框以及所述导体基板的至少一部分，
所述第1接合材料形成于避开了所述栅极配线的区域。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第1及第2镀敷电极的厚度和材质彼此相同。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述第1及第2镀敷电极的厚度大于或等于1μm而小于或等于10μm。
4.根据权利要求1或2所述的半导体装置，其特征在于，
所述绝缘膜还设置在所述第1及第2表面电极与所述电极层之间，
在所述绝缘膜设置有多个通孔，
穿过所述多个通孔，所述第1及第2表面电极与所述电极层机械连接、电连接。
5.根据权利要求1或2所述的半导体装置，其特征在于，
所述绝缘膜是对终端区域进行保护的保护膜延展至动作单元区域而得到的。
6.根据权利要求1或2所述的半导体装置，其特征在于，
具备终端构造配线，该终端构造配线在终端区域形成于所述半导体衬底的所述表面，具有与所述第1及第2表面电极相同的厚度，
所述电极层未形成于所述终端区域。
7.根据权利要求6所述的半导体装置，其特征在于，
所述第1及第2表面电极以及所述终端构造配线的厚度比所述电极层的厚度薄。
8.根据权利要求1所述的半导体装置，其特征在于，
所述第1及第2接合材料包含锡。
9.根据权利要求1或2所述的半导体装置，其特征在于，
具备包覆所述第1镀敷电极的焊料接合区域的外周的包覆膜。
10.根据权利要求9所述的半导体装置，其特征在于，
所述包覆膜包含聚酰亚胺。
11.根据权利要求1或2所述的半导体装置，其特征在于，
还具备形成于所述绝缘膜之上的有机膜。
12.根据权利要求11所述的半导体装置，其特征在于，
所述有机膜包含聚酰亚胺。
13.根据权利要求1或2所述的半导体装置，其特征在于，
所述第1及第2表面电极以及所述背面电极由包含铝的材料形成。
14.根据权利要求1或2所述的半导体装置，其特征在于，
所述电极层由包含铝的材料形成。
15.根据权利要求1或2所述的半导体装置，其特征在于，
所述绝缘膜包含氮化硅。
16.根据权利要求1或2所述的半导体装置，其特征在于，
所述第1及第2镀敷电极包含镍或者铜。
17.根据权利要求1或2所述的半导体装置，其特征在于，
在所述第1及第2镀敷电极的最表面形成有包含金的材料。
18.根据权利要求1或2所述的半导体装置，其特征在于，
所述半导体衬底由宽带隙半导体形成。
19.一种半导体装置的制造方法，其特征在于，具备以下工序：
在半导体衬底的表面形成栅极配线以及通过所述栅极配线而彼此分割开的第1及第2表面电极；
形成覆盖所述栅极配线的绝缘膜；
跨过所述栅极配线而在所述绝缘膜以及所述第1及第2表面电极之上形成电极层；
在所述半导体衬底的背面形成背面电极；
通过镀敷法而同时分别在所述电极层之上形成第1镀敷电极，在所述背面电极之上形成第2镀敷电极；
通过第1接合材料将引线框与所述第1镀敷电极接合；
通过第2接合材料将导体基板与所述第2镀敷电极接合；以及
通过封装材料将所述半导体衬底、所述引线框以及所述导体基板的至少一部分包覆，
所述第1接合材料形成于避开了所述栅极配线的区域。
20.根据权利要求19所述的半导体装置的制造方法，其特征在于，
通过剥离法而将所述电极层图案化。
21.根据权利要求19所述的半导体装置的制造方法，其特征在于，
越过在电极层形成区域具有开口的掩模而对所述电极层进行堆叠，由此将所述电极层图案化。
22.根据权利要求19至21中任一项所述的半导体装置的制造方法，其特征在于，
将由以Ag为主要成分的材料构成的微粒烧结而将导体基板与所述第2镀敷电极接合。
23.根据权利要求19至21中任一项所述的半导体装置的制造方法，其特征在于，
通过将聚酰亚胺前驱体溶液向所述第1镀敷电极之上喷出、进行描绘而形成图案，进行固化，由此形成包覆所述第1镀敷电极的焊料接合区域的外周的包覆膜。
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